1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallSet.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/SparseBitVector.h"
43 class MachineRegisterInfo;
44 class TargetRegisterInfo;
46 class LiveVariables : public MachineFunctionPass {
48 static char ID; // Pass identification, replacement for typeid
49 LiveVariables() : MachineFunctionPass(ID) {
50 initializeLiveVariablesPass(*PassRegistry::getPassRegistry());
53 /// VarInfo - This represents the regions where a virtual register is live in
54 /// the program. We represent this with three different pieces of
55 /// information: the set of blocks in which the instruction is live
56 /// throughout, the set of blocks in which the instruction is actually used,
57 /// and the set of non-phi instructions that are the last users of the value.
59 /// In the common case where a value is defined and killed in the same block,
60 /// There is one killing instruction, and AliveBlocks is empty.
62 /// Otherwise, the value is live out of the block. If the value is live
63 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
64 /// where the liveness range ends are not included in AliveBlocks, instead
65 /// being captured by the Kills set. In these blocks, the value is live into
66 /// the block (unless the value is defined and killed in the same block) and
67 /// lives until the specified instruction. Note that there cannot ever be a
68 /// value whose Kills set contains two instructions from the same basic block.
70 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
71 /// value in one of its predecessor blocks, it is not listed in the kills set,
72 /// but does include the predecessor block in the AliveBlocks set (unless that
73 /// block also defines the value). This leads to the (perfectly sensical)
74 /// situation where a value is defined in a block, and the last use is a phi
75 /// node in the successor. In this case, AliveBlocks is empty (the value is
76 /// not live across any blocks) and Kills is empty (phi nodes are not
77 /// included). This is sensical because the value must be live to the end of
78 /// the block, but is not live in any successor blocks.
80 /// AliveBlocks - Set of blocks in which this value is alive completely
81 /// through. This is a bit set which uses the basic block number as an
84 SparseBitVector<> AliveBlocks;
86 /// NumUses - Number of uses of this register across the entire function.
90 /// Kills - List of MachineInstruction's which are the last use of this
91 /// virtual register (kill it) in their basic block.
93 std::vector<MachineInstr*> Kills;
95 VarInfo() : NumUses(0) {}
97 /// removeKill - Delete a kill corresponding to the specified
98 /// machine instruction. Returns true if there was a kill
99 /// corresponding to this instruction, false otherwise.
100 bool removeKill(MachineInstr *MI) {
101 std::vector<MachineInstr*>::iterator
102 I = std::find(Kills.begin(), Kills.end(), MI);
103 if (I == Kills.end())
109 /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
110 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
112 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
113 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
114 /// MBB, it is not considered live in.
115 bool isLiveIn(const MachineBasicBlock &MBB,
117 MachineRegisterInfo &MRI);
123 /// VirtRegInfo - This list is a mapping from virtual register number to
124 /// variable information. FirstVirtualRegister is subtracted from the virtual
125 /// register number before indexing into this list.
127 std::vector<VarInfo> VirtRegInfo;
129 /// PHIJoins - list of virtual registers that are PHI joins. These registers
130 /// may have multiple definitions, and they require special handling when
131 /// building live intervals.
132 SparseBitVector<> PHIJoins;
134 /// ReservedRegisters - This vector keeps track of which registers
135 /// are reserved register which are not allocatable by the target machine.
136 /// We can not track liveness for values that are in this set.
138 BitVector ReservedRegisters;
140 private: // Intermediate data structures
143 MachineRegisterInfo* MRI;
145 const TargetRegisterInfo *TRI;
147 // PhysRegInfo - Keep track of which instruction was the last def of a
148 // physical register. This is a purely local property, because all physical
149 // register references are presumed dead across basic blocks.
150 MachineInstr **PhysRegDef;
152 // PhysRegInfo - Keep track of which instruction was the last use of a
153 // physical register. This is a purely local property, because all physical
154 // register references are presumed dead across basic blocks.
155 MachineInstr **PhysRegUse;
157 SmallVector<unsigned, 4> *PHIVarInfo;
159 // DistanceMap - Keep track the distance of a MI from the start of the
160 // current basic block.
161 DenseMap<MachineInstr*, unsigned> DistanceMap;
163 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
164 /// uses. Pay special attention to the sub-register uses which may come below
165 /// the last use of the whole register.
166 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
168 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
169 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
170 SmallVector<unsigned, 4> &Defs);
171 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
173 /// FindLastRefOrPartRef - Return the last reference or partial reference of
174 /// the specified register.
175 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
177 /// FindLastPartialDef - Return the last partial def of the specified
178 /// register. Also returns the sub-registers that're defined by the
180 MachineInstr *FindLastPartialDef(unsigned Reg,
181 SmallSet<unsigned,4> &PartDefRegs);
183 /// analyzePHINodes - Gather information about the PHI nodes in here. In
184 /// particular, we want to map the variable information of a virtual
185 /// register which is used in a PHI node. We map that to the BB the vreg
187 void analyzePHINodes(const MachineFunction& Fn);
190 virtual bool runOnMachineFunction(MachineFunction &MF);
192 /// RegisterDefIsDead - Return true if the specified instruction defines the
193 /// specified register, but that definition is dead.
194 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
196 //===--------------------------------------------------------------------===//
197 // API to update live variable information
199 /// replaceKillInstruction - Update register kill info by replacing a kill
200 /// instruction with a new one.
201 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
202 MachineInstr *NewMI);
204 /// addVirtualRegisterKilled - Add information about the fact that the
205 /// specified register is killed after being used by the specified
206 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
208 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
209 bool AddIfNotFound = false) {
210 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
211 getVarInfo(IncomingReg).Kills.push_back(MI);
214 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
215 /// register from the live variable information. Returns true if the
216 /// variable was marked as killed by the specified instruction,
218 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
219 if (!getVarInfo(reg).removeKill(MI))
222 bool Removed = false;
223 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
224 MachineOperand &MO = MI->getOperand(i);
225 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
232 assert(Removed && "Register is not used by this instruction!");
236 /// removeVirtualRegistersKilled - Remove all killed info for the specified
238 void removeVirtualRegistersKilled(MachineInstr *MI);
240 /// addVirtualRegisterDead - Add information about the fact that the specified
241 /// register is dead after being used by the specified instruction. If
242 /// AddIfNotFound is true, add a implicit operand if it's not found.
243 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
244 bool AddIfNotFound = false) {
245 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
246 getVarInfo(IncomingReg).Kills.push_back(MI);
249 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
250 /// register from the live variable information. Returns true if the
251 /// variable was marked dead at the specified instruction, false
253 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
254 if (!getVarInfo(reg).removeKill(MI))
257 bool Removed = false;
258 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
259 MachineOperand &MO = MI->getOperand(i);
260 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
266 assert(Removed && "Register is not defined by this instruction!");
270 void getAnalysisUsage(AnalysisUsage &AU) const;
272 virtual void releaseMemory() {
276 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
278 VarInfo &getVarInfo(unsigned RegIdx);
280 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
281 MachineBasicBlock *BB);
282 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
283 MachineBasicBlock *BB,
284 std::vector<MachineBasicBlock*> &WorkList);
285 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
286 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
289 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
290 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
293 /// isLiveOut - Determine if Reg is live out from MBB, when not considering
294 /// PHI nodes. This means that Reg is either killed by a successor block or
295 /// passed through one.
296 bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
298 /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
299 /// variables that are live out of DomBB and live into SuccBB will be marked
300 /// as passing live through BB. This method assumes that the machine code is
301 /// still in SSA form.
302 void addNewBlock(MachineBasicBlock *BB,
303 MachineBasicBlock *DomBB,
304 MachineBasicBlock *SuccBB);
306 /// isPHIJoin - Return true if Reg is a phi join register.
307 bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
309 /// setPHIJoin - Mark Reg as a phi join register.
310 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
313 } // End llvm namespace