1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/SmallVector.h"
42 class LiveVariables : public MachineFunctionPass {
44 static char ID; // Pass identification, replacement for typeid
45 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {}
47 /// VarInfo - This represents the regions where a virtual register is live in
48 /// the program. We represent this with three different pieces of
49 /// information: the instruction that uniquely defines the value, the set of
50 /// blocks the instruction is live into and live out of, and the set of
51 /// non-phi instructions that are the last users of the value.
53 /// In the common case where a value is defined and killed in the same block,
54 /// DefInst is the defining inst, there is one killing instruction, and
55 /// AliveBlocks is empty.
57 /// Otherwise, the value is live out of the block. If the value is live
58 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
59 /// the liveness range ends are not included in AliveBlocks, instead being
60 /// captured by the Kills set. In these blocks, the value is live into the
61 /// block (unless the value is defined and killed in the same block) and lives
62 /// until the specified instruction. Note that there cannot ever be a value
63 /// whose Kills set contains two instructions from the same basic block.
65 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
66 /// value in one of its predecessor blocks, it is not listed in the kills set,
67 /// but does include the predecessor block in the AliveBlocks set (unless that
68 /// block also defines the value). This leads to the (perfectly sensical)
69 /// situation where a value is defined in a block, and the last use is a phi
70 /// node in the successor. In this case, DefInst will be the defining
71 /// instruction, AliveBlocks is empty (the value is not live across any
72 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
73 /// because the value must be live to the end of the block, but is not live in
74 /// any successor blocks.
76 /// DefInst - The machine instruction that defines this register.
78 MachineInstr *DefInst;
80 /// AliveBlocks - Set of blocks of which this value is alive completely
81 /// through. This is a bit set which uses the basic block number as an
84 BitVector AliveBlocks;
86 /// NumUses - Number of uses of this register across the entire function.
90 /// Kills - List of MachineInstruction's which are the last use of this
91 /// virtual register (kill it) in their basic block.
93 std::vector<MachineInstr*> Kills;
95 VarInfo() : DefInst(0), NumUses(0) {}
97 /// removeKill - Delete a kill corresponding to the specified
98 /// machine instruction. Returns true if there was a kill
99 /// corresponding to this instruction, false otherwise.
100 bool removeKill(MachineInstr *MI) {
101 for (std::vector<MachineInstr*>::iterator i = Kills.begin(),
102 e = Kills.end(); i != e; ++i)
114 /// VirtRegInfo - This list is a mapping from virtual register number to
115 /// variable information. FirstVirtualRegister is subtracted from the virtual
116 /// register number before indexing into this list.
118 std::vector<VarInfo> VirtRegInfo;
120 /// ReservedRegisters - This vector keeps track of which registers
121 /// are reserved register which are not allocatable by the target machine.
122 /// We can not track liveness for values that are in this set.
124 BitVector ReservedRegisters;
126 private: // Intermediate data structures
129 const MRegisterInfo *RegInfo;
131 // PhysRegInfo - Keep track of which instruction was the last def/use of a
132 // physical register. This is a purely local property, because all physical
133 // register references as presumed dead across basic blocks.
134 MachineInstr **PhysRegInfo;
136 // PhysRegUsed - Keep track whether the physical register has been used after
137 // its last definition. This is local property.
140 // PhysRegPartUse - Keep track of which instruction was the last partial use
141 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
142 // This is a purely local property.
143 MachineInstr **PhysRegPartUse;
145 // PhysRegPartDef - Keep track of a list of instructions which "partially"
146 // defined the physical register (e.g. on X86 AX partially defines EAX).
147 // These are turned into use/mod/write if there is a use of the register
148 // later in the same block. This is local property.
149 SmallVector<MachineInstr*, 4> *PhysRegPartDef;
151 SmallVector<unsigned, 4> *PHIVarInfo;
153 /// addRegisterKilled - We have determined MI kills a register. Look for the
154 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
155 /// add a implicit operand if it's not found. Returns true if the operand
156 /// exists / is added.
157 bool addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
158 bool AddIfNotFound = false);
160 /// addRegisterDead - We have determined MI defined a register without a use.
161 /// Look for the operand that defines it and mark it as IsDead. If
162 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
163 /// true if the operand exists / is added.
164 bool addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
165 bool AddIfNotFound = false);
167 void addRegisterKills(unsigned Reg, MachineInstr *MI,
168 SmallSet<unsigned, 4> &SubKills);
170 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
171 /// uses. Pay special attention to the sub-register uses which may come below
172 /// the last use of the whole register.
173 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI,
174 SmallSet<unsigned, 4> &SubKills);
175 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
176 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
177 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
179 /// analyzePHINodes - Gather information about the PHI nodes in here. In
180 /// particular, we want to map the variable information of a virtual
181 /// register which is used in a PHI node. We map that to the BB the vreg
183 void analyzePHINodes(const MachineFunction& Fn);
186 virtual bool runOnMachineFunction(MachineFunction &MF);
188 /// KillsRegister - Return true if the specified instruction kills the
189 /// specified register.
190 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
192 /// RegisterDefIsDead - Return true if the specified instruction defines the
193 /// specified register, but that definition is dead.
194 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
196 /// ModifiesRegister - Return true if the specified instruction modifies the
197 /// specified register.
198 bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
200 //===--------------------------------------------------------------------===//
201 // API to update live variable information
203 /// instructionChanged - When the address of an instruction changes, this
204 /// method should be called so that live variables can update its internal
205 /// data structures. This removes the records for OldMI, transfering them to
206 /// the records for NewMI.
207 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
209 /// addVirtualRegisterKilled - Add information about the fact that the
210 /// specified register is killed after being used by the specified
211 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
213 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
214 bool AddIfNotFound = false) {
215 if (addRegisterKilled(IncomingReg, MI, AddIfNotFound))
216 getVarInfo(IncomingReg).Kills.push_back(MI);
219 /// removeVirtualRegisterKilled - Remove the specified virtual
220 /// register from the live variable information. Returns true if the
221 /// variable was marked as killed by the specified instruction,
223 bool removeVirtualRegisterKilled(unsigned reg,
224 MachineBasicBlock *MBB,
226 if (!getVarInfo(reg).removeKill(MI))
229 bool Removed = false;
230 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
231 MachineOperand &MO = MI->getOperand(i);
232 if (MO.isReg() && MO.isUse() && MO.getReg() == reg) {
239 assert(Removed && "Register is not used by this instruction!");
243 /// removeVirtualRegistersKilled - Remove all killed info for the specified
245 void removeVirtualRegistersKilled(MachineInstr *MI);
247 /// addVirtualRegisterDead - Add information about the fact that the specified
248 /// register is dead after being used by the specified instruction. If
249 /// AddIfNotFound is true, add a implicit operand if it's not found.
250 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
251 bool AddIfNotFound = false) {
252 if (addRegisterDead(IncomingReg, MI, AddIfNotFound))
253 getVarInfo(IncomingReg).Kills.push_back(MI);
256 /// removeVirtualRegisterDead - Remove the specified virtual
257 /// register from the live variable information. Returns true if the
258 /// variable was marked dead at the specified instruction, false
260 bool removeVirtualRegisterDead(unsigned reg,
261 MachineBasicBlock *MBB,
263 if (!getVarInfo(reg).removeKill(MI))
266 bool Removed = false;
267 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
268 MachineOperand &MO = MI->getOperand(i);
269 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
275 assert(Removed && "Register is not defined by this instruction!");
279 /// removeVirtualRegistersDead - Remove all of the dead registers for the
280 /// specified instruction from the live variable information.
281 void removeVirtualRegistersDead(MachineInstr *MI);
283 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
284 AU.setPreservesAll();
287 virtual void releaseMemory() {
291 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
293 VarInfo &getVarInfo(unsigned RegIdx);
295 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
296 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB,
297 std::vector<MachineBasicBlock*> &WorkList);
298 void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
302 } // End llvm namespace