1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/SmallVector.h"
40 class MachineRegisterInfo;
41 class TargetRegisterInfo;
43 class LiveVariables : public MachineFunctionPass {
45 static char ID; // Pass identification, replacement for typeid
46 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {}
48 /// VarInfo - This represents the regions where a virtual register is live in
49 /// the program. We represent this with three different pieces of
50 /// information: the instruction that uniquely defines the value, the set of
51 /// blocks the instruction is live into and live out of, and the set of
52 /// non-phi instructions that are the last users of the value.
54 /// In the common case where a value is defined and killed in the same block,
55 /// DefInst is the defining inst, there is one killing instruction, and
56 /// AliveBlocks is empty.
58 /// Otherwise, the value is live out of the block. If the value is live
59 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
60 /// the liveness range ends are not included in AliveBlocks, instead being
61 /// captured by the Kills set. In these blocks, the value is live into the
62 /// block (unless the value is defined and killed in the same block) and lives
63 /// until the specified instruction. Note that there cannot ever be a value
64 /// whose Kills set contains two instructions from the same basic block.
66 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
67 /// value in one of its predecessor blocks, it is not listed in the kills set,
68 /// but does include the predecessor block in the AliveBlocks set (unless that
69 /// block also defines the value). This leads to the (perfectly sensical)
70 /// situation where a value is defined in a block, and the last use is a phi
71 /// node in the successor. In this case, DefInst will be the defining
72 /// instruction, AliveBlocks is empty (the value is not live across any
73 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
74 /// because the value must be live to the end of the block, but is not live in
75 /// any successor blocks.
77 /// DefInst - The machine instruction that defines this register.
79 MachineInstr *DefInst;
81 /// AliveBlocks - Set of blocks of which this value is alive completely
82 /// through. This is a bit set which uses the basic block number as an
85 BitVector AliveBlocks;
87 /// UsedBlocks - Set of blocks of which this value is actually used. This
88 /// is a bit set which uses the basic block number as an index.
91 /// NumUses - Number of uses of this register across the entire function.
95 /// Kills - List of MachineInstruction's which are the last use of this
96 /// virtual register (kill it) in their basic block.
98 std::vector<MachineInstr*> Kills;
100 VarInfo() : DefInst(0), NumUses(0) {}
102 /// removeKill - Delete a kill corresponding to the specified
103 /// machine instruction. Returns true if there was a kill
104 /// corresponding to this instruction, false otherwise.
105 bool removeKill(MachineInstr *MI) {
106 std::vector<MachineInstr*>::iterator
107 I = std::find(Kills.begin(), Kills.end(), MI);
108 if (I == Kills.end())
118 /// VirtRegInfo - This list is a mapping from virtual register number to
119 /// variable information. FirstVirtualRegister is subtracted from the virtual
120 /// register number before indexing into this list.
122 std::vector<VarInfo> VirtRegInfo;
124 /// ReservedRegisters - This vector keeps track of which registers
125 /// are reserved register which are not allocatable by the target machine.
126 /// We can not track liveness for values that are in this set.
128 BitVector ReservedRegisters;
130 private: // Intermediate data structures
133 MachineRegisterInfo* MRI;
135 const TargetRegisterInfo *TRI;
137 // PhysRegInfo - Keep track of which instruction was the last def of a
138 // physical register. This is a purely local property, because all physical
139 // register references are presumed dead across basic blocks.
140 MachineInstr **PhysRegDef;
142 // PhysRegInfo - Keep track of which instruction was the last use of a
143 // physical register. This is a purely local property, because all physical
144 // register references are presumed dead across basic blocks.
145 MachineInstr **PhysRegUse;
147 SmallVector<unsigned, 4> *PHIVarInfo;
149 // DistanceMap - Keep track the distance of a MI from the start of the
150 // current basic block.
151 DenseMap<MachineInstr*, unsigned> DistanceMap;
153 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
154 /// uses. Pay special attention to the sub-register uses which may come below
155 /// the last use of the whole register.
156 bool HandlePhysRegKill(unsigned Reg);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
161 /// FindLastPartialDef - Return the last partial def of the specified register.
162 /// Also returns the sub-register that's defined.
163 MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
165 /// hasRegisterUseBelow - Return true if the specified register is used after
166 /// the current instruction and before it's next definition.
167 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
168 MachineBasicBlock *MBB);
170 /// analyzePHINodes - Gather information about the PHI nodes in here. In
171 /// particular, we want to map the variable information of a virtual
172 /// register which is used in a PHI node. We map that to the BB the vreg
174 void analyzePHINodes(const MachineFunction& Fn);
177 virtual bool runOnMachineFunction(MachineFunction &MF);
179 /// RegisterDefIsDead - Return true if the specified instruction defines the
180 /// specified register, but that definition is dead.
181 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
183 //===--------------------------------------------------------------------===//
184 // API to update live variable information
186 /// instructionChanged - When the address of an instruction changes, this
187 /// method should be called so that live variables can update its internal
188 /// data structures. This removes the records for OldMI, transfering them to
189 /// the records for NewMI.
190 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
192 /// addVirtualRegisterKilled - Add information about the fact that the
193 /// specified register is killed after being used by the specified
194 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
196 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
197 bool AddIfNotFound = false) {
198 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
199 getVarInfo(IncomingReg).Kills.push_back(MI);
202 /// removeVirtualRegisterKilled - Remove the specified virtual
203 /// register from the live variable information. Returns true if the
204 /// variable was marked as killed by the specified instruction,
206 bool removeVirtualRegisterKilled(unsigned reg,
207 MachineBasicBlock *MBB,
209 if (!getVarInfo(reg).removeKill(MI))
212 bool Removed = false;
213 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
214 MachineOperand &MO = MI->getOperand(i);
215 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
222 assert(Removed && "Register is not used by this instruction!");
226 /// removeVirtualRegistersKilled - Remove all killed info for the specified
228 void removeVirtualRegistersKilled(MachineInstr *MI);
230 /// addVirtualRegisterDead - Add information about the fact that the specified
231 /// register is dead after being used by the specified instruction. If
232 /// AddIfNotFound is true, add a implicit operand if it's not found.
233 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
234 bool AddIfNotFound = false) {
235 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
236 getVarInfo(IncomingReg).Kills.push_back(MI);
239 /// removeVirtualRegisterDead - Remove the specified virtual
240 /// register from the live variable information. Returns true if the
241 /// variable was marked dead at the specified instruction, false
243 bool removeVirtualRegisterDead(unsigned reg,
244 MachineBasicBlock *MBB,
246 if (!getVarInfo(reg).removeKill(MI))
249 bool Removed = false;
250 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
251 MachineOperand &MO = MI->getOperand(i);
252 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
258 assert(Removed && "Register is not defined by this instruction!");
262 /// removeVirtualRegistersDead - Remove all of the dead registers for the
263 /// specified instruction from the live variable information.
264 void removeVirtualRegistersDead(MachineInstr *MI);
266 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
267 AU.setPreservesAll();
270 virtual void releaseMemory() {
274 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
276 VarInfo &getVarInfo(unsigned RegIdx);
278 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
279 MachineBasicBlock *BB);
280 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
281 MachineBasicBlock *BB,
282 std::vector<MachineBasicBlock*> &WorkList);
283 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
287 } // End llvm namespace