1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
39 class LiveVariables : public MachineFunctionPass {
42 /// DefInst - The machine instruction that defines this register.
44 MachineInstr *DefInst;
46 /// AliveBlocks - Set of blocks of which this value is alive completely
47 /// through. This is a bit set which uses the basic block number as an
50 std::vector<bool> AliveBlocks;
52 /// Kills - List of MachineInstruction's which are the last use of this
53 /// virtual register (kill it) in their basic block.
55 std::vector<MachineInstr*> Kills;
57 VarInfo() : DefInst(0) {}
59 /// removeKill - Delete a kill corresponding to the specified
60 /// machine instruction. Returns true if there was a kill
61 /// corresponding to this instruction, false otherwise.
62 bool removeKill(MachineInstr *MI) {
63 for (std::vector<MachineInstr*>::iterator i = Kills.begin(),
64 e = Kills.end(); i != e; ++i)
74 /// VirtRegInfo - This list is a mapping from virtual register number to
75 /// variable information. FirstVirtualRegister is subtracted from the virtual
76 /// register number before indexing into this list.
78 std::vector<VarInfo> VirtRegInfo;
80 /// RegistersKilled - This map keeps track of all of the registers that
81 /// are dead immediately after an instruction reads its operands. If an
82 /// instruction does not have an entry in this map, it kills no registers.
84 std::map<MachineInstr*, std::vector<unsigned> > RegistersKilled;
86 /// RegistersDead - This map keeps track of all of the registers that are
87 /// dead immediately after an instruction executes, which are not dead after
88 /// the operands are evaluated. In practice, this only contains registers
89 /// which are defined by an instruction, but never used.
91 std::map<MachineInstr*, std::vector<unsigned> > RegistersDead;
93 /// Dummy - An always empty vector used for instructions without dead or
95 std::vector<unsigned> Dummy;
97 /// AllocatablePhysicalRegisters - This vector keeps track of which registers
98 /// are actually register allocatable by the target machine. We can not track
99 /// liveness for values that are not in this set.
101 std::vector<bool> AllocatablePhysicalRegisters;
103 private: // Intermediate data structures
104 const MRegisterInfo *RegInfo;
106 MachineInstr **PhysRegInfo;
109 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
110 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
114 virtual bool runOnMachineFunction(MachineFunction &MF);
116 /// killed_iterator - Iterate over registers killed by a machine instruction
118 typedef std::vector<unsigned>::iterator killed_iterator;
120 std::vector<unsigned> &getKillsVector(MachineInstr *MI) {
121 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
122 RegistersKilled.find(MI);
123 return I != RegistersKilled.end() ? I->second : Dummy;
125 std::vector<unsigned> &getDeadDefsVector(MachineInstr *MI) {
126 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
127 RegistersDead.find(MI);
128 return I != RegistersDead.end() ? I->second : Dummy;
132 /// killed_begin/end - Get access to the range of registers killed by a
133 /// machine instruction.
134 killed_iterator killed_begin(MachineInstr *MI) {
135 return getKillsVector(MI).begin();
137 killed_iterator killed_end(MachineInstr *MI) {
138 return getKillsVector(MI).end();
140 std::pair<killed_iterator, killed_iterator>
141 killed_range(MachineInstr *MI) {
142 std::vector<unsigned> &V = getKillsVector(MI);
143 return std::make_pair(V.begin(), V.end());
146 /// KillsRegister - Return true if the specified instruction kills the
147 /// specified register.
148 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
150 killed_iterator dead_begin(MachineInstr *MI) {
151 return getDeadDefsVector(MI).begin();
153 killed_iterator dead_end(MachineInstr *MI) {
154 return getDeadDefsVector(MI).end();
156 std::pair<killed_iterator, killed_iterator>
157 dead_range(MachineInstr *MI) {
158 std::vector<unsigned> &V = getDeadDefsVector(MI);
159 return std::make_pair(V.begin(), V.end());
162 /// RegisterDefIsDead - Return true if the specified instruction defines the
163 /// specified register, but that definition is dead.
164 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
166 //===--------------------------------------------------------------------===//
167 // API to update live variable information
169 /// instructionChanged - When the address of an instruction changes, this
170 /// method should be called so that live variables can update its internal
171 /// data structures. This removes the records for OldMI, transfering them to
172 /// the records for NewMI.
173 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
175 /// addVirtualRegisterKilled - Add information about the fact that the
176 /// specified register is killed after being used by the specified
179 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
180 std::vector<unsigned> &V = RegistersKilled[MI];
181 // Insert in a sorted order.
182 if (V.empty() || IncomingReg > V.back()) {
183 V.push_back(IncomingReg);
185 std::vector<unsigned>::iterator I = V.begin();
186 for (; *I < IncomingReg; ++I)
188 if (*I != IncomingReg) // Don't insert duplicates.
189 V.insert(I, IncomingReg);
191 getVarInfo(IncomingReg).Kills.push_back(MI);
194 /// removeVirtualRegisterKilled - Remove the specified virtual
195 /// register from the live variable information. Returns true if the
196 /// variable was marked as killed by the specified instruction,
198 bool removeVirtualRegisterKilled(unsigned reg,
199 MachineBasicBlock *MBB,
201 if (!getVarInfo(reg).removeKill(MI))
204 std::vector<unsigned> &V = getKillsVector(MI);
205 for (unsigned i = 0, e = V.size(); i != e; ++i)
207 V.erase(V.begin()+i);
213 /// removeVirtualRegistersKilled - Remove all killed info for the specified
215 void removeVirtualRegistersKilled(MachineInstr *MI) {
216 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
217 RegistersKilled.find(MI);
218 if (I != RegistersKilled.end()) {
219 std::vector<unsigned> &Regs = I->second;
220 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
221 bool removed = getVarInfo(Regs[i]).removeKill(MI);
222 assert(removed && "kill not in register's VarInfo?");
224 RegistersKilled.erase(I);
228 /// addVirtualRegisterDead - Add information about the fact that the specified
229 /// register is dead after being used by the specified instruction.
231 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
232 std::vector<unsigned> &V = RegistersDead[MI];
233 // Insert in a sorted order.
234 if (V.empty() || IncomingReg > V.back()) {
235 V.push_back(IncomingReg);
237 std::vector<unsigned>::iterator I = V.begin();
238 for (; *I < IncomingReg; ++I)
240 if (*I != IncomingReg) // Don't insert duplicates.
241 V.insert(I, IncomingReg);
243 getVarInfo(IncomingReg).Kills.push_back(MI);
246 /// removeVirtualRegisterDead - Remove the specified virtual
247 /// register from the live variable information. Returns true if the
248 /// variable was marked dead at the specified instruction, false
250 bool removeVirtualRegisterDead(unsigned reg,
251 MachineBasicBlock *MBB,
253 if (!getVarInfo(reg).removeKill(MI))
256 std::vector<unsigned> &V = getDeadDefsVector(MI);
257 for (unsigned i = 0, e = V.size(); i != e; ++i)
259 V.erase(V.begin()+i);
265 /// removeVirtualRegistersDead - Remove all of the specified dead
266 /// registers from the live variable information.
267 void removeVirtualRegistersDead(MachineInstr *MI) {
268 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
269 RegistersDead.find(MI);
270 if (I != RegistersDead.end()) {
271 std::vector<unsigned> &Regs = I->second;
272 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
273 bool removed = getVarInfo(Regs[i]).removeKill(MI);
274 assert(removed && "kill not in register's VarInfo?");
276 RegistersDead.erase(I);
280 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
281 AU.setPreservesAll();
284 virtual void releaseMemory() {
286 RegistersKilled.clear();
287 RegistersDead.clear();
290 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
292 VarInfo &getVarInfo(unsigned RegIdx);
294 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
295 void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
299 } // End llvm namespace