1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
18 class MachineBasicBlock;
20 typedef int MachineOpCode;
22 //---------------------------------------------------------------------------
23 // class MachineOperand
26 // Representation of each machine instruction operand.
27 // This class is designed so that you can allocate a vector of operands
28 // first and initialize each one later.
30 // E.g, for this VM instruction:
31 // ptr = alloca type, numElements
32 // we generate 2 machine instructions on the SPARC:
34 // mul Constant, Numelements -> Reg
35 // add %sp, Reg -> Ptr
37 // Each instruction has 3 operands, listed above. Of those:
38 // - Reg, NumElements, and Ptr are of operand type MO_Register.
39 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
41 // For the register operands, the virtual register type is as follows:
43 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
44 // MachineInstr* minstr will point to the instruction that computes reg.
46 // - %sp will be of virtual register type MO_MachineReg.
47 // The field regNum identifies the machine register.
49 // - NumElements will be of virtual register type MO_VirtualReg.
50 // The field Value* value identifies the value.
52 // - Ptr will also be of virtual register type MO_VirtualReg.
53 // Again, the field Value* value identifies the value.
55 //---------------------------------------------------------------------------
57 class MachineOperand {
59 enum MachineOperandType {
60 MO_VirtualRegister, // virtual register for *value
61 MO_MachineRegister, // pre-assigned machine register `regNum'
69 // Bit fields of the flags variable used for different operand properties
70 static const char DEFFLAG = 0x1; // this is a def of the operand
71 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
72 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
73 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
74 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
75 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
88 char flags; // see bit field definitions above
89 int regNum; // register number for an explicit register
90 // will be set for a value after reg allocation
94 opType(MO_VirtualRegister),
98 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
104 MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
107 flags(isDef ? DEFFLAG : 0),
110 MachineOperand(Value *V, MachineOperandType OpTy,
111 bool isDef = false, bool isDNU = false)
115 flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
119 MachineOperand(const MachineOperand &M)
120 : immedVal(M.immedVal),
127 // Accessor methods. Caller is responsible for checking the
128 // operand type before invoking the corresponding accessor.
130 MachineOperandType getType() const { return opType; }
132 inline Value* getVRegValue () const {
133 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
134 opType == MO_PCRelativeDisp);
137 inline Value* getVRegValueOrNull() const {
138 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
139 opType == MO_PCRelativeDisp)? value : NULL;
141 inline int getMachineRegNum() const {
142 assert(opType == MO_MachineRegister);
145 inline int64_t getImmedValue () const {
146 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
149 bool opIsDef () const { return flags & DEFFLAG; }
150 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
151 bool opHiBits32 () const { return flags & HIFLAG32; }
152 bool opLoBits32 () const { return flags & LOFLAG32; }
153 bool opHiBits64 () const { return flags & HIFLAG64; }
154 bool opLoBits64 () const { return flags & LOFLAG64; }
156 // used to check if a machine register has been allocated to this operand
157 inline bool hasAllocatedReg() const {
158 return (regNum >= 0 &&
159 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
160 opType == MO_MachineRegister));
163 // used to get the reg number if when one is allocated
164 inline int getAllocatedRegNum() const {
165 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
166 opType == MO_MachineRegister);
171 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
175 // Construction methods needed for fine-grain control.
176 // These must be accessed via coresponding methods in MachineInstr.
177 void markDef() { flags |= DEFFLAG; }
178 void markDefAndUse() { flags |= DEFUSEFLAG; }
179 void markHi32() { flags |= HIFLAG32; }
180 void markLo32() { flags |= LOFLAG32; }
181 void markHi64() { flags |= HIFLAG64; }
182 void markLo64() { flags |= LOFLAG64; }
184 // Replaces the Value with its corresponding physical register after
185 // register allocation is complete
186 void setRegForValue(int reg) {
187 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
188 opType == MO_MachineRegister);
192 friend class MachineInstr;
196 //---------------------------------------------------------------------------
197 // class MachineInstr
200 // Representation of each machine instruction.
202 // MachineOpCode must be an enum, defined separately for each target.
203 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
205 // There are 2 kinds of operands:
207 // (1) Explicit operands of the machine instruction in vector operands[]
209 // (2) "Implicit operands" are values implicitly used or defined by the
210 // machine instruction, such as arguments to a CALL, return value of
211 // a CALL (if any), and return value of a RETURN.
212 //---------------------------------------------------------------------------
214 class MachineInstr: public NonCopyable { // Disable copy operations
216 MachineOpCode opCode; // the opcode
217 std::vector<MachineOperand> operands; // the operands
218 unsigned numImplicitRefs; // number of implicit operands
220 MachineOperand& getImplicitOp(unsigned i) {
221 assert(i < numImplicitRefs && "implicit ref# out of range!");
222 return operands[i + operands.size() - numImplicitRefs];
224 const MachineOperand& getImplicitOp(unsigned i) const {
225 assert(i < numImplicitRefs && "implicit ref# out of range!");
226 return operands[i + operands.size() - numImplicitRefs];
229 // regsUsed - all machine registers used for this instruction, including regs
230 // used to save values across the instruction. This is a bitset of registers.
231 std::vector<bool> regsUsed;
233 // OperandComplete - Return true if it's illegal to add a new operand
234 bool OperandsComplete() const;
237 MachineInstr(MachineOpCode Opcode);
238 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
240 /// MachineInstr ctor - This constructor only does a _reserve_ of the
241 /// operands, not a resize for them. It is expected that if you use this that
242 /// you call add* methods below to fill up the operands, instead of the Set
243 /// methods. Eventually, the "resizing" ctors will be phased out.
245 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
247 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
248 /// the MachineInstr is created and added to the end of the specified basic
251 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
254 /// replace - Support to rewrite a machine instruction in place: for now,
255 /// simply replace() and then set new operands with Set.*Operand methods
258 void replace(MachineOpCode Opcode, unsigned numOperands);
262 const MachineOpCode getOpcode() const { return opCode; }
263 const MachineOpCode getOpCode() const { return opCode; }
266 // Information about explicit operands of the instruction
268 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
270 const MachineOperand& getOperand(unsigned i) const {
271 assert(i < getNumOperands() && "getOperand() out of range!");
274 MachineOperand& getOperand(unsigned i) {
275 assert(i < getNumOperands() && "getOperand() out of range!");
279 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
280 return getOperand(i).getType();
283 bool operandIsDefined(unsigned i) const {
284 return getOperand(i).opIsDef();
287 bool operandIsDefinedAndUsed(unsigned i) const {
288 return getOperand(i).opIsDefAndUse();
292 // Information about implicit operands of the instruction
294 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
296 const Value* getImplicitRef(unsigned i) const {
297 return getImplicitOp(i).getVRegValue();
299 Value* getImplicitRef(unsigned i) {
300 return getImplicitOp(i).getVRegValue();
303 bool implicitRefIsDefined(unsigned i) const {
304 return getImplicitOp(i).opIsDef();
306 bool implicitRefIsDefinedAndUsed(unsigned i) const {
307 return getImplicitOp(i).opIsDefAndUse();
309 inline void addImplicitRef (Value* V,
310 bool isDef=false,bool isDefAndUse=false);
311 inline void setImplicitRef (unsigned i, Value* V,
312 bool isDef=false, bool isDefAndUse=false);
315 // Information about registers used in this instruction
317 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
319 // insertUsedReg - Add a register to the Used registers set...
320 void insertUsedReg(unsigned Reg) {
321 if (Reg >= regsUsed.size())
322 regsUsed.resize(Reg+1);
323 regsUsed[Reg] = true;
330 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
333 // Define iterators to access the Value operands of the Machine Instruction.
334 // Note that these iterators only enumerate the explicit operands.
335 // begin() and end() are defined to produce these iterators...
337 template<class _MI, class _V> class ValOpIterator;
338 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
339 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
341 // Access to set the operands when building the machine instruction
343 void SetMachineOperandVal (unsigned i,
344 MachineOperand::MachineOperandType operandType,
347 bool isDefAndUse=false);
349 void SetMachineOperandConst (unsigned i,
350 MachineOperand::MachineOperandType operandType,
353 void SetMachineOperandReg (unsigned i,
357 //===--------------------------------------------------------------------===//
358 // Accessors to add operands when building up machine instructions
361 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
364 void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
365 assert(!OperandsComplete() &&
366 "Trying to add an operand to a machine instr that is already done!");
367 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
368 isDef, isDefAndUse));
371 /// addRegOperand - Add a symbolic virtual register reference...
373 void addRegOperand(int reg) {
374 assert(!OperandsComplete() &&
375 "Trying to add an operand to a machine instr that is already done!");
376 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
379 /// addPCDispOperand - Add a PC relative displacement operand to the MI
381 void addPCDispOperand(Value *V) {
382 assert(!OperandsComplete() &&
383 "Trying to add an operand to a machine instr that is already done!");
384 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
387 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
389 void addMachineRegOperand(int reg, bool isDef=false) {
390 assert(!OperandsComplete() &&
391 "Trying to add an operand to a machine instr that is already done!");
392 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
397 /// addZeroExtImmOperand - Add a zero extended constant argument to the
398 /// machine instruction.
400 void addZeroExtImmOperand(int64_t intValue) {
401 assert(!OperandsComplete() &&
402 "Trying to add an operand to a machine instr that is already done!");
403 operands.push_back(MachineOperand(intValue,
404 MachineOperand::MO_UnextendedImmed));
407 /// addSignExtImmOperand - Add a zero extended constant argument to the
408 /// machine instruction.
410 void addSignExtImmOperand(int64_t intValue) {
411 assert(!OperandsComplete() &&
412 "Trying to add an operand to a machine instr that is already done!");
413 operands.push_back(MachineOperand(intValue,
414 MachineOperand::MO_SignExtendedImmed));
418 unsigned substituteValue(const Value* oldVal, Value* newVal,
419 bool defsOnly = true);
421 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
422 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
423 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
424 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
427 // SetRegForOperand - Replaces the Value for the operand with its allocated
428 // physical register after register allocation is complete.
430 void SetRegForOperand(unsigned i, int regNum);
433 // Iterator to enumerate machine operands.
435 template<class MITy, class VTy>
436 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
440 void skipToNextVal() {
441 while (i < MI->getNumOperands() &&
442 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
443 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
444 && MI->getOperand(i).getVRegValue() != 0))
448 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
453 typedef ValOpIterator<MITy, VTy> _Self;
455 inline VTy operator*() const {
456 return MI->getOperand(i).getVRegValue();
459 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
460 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
462 inline VTy operator->() const { return operator*(); }
464 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
465 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
467 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
468 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
470 inline bool operator==(const _Self &y) const {
473 inline bool operator!=(const _Self &y) const {
474 return !operator==(y);
477 static _Self begin(MITy MI) {
480 static _Self end(MITy MI) {
481 return _Self(MI, MI->getNumOperands());
485 // define begin() and end()
486 val_op_iterator begin() { return val_op_iterator::begin(this); }
487 val_op_iterator end() { return val_op_iterator::end(this); }
489 const_val_op_iterator begin() const {
490 return const_val_op_iterator::begin(this);
492 const_val_op_iterator end() const {
493 return const_val_op_iterator::end(this);
498 // Define here to enable inlining of the functions used.
500 void MachineInstr::addImplicitRef(Value* V,
505 addRegOperand(V, isDef, isDefAndUse);
508 void MachineInstr::setImplicitRef(unsigned i,
513 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
514 SetMachineOperandVal(i + getNumImplicitRefs(),
515 MachineOperand::MO_VirtualRegister,
516 V, isDef, isDefAndUse);
520 //---------------------------------------------------------------------------
522 //---------------------------------------------------------------------------
524 std::ostream& operator<< (std::ostream& os,
525 const MachineInstr& minstr);
527 std::ostream& operator<< (std::ostream& os,
528 const MachineOperand& mop);
530 void PrintMachineInstructions (const Function *F);