1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
56 FrameSetup = 1 << 0 // Instruction is used as a part of
57 // function frame setup code.
60 const TargetInstrDesc *TID; // Instruction descriptor.
61 uint16_t NumImplicitOps; // Number of implicit operands (which
62 // are determined at construction time).
64 uint8_t Flags; // Various bits of additional
65 // information about machine
68 uint8_t AsmPrinterFlags; // Various bits of information used by
69 // the AsmPrinter to emit helpful
70 // comments. This is *not* semantic
71 // information. Do not use this for
72 // anything other than to convey comment
73 // information to AsmPrinter.
75 std::vector<MachineOperand> Operands; // the operands
76 mmo_iterator MemRefs; // information on memory references
77 mmo_iterator MemRefsEnd;
78 MachineBasicBlock *Parent; // Pointer to the owning basic block.
79 DebugLoc debugLoc; // Source line information.
81 // OperandComplete - Return true if it's illegal to add a new operand
82 bool OperandsComplete() const;
84 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
85 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
87 // Intrusive list support
88 friend struct ilist_traits<MachineInstr>;
89 friend struct ilist_traits<MachineBasicBlock>;
90 void setParent(MachineBasicBlock *P) { Parent = P; }
92 /// MachineInstr ctor - This constructor creates a copy of the given
93 /// MachineInstr in the given MachineFunction.
94 MachineInstr(MachineFunction &, const MachineInstr &);
96 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
97 /// TID NULL and no operands.
100 // The next two constructors have DebugLoc and non-DebugLoc versions;
101 // over time, the non-DebugLoc versions should be phased out and eventually
104 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
105 /// implicit operands. It reserves space for the number of operands specified
106 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
107 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
109 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
110 /// the MachineInstr is created and added to the end of the specified basic
111 /// block. The version with a DebugLoc should be preferred.
112 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
114 /// MachineInstr ctor - This constructor create a MachineInstr and add the
115 /// implicit operands. It reserves space for number of operands specified by
116 /// TargetInstrDesc. An explicit DebugLoc is supplied.
117 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
120 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
121 /// the MachineInstr is created and added to the end of the specified basic
123 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
124 const TargetInstrDesc &TID);
128 // MachineInstrs are pool-allocated and owned by MachineFunction.
129 friend class MachineFunction;
132 const MachineBasicBlock* getParent() const { return Parent; }
133 MachineBasicBlock* getParent() { return Parent; }
135 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
137 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
139 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
141 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
143 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
145 bool getAsmPrinterFlag(CommentFlag Flag) const {
146 return AsmPrinterFlags & Flag;
149 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
151 void setAsmPrinterFlag(CommentFlag Flag) {
152 AsmPrinterFlags |= (uint8_t)Flag;
155 /// getFlags - Return the MI flags bitvector.
156 uint8_t getFlags() const {
160 /// getFlag - Return whether an MI flag is set.
161 bool getFlag(MIFlag Flag) const {
165 /// setFlag - Set a MI flag.
166 void setFlag(MIFlag Flag) {
167 Flags |= (uint8_t)Flag;
170 void setFlags(unsigned flags) {
174 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
176 void clearAsmPrinterFlag(CommentFlag Flag) {
177 AsmPrinterFlags &= ~Flag;
180 /// getDebugLoc - Returns the debug location id of this MachineInstr.
182 DebugLoc getDebugLoc() const { return debugLoc; }
184 /// getDesc - Returns the target instruction descriptor of this
186 const TargetInstrDesc &getDesc() const { return *TID; }
188 /// getOpcode - Returns the opcode of this MachineInstr.
190 int getOpcode() const { return TID->Opcode; }
192 /// Access to explicit operands of the instruction.
194 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
196 const MachineOperand& getOperand(unsigned i) const {
197 assert(i < getNumOperands() && "getOperand() out of range!");
200 MachineOperand& getOperand(unsigned i) {
201 assert(i < getNumOperands() && "getOperand() out of range!");
205 /// getNumExplicitOperands - Returns the number of non-implicit operands.
207 unsigned getNumExplicitOperands() const;
209 /// iterator/begin/end - Iterate over all operands of a machine instruction.
210 typedef std::vector<MachineOperand>::iterator mop_iterator;
211 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
213 mop_iterator operands_begin() { return Operands.begin(); }
214 mop_iterator operands_end() { return Operands.end(); }
216 const_mop_iterator operands_begin() const { return Operands.begin(); }
217 const_mop_iterator operands_end() const { return Operands.end(); }
219 /// Access to memory operands of the instruction
220 mmo_iterator memoperands_begin() const { return MemRefs; }
221 mmo_iterator memoperands_end() const { return MemRefsEnd; }
222 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
224 /// hasOneMemOperand - Return true if this instruction has exactly one
225 /// MachineMemOperand.
226 bool hasOneMemOperand() const {
227 return MemRefsEnd - MemRefs == 1;
231 CheckDefs, // Check all operands for equality
232 IgnoreDefs, // Ignore all definitions
233 IgnoreVRegDefs // Ignore virtual register definitions
236 /// isIdenticalTo - Return true if this instruction is identical to (same
237 /// opcode and same operands as) the specified instruction.
238 bool isIdenticalTo(const MachineInstr *Other,
239 MICheckType Check = CheckDefs) const;
241 /// removeFromParent - This method unlinks 'this' from the containing basic
242 /// block, and returns it, but does not delete it.
243 MachineInstr *removeFromParent();
245 /// eraseFromParent - This method unlinks 'this' from the containing basic
246 /// block and deletes it.
247 void eraseFromParent();
249 /// isLabel - Returns true if the MachineInstr represents a label.
251 bool isLabel() const {
252 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
253 getOpcode() == TargetOpcode::EH_LABEL ||
254 getOpcode() == TargetOpcode::GC_LABEL;
257 bool isPrologLabel() const {
258 return getOpcode() == TargetOpcode::PROLOG_LABEL;
260 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
261 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
262 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
264 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
265 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
266 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
267 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
268 bool isStackAligningInlineAsm() const;
269 bool isInsertSubreg() const {
270 return getOpcode() == TargetOpcode::INSERT_SUBREG;
272 bool isSubregToReg() const {
273 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
275 bool isRegSequence() const {
276 return getOpcode() == TargetOpcode::REG_SEQUENCE;
278 bool isCopy() const {
279 return getOpcode() == TargetOpcode::COPY;
282 /// isCopyLike - Return true if the instruction behaves like a copy.
283 /// This does not include native copy instructions.
284 bool isCopyLike() const {
285 return isCopy() || isSubregToReg();
288 /// isIdentityCopy - Return true is the instruction is an identity copy.
289 bool isIdentityCopy() const {
290 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
291 getOperand(0).getSubReg() == getOperand(1).getSubReg();
294 /// readsRegister - Return true if the MachineInstr reads the specified
295 /// register. If TargetRegisterInfo is passed, then it also checks if there
296 /// is a read of a super-register.
297 /// This does not count partial redefines of virtual registers as reads:
299 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
300 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
303 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
304 /// virtual register. Take into account that a partial define is a
305 /// read-modify-write operation.
306 bool readsVirtualRegister(unsigned Reg) const {
307 return readsWritesVirtualRegister(Reg).first;
310 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
311 /// indicating if this instruction reads or writes Reg. This also considers
313 /// If Ops is not null, all operand indices for Reg are added.
314 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
315 SmallVectorImpl<unsigned> *Ops = 0) const;
317 /// killsRegister - Return true if the MachineInstr kills the specified
318 /// register. If TargetRegisterInfo is passed, then it also checks if there is
319 /// a kill of a super-register.
320 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
321 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
324 /// definesRegister - Return true if the MachineInstr fully defines the
325 /// specified register. If TargetRegisterInfo is passed, then it also checks
326 /// if there is a def of a super-register.
327 /// NOTE: It's ignoring subreg indices on virtual registers.
328 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
329 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
332 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
333 /// or partially define) the specified register.
334 /// NOTE: It's ignoring subreg indices on virtual registers.
335 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
336 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
339 /// registerDefIsDead - Returns true if the register is dead in this machine
340 /// instruction. If TargetRegisterInfo is passed, then it also checks
341 /// if there is a dead def of a super-register.
342 bool registerDefIsDead(unsigned Reg,
343 const TargetRegisterInfo *TRI = NULL) const {
344 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
347 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
348 /// the specific register or -1 if it is not found. It further tightens
349 /// the search criteria to a use that kills the register if isKill is true.
350 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
351 const TargetRegisterInfo *TRI = NULL) const;
353 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
354 /// a pointer to the MachineOperand rather than an index.
355 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
356 const TargetRegisterInfo *TRI = NULL) {
357 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
358 return (Idx == -1) ? NULL : &getOperand(Idx);
361 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
362 /// the specified register or -1 if it is not found. If isDead is true, defs
363 /// that are not dead are skipped. If Overlap is true, then it also looks for
364 /// defs that merely overlap the specified register. If TargetRegisterInfo is
365 /// non-null, then it also checks if there is a def of a super-register.
366 int findRegisterDefOperandIdx(unsigned Reg,
367 bool isDead = false, bool Overlap = false,
368 const TargetRegisterInfo *TRI = NULL) const;
370 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
371 /// a pointer to the MachineOperand rather than an index.
372 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
373 const TargetRegisterInfo *TRI = NULL) {
374 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
375 return (Idx == -1) ? NULL : &getOperand(Idx);
378 /// findFirstPredOperandIdx() - Find the index of the first operand in the
379 /// operand list that is used to represent the predicate. It returns -1 if
381 int findFirstPredOperandIdx() const;
383 /// isRegTiedToUseOperand - Given the index of a register def operand,
384 /// check if the register def is tied to a source operand, due to either
385 /// two-address elimination or inline assembly constraints. Returns the
386 /// first tied use operand index by reference is UseOpIdx is not null.
387 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
389 /// isRegTiedToDefOperand - Return true if the use operand of the specified
390 /// index is tied to an def operand. It also returns the def operand index by
391 /// reference if DefOpIdx is not null.
392 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
394 /// clearKillInfo - Clears kill flags on all operands.
396 void clearKillInfo();
398 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
400 void copyKillDeadInfo(const MachineInstr *MI);
402 /// copyPredicates - Copies predicate operand(s) from MI.
403 void copyPredicates(const MachineInstr *MI);
405 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
406 /// properly composing subreg indices where necessary.
407 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
408 const TargetRegisterInfo &RegInfo);
410 /// addRegisterKilled - We have determined MI kills a register. Look for the
411 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
412 /// add a implicit operand if it's not found. Returns true if the operand
413 /// exists / is added.
414 bool addRegisterKilled(unsigned IncomingReg,
415 const TargetRegisterInfo *RegInfo,
416 bool AddIfNotFound = false);
418 /// addRegisterDead - We have determined MI defined a register without a use.
419 /// Look for the operand that defines it and mark it as IsDead. If
420 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
421 /// true if the operand exists / is added.
422 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
423 bool AddIfNotFound = false);
425 /// addRegisterDefined - We have determined MI defines a register. Make sure
426 /// there is an operand defining Reg.
427 void addRegisterDefined(unsigned IncomingReg,
428 const TargetRegisterInfo *RegInfo = 0);
430 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
431 /// except those in the UsedRegs list.
432 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
433 const TargetRegisterInfo &TRI);
435 /// isSafeToMove - Return true if it is safe to move this instruction. If
436 /// SawStore is set to true, it means that there is a store (or call) between
437 /// the instruction's location and its intended destination.
438 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
439 bool &SawStore) const;
441 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
442 /// instruction which defined the specified register instead of copying it.
443 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
444 unsigned DstReg) const;
446 /// hasVolatileMemoryRef - Return true if this instruction may have a
447 /// volatile memory reference, or if the information describing the
448 /// memory reference is not available. Return false if it is known to
449 /// have no volatile memory references.
450 bool hasVolatileMemoryRef() const;
452 /// isInvariantLoad - Return true if this instruction is loading from a
453 /// location whose value is invariant across the function. For example,
454 /// loading a value from the constant pool or from the argument area of
455 /// a function if it does not change. This should only return true of *all*
456 /// loads the instruction does are invariant (if it does multiple loads).
457 bool isInvariantLoad(AliasAnalysis *AA) const;
459 /// isConstantValuePHI - If the specified instruction is a PHI that always
460 /// merges together the same virtual register, return the register, otherwise
462 unsigned isConstantValuePHI() const;
464 /// hasUnmodeledSideEffects - Return true if this instruction has side
465 /// effects that are not modeled by mayLoad / mayStore, etc.
466 /// For all instructions, the property is encoded in TargetInstrDesc::Flags
467 /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is
468 /// INLINEASM instruction, in which case the side effect property is encoded
469 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
471 bool hasUnmodeledSideEffects() const;
473 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
475 bool allDefsAreDead() const;
477 /// copyImplicitOps - Copy implicit register operands from specified
478 /// instruction to this instruction.
479 void copyImplicitOps(const MachineInstr *MI);
484 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
487 //===--------------------------------------------------------------------===//
488 // Accessors used to build up machine instructions.
490 /// addOperand - Add the specified operand to the instruction. If it is an
491 /// implicit operand, it is added to the end of the operand list. If it is
492 /// an explicit operand it is added at the end of the explicit operand list
493 /// (before the first implicit operand).
494 void addOperand(const MachineOperand &Op);
496 /// setDesc - Replace the instruction descriptor (thus opcode) of
497 /// the current instruction with a new one.
499 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
501 /// setDebugLoc - Replace current source information with new such.
502 /// Avoid using this, the constructor argument is preferable.
504 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
506 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
507 /// fewer operand than it started with.
509 void RemoveOperand(unsigned i);
511 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
512 /// This function should be used only occasionally. The setMemRefs function
513 /// is the primary method for setting up a MachineInstr's MemRefs list.
514 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
516 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
517 /// list. This does not transfer ownership.
518 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
519 MemRefs = NewMemRefs;
520 MemRefsEnd = NewMemRefsEnd;
524 /// getRegInfo - If this instruction is embedded into a MachineFunction,
525 /// return the MachineRegisterInfo object for the current function, otherwise
527 MachineRegisterInfo *getRegInfo();
529 /// addImplicitDefUseOperands - Add all implicit def and use operands to
530 /// this instruction.
531 void addImplicitDefUseOperands();
533 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
534 /// this instruction from their respective use lists. This requires that the
535 /// operands already be on their use lists.
536 void RemoveRegOperandsFromUseLists();
538 /// AddRegOperandsToUseLists - Add all of the register operands in
539 /// this instruction from their respective use lists. This requires that the
540 /// operands not be on their use lists yet.
541 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
544 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
545 /// MachineInstr* by *value* of the instruction rather than by pointer value.
546 /// The hashing and equality testing functions ignore definitions so this is
547 /// useful for CSE, etc.
548 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
549 static inline MachineInstr *getEmptyKey() {
553 static inline MachineInstr *getTombstoneKey() {
554 return reinterpret_cast<MachineInstr*>(-1);
557 static unsigned getHashValue(const MachineInstr* const &MI);
559 static bool isEqual(const MachineInstr* const &LHS,
560 const MachineInstr* const &RHS) {
561 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
562 LHS == getEmptyKey() || LHS == getTombstoneKey())
564 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
568 //===----------------------------------------------------------------------===//
571 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
576 } // End llvm namespace