1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/ArrayRecycler.h"
29 #include "llvm/Support/DebugLoc.h"
30 #include "llvm/Target/TargetOpcodes.h"
35 template <typename T> class SmallVectorImpl;
37 class TargetInstrInfo;
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
40 class MachineFunction;
41 class MachineMemOperand;
43 //===----------------------------------------------------------------------===//
44 /// MachineInstr - Representation of each machine instruction.
46 /// This class isn't a POD type, but it must have a trivial destructor. When a
47 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
48 /// without having their destructor called.
50 class MachineInstr : public ilist_node<MachineInstr> {
52 typedef MachineMemOperand **mmo_iterator;
54 /// Flags to specify different kinds of comments to output in
55 /// assembly code. These flags carry semantic information not
56 /// otherwise easily derivable from the IR text.
64 FrameSetup = 1 << 0, // Instruction is used as a part of
65 // function frame setup code.
66 BundledPred = 1 << 1, // Instruction has bundled predecessors.
67 BundledSucc = 1 << 2 // Instruction has bundled successors.
70 const MCInstrDesc *MCID; // Instruction descriptor.
71 MachineBasicBlock *Parent; // Pointer to the owning basic block.
73 // Operands are allocated by an ArrayRecycler.
74 MachineOperand *Operands; // Pointer to the first operand.
75 unsigned NumOperands; // Number of operands on instruction.
76 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
77 OperandCapacity CapOperands; // Capacity of the Operands array.
79 uint8_t Flags; // Various bits of additional
80 // information about machine
83 uint8_t AsmPrinterFlags; // Various bits of information used by
84 // the AsmPrinter to emit helpful
85 // comments. This is *not* semantic
86 // information. Do not use this for
87 // anything other than to convey comment
88 // information to AsmPrinter.
90 uint8_t NumMemRefs; // Information on memory references.
93 DebugLoc debugLoc; // Source line information.
95 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
96 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 // Use MachineFunction::DeleteMachineInstr() instead.
98 ~MachineInstr() LLVM_DELETED_FUNCTION;
100 // Intrusive list support
101 friend struct ilist_traits<MachineInstr>;
102 friend struct ilist_traits<MachineBasicBlock>;
103 void setParent(MachineBasicBlock *P) { Parent = P; }
105 /// MachineInstr ctor - This constructor creates a copy of the given
106 /// MachineInstr in the given MachineFunction.
107 MachineInstr(MachineFunction &, const MachineInstr &);
109 /// MachineInstr ctor - This constructor create a MachineInstr and add the
110 /// implicit operands. It reserves space for number of operands specified by
111 /// MCInstrDesc. An explicit DebugLoc is supplied.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
113 const DebugLoc dl, bool NoImp = false);
115 // MachineInstrs are pool-allocated and owned by MachineFunction.
116 friend class MachineFunction;
119 const MachineBasicBlock* getParent() const { return Parent; }
120 MachineBasicBlock* getParent() { return Parent; }
122 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
124 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
126 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
128 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (uint8_t)Flag;
142 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
144 void clearAsmPrinterFlag(CommentFlag Flag) {
145 AsmPrinterFlags &= ~Flag;
148 /// getFlags - Return the MI flags bitvector.
149 uint8_t getFlags() const {
153 /// getFlag - Return whether an MI flag is set.
154 bool getFlag(MIFlag Flag) const {
158 /// setFlag - Set a MI flag.
159 void setFlag(MIFlag Flag) {
160 Flags |= (uint8_t)Flag;
163 void setFlags(unsigned flags) {
164 // Filter out the automatically maintained flags.
165 unsigned Mask = BundledPred | BundledSucc;
166 Flags = (Flags & Mask) | (flags & ~Mask);
169 /// clearFlag - Clear a MI flag.
170 void clearFlag(MIFlag Flag) {
171 Flags &= ~((uint8_t)Flag);
174 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
177 /// A bundle looks like this before it's finalized:
189 /// In this case, the first MI starts a bundle but is not inside a bundle, the
190 /// next 2 MIs are considered "inside" the bundle.
192 /// After a bundle is finalized, it looks like this:
208 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
209 /// a bundle, but the next three MIs are.
210 bool isInsideBundle() const {
211 return getFlag(BundledPred);
214 /// isBundled - Return true if this instruction part of a bundle. This is true
215 /// if either itself or its following instruction is marked "InsideBundle".
216 bool isBundled() const {
217 return isBundledWithPred() || isBundledWithSucc();
220 /// Return true if this instruction is part of a bundle, and it is not the
221 /// first instruction in the bundle.
222 bool isBundledWithPred() const { return getFlag(BundledPred); }
224 /// Return true if this instruction is part of a bundle, and it is not the
225 /// last instruction in the bundle.
226 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
228 /// Bundle this instruction with its predecessor. This can be an unbundled
229 /// instruction, or it can be the first instruction in a bundle.
230 void bundleWithPred();
232 /// Bundle this instruction with its successor. This can be an unbundled
233 /// instruction, or it can be the last instruction in a bundle.
234 void bundleWithSucc();
236 /// Break bundle above this instruction.
237 void unbundleFromPred();
239 /// Break bundle below this instruction.
240 void unbundleFromSucc();
242 /// getDebugLoc - Returns the debug location id of this MachineInstr.
244 DebugLoc getDebugLoc() const { return debugLoc; }
246 /// emitError - Emit an error referring to the source location of this
247 /// instruction. This should only be used for inline assembly that is somehow
248 /// impossible to compile. Other errors should have been handled much
251 /// If this method returns, the caller should try to recover from the error.
253 void emitError(StringRef Msg) const;
255 /// getDesc - Returns the target instruction descriptor of this
257 const MCInstrDesc &getDesc() const { return *MCID; }
259 /// getOpcode - Returns the opcode of this MachineInstr.
261 int getOpcode() const { return MCID->Opcode; }
263 /// Access to explicit operands of the instruction.
265 unsigned getNumOperands() const { return NumOperands; }
267 const MachineOperand& getOperand(unsigned i) const {
268 assert(i < getNumOperands() && "getOperand() out of range!");
271 MachineOperand& getOperand(unsigned i) {
272 assert(i < getNumOperands() && "getOperand() out of range!");
276 /// getNumExplicitOperands - Returns the number of non-implicit operands.
278 unsigned getNumExplicitOperands() const;
280 /// iterator/begin/end - Iterate over all operands of a machine instruction.
281 typedef MachineOperand *mop_iterator;
282 typedef const MachineOperand *const_mop_iterator;
284 mop_iterator operands_begin() { return Operands; }
285 mop_iterator operands_end() { return Operands + NumOperands; }
287 const_mop_iterator operands_begin() const { return Operands; }
288 const_mop_iterator operands_end() const { return Operands + NumOperands; }
290 /// Access to memory operands of the instruction
291 mmo_iterator memoperands_begin() const { return MemRefs; }
292 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
293 bool memoperands_empty() const { return NumMemRefs == 0; }
295 /// hasOneMemOperand - Return true if this instruction has exactly one
296 /// MachineMemOperand.
297 bool hasOneMemOperand() const {
298 return NumMemRefs == 1;
301 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
302 /// queries but they are bundle aware.
305 IgnoreBundle, // Ignore bundles
306 AnyInBundle, // Return true if any instruction in bundle has property
307 AllInBundle // Return true if all instructions in bundle have property
310 /// hasProperty - Return true if the instruction (or in the case of a bundle,
311 /// the instructions inside the bundle) has the specified property.
312 /// The first argument is the property being queried.
313 /// The second argument indicates whether the query should look inside
314 /// instruction bundles.
315 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
316 // Inline the fast path for unbundled or bundle-internal instructions.
317 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
318 return getDesc().getFlags() & (1 << MCFlag);
320 // If this is the first instruction in a bundle, take the slow path.
321 return hasPropertyInBundle(1 << MCFlag, Type);
324 /// isVariadic - Return true if this instruction can have a variable number of
325 /// operands. In this case, the variable operands will be after the normal
326 /// operands but before the implicit definitions and uses (if any are
328 bool isVariadic(QueryType Type = IgnoreBundle) const {
329 return hasProperty(MCID::Variadic, Type);
332 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
333 /// ARM instructions which can set condition code if 's' bit is set.
334 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
335 return hasProperty(MCID::HasOptionalDef, Type);
338 /// isPseudo - Return true if this is a pseudo instruction that doesn't
339 /// correspond to a real machine instruction.
341 bool isPseudo(QueryType Type = IgnoreBundle) const {
342 return hasProperty(MCID::Pseudo, Type);
345 bool isReturn(QueryType Type = AnyInBundle) const {
346 return hasProperty(MCID::Return, Type);
349 bool isCall(QueryType Type = AnyInBundle) const {
350 return hasProperty(MCID::Call, Type);
353 /// isBarrier - Returns true if the specified instruction stops control flow
354 /// from executing the instruction immediately following it. Examples include
355 /// unconditional branches and return instructions.
356 bool isBarrier(QueryType Type = AnyInBundle) const {
357 return hasProperty(MCID::Barrier, Type);
360 /// isTerminator - Returns true if this instruction part of the terminator for
361 /// a basic block. Typically this is things like return and branch
364 /// Various passes use this to insert code into the bottom of a basic block,
365 /// but before control flow occurs.
366 bool isTerminator(QueryType Type = AnyInBundle) const {
367 return hasProperty(MCID::Terminator, Type);
370 /// isBranch - Returns true if this is a conditional, unconditional, or
371 /// indirect branch. Predicates below can be used to discriminate between
372 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
373 /// get more information.
374 bool isBranch(QueryType Type = AnyInBundle) const {
375 return hasProperty(MCID::Branch, Type);
378 /// isIndirectBranch - Return true if this is an indirect branch, such as a
379 /// branch through a register.
380 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
381 return hasProperty(MCID::IndirectBranch, Type);
384 /// isConditionalBranch - Return true if this is a branch which may fall
385 /// through to the next instruction or may transfer control flow to some other
386 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
387 /// information about this branch.
388 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
389 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
392 /// isUnconditionalBranch - Return true if this is a branch which always
393 /// transfers control flow to some other block. The
394 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
395 /// about this branch.
396 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
397 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
400 // isPredicable - Return true if this instruction has a predicate operand that
401 // controls execution. It may be set to 'always', or may be set to other
402 /// values. There are various methods in TargetInstrInfo that can be used to
403 /// control and modify the predicate in this instruction.
404 bool isPredicable(QueryType Type = AllInBundle) const {
405 // If it's a bundle than all bundled instructions must be predicable for this
407 return hasProperty(MCID::Predicable, Type);
410 /// isCompare - Return true if this instruction is a comparison.
411 bool isCompare(QueryType Type = IgnoreBundle) const {
412 return hasProperty(MCID::Compare, Type);
415 /// isMoveImmediate - Return true if this instruction is a move immediate
416 /// (including conditional moves) instruction.
417 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
418 return hasProperty(MCID::MoveImm, Type);
421 /// isBitcast - Return true if this instruction is a bitcast instruction.
423 bool isBitcast(QueryType Type = IgnoreBundle) const {
424 return hasProperty(MCID::Bitcast, Type);
427 /// isSelect - Return true if this instruction is a select instruction.
429 bool isSelect(QueryType Type = IgnoreBundle) const {
430 return hasProperty(MCID::Select, Type);
433 /// isNotDuplicable - Return true if this instruction cannot be safely
434 /// duplicated. For example, if the instruction has a unique labels attached
435 /// to it, duplicating it would cause multiple definition errors.
436 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
437 return hasProperty(MCID::NotDuplicable, Type);
440 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
441 /// which must be filled by the code generator.
442 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
443 return hasProperty(MCID::DelaySlot, Type);
446 /// canFoldAsLoad - Return true for instructions that can be folded as
447 /// memory operands in other instructions. The most common use for this
448 /// is instructions that are simple loads from memory that don't modify
449 /// the loaded value in any way, but it can also be used for instructions
450 /// that can be expressed as constant-pool loads, such as V_SETALLONES
451 /// on x86, to allow them to be folded when it is beneficial.
452 /// This should only be set on instructions that return a value in their
453 /// only virtual register definition.
454 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
455 return hasProperty(MCID::FoldableAsLoad, Type);
458 //===--------------------------------------------------------------------===//
459 // Side Effect Analysis
460 //===--------------------------------------------------------------------===//
462 /// mayLoad - Return true if this instruction could possibly read memory.
463 /// Instructions with this flag set are not necessarily simple load
464 /// instructions, they may load a value and modify it, for example.
465 bool mayLoad(QueryType Type = AnyInBundle) const {
467 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
468 if (ExtraInfo & InlineAsm::Extra_MayLoad)
471 return hasProperty(MCID::MayLoad, Type);
475 /// mayStore - Return true if this instruction could possibly modify memory.
476 /// Instructions with this flag set are not necessarily simple store
477 /// instructions, they may store a modified value based on their operands, or
478 /// may not actually modify anything, for example.
479 bool mayStore(QueryType Type = AnyInBundle) const {
481 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
482 if (ExtraInfo & InlineAsm::Extra_MayStore)
485 return hasProperty(MCID::MayStore, Type);
488 //===--------------------------------------------------------------------===//
489 // Flags that indicate whether an instruction can be modified by a method.
490 //===--------------------------------------------------------------------===//
492 /// isCommutable - Return true if this may be a 2- or 3-address
493 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
494 /// result if Y and Z are exchanged. If this flag is set, then the
495 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
498 /// Note that this flag may be set on instructions that are only commutable
499 /// sometimes. In these cases, the call to commuteInstruction will fail.
500 /// Also note that some instructions require non-trivial modification to
502 bool isCommutable(QueryType Type = IgnoreBundle) const {
503 return hasProperty(MCID::Commutable, Type);
506 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
507 /// which can be changed into a 3-address instruction if needed. Doing this
508 /// transformation can be profitable in the register allocator, because it
509 /// means that the instruction can use a 2-address form if possible, but
510 /// degrade into a less efficient form if the source and dest register cannot
511 /// be assigned to the same register. For example, this allows the x86
512 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
513 /// is the same speed as the shift but has bigger code size.
515 /// If this returns true, then the target must implement the
516 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
517 /// is allowed to fail if the transformation isn't valid for this specific
518 /// instruction (e.g. shl reg, 4 on x86).
520 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
521 return hasProperty(MCID::ConvertibleTo3Addr, Type);
524 /// usesCustomInsertionHook - Return true if this instruction requires
525 /// custom insertion support when the DAG scheduler is inserting it into a
526 /// machine basic block. If this is true for the instruction, it basically
527 /// means that it is a pseudo instruction used at SelectionDAG time that is
528 /// expanded out into magic code by the target when MachineInstrs are formed.
530 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
531 /// is used to insert this into the MachineBasicBlock.
532 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
533 return hasProperty(MCID::UsesCustomInserter, Type);
536 /// hasPostISelHook - Return true if this instruction requires *adjustment*
537 /// after instruction selection by calling a target hook. For example, this
538 /// can be used to fill in ARM 's' optional operand depending on whether
539 /// the conditional flag register is used.
540 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
541 return hasProperty(MCID::HasPostISelHook, Type);
544 /// isRematerializable - Returns true if this instruction is a candidate for
545 /// remat. This flag is deprecated, please don't use it anymore. If this
546 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
547 /// verify the instruction is really rematable.
548 bool isRematerializable(QueryType Type = AllInBundle) const {
549 // It's only possible to re-mat a bundle if all bundled instructions are
550 // re-materializable.
551 return hasProperty(MCID::Rematerializable, Type);
554 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
555 /// less) than a move instruction. This is useful during certain types of
556 /// optimizations (e.g., remat during two-address conversion or machine licm)
557 /// where we would like to remat or hoist the instruction, but not if it costs
558 /// more than moving the instruction into the appropriate register. Note, we
559 /// are not marking copies from and to the same register class with this flag.
560 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
561 // Only returns true for a bundle if all bundled instructions are cheap.
562 // FIXME: This probably requires a target hook.
563 return hasProperty(MCID::CheapAsAMove, Type);
566 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
567 /// have special register allocation requirements that are not captured by the
568 /// operand register classes. e.g. ARM::STRD's two source registers must be an
569 /// even / odd pair, ARM::STM registers have to be in ascending order.
570 /// Post-register allocation passes should not attempt to change allocations
571 /// for sources of instructions with this flag.
572 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
573 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
576 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
577 /// have special register allocation requirements that are not captured by the
578 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
579 /// even / odd pair, ARM::LDM registers have to be in ascending order.
580 /// Post-register allocation passes should not attempt to change allocations
581 /// for definitions of instructions with this flag.
582 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
583 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
588 CheckDefs, // Check all operands for equality
589 CheckKillDead, // Check all operands including kill / dead markers
590 IgnoreDefs, // Ignore all definitions
591 IgnoreVRegDefs // Ignore virtual register definitions
594 /// isIdenticalTo - Return true if this instruction is identical to (same
595 /// opcode and same operands as) the specified instruction.
596 bool isIdenticalTo(const MachineInstr *Other,
597 MICheckType Check = CheckDefs) const;
599 /// Unlink 'this' from the containing basic block, and return it without
602 /// This function can not be used on bundled instructions, use
603 /// removeFromBundle() to remove individual instructions from a bundle.
604 MachineInstr *removeFromParent();
606 /// Unlink this instruction from its basic block and return it without
609 /// If the instruction is part of a bundle, the other instructions in the
610 /// bundle remain bundled.
611 MachineInstr *removeFromBundle();
613 /// Unlink 'this' from the containing basic block and delete it.
615 /// If this instruction is the header of a bundle, the whole bundle is erased.
616 /// This function can not be used for instructions inside a bundle, use
617 /// eraseFromBundle() to erase individual bundled instructions.
618 void eraseFromParent();
620 /// Unlink 'this' form its basic block and delete it.
622 /// If the instruction is part of a bundle, the other instructions in the
623 /// bundle remain bundled.
624 void eraseFromBundle();
626 /// isLabel - Returns true if the MachineInstr represents a label.
628 bool isLabel() const {
629 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
630 getOpcode() == TargetOpcode::EH_LABEL ||
631 getOpcode() == TargetOpcode::GC_LABEL;
634 bool isPrologLabel() const {
635 return getOpcode() == TargetOpcode::PROLOG_LABEL;
637 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
638 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
639 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
641 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
642 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
643 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
644 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
645 bool isMSInlineAsm() const {
646 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
648 bool isStackAligningInlineAsm() const;
649 InlineAsm::AsmDialect getInlineAsmDialect() const;
650 bool isInsertSubreg() const {
651 return getOpcode() == TargetOpcode::INSERT_SUBREG;
653 bool isSubregToReg() const {
654 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
656 bool isRegSequence() const {
657 return getOpcode() == TargetOpcode::REG_SEQUENCE;
659 bool isBundle() const {
660 return getOpcode() == TargetOpcode::BUNDLE;
662 bool isCopy() const {
663 return getOpcode() == TargetOpcode::COPY;
665 bool isFullCopy() const {
666 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
669 /// isCopyLike - Return true if the instruction behaves like a copy.
670 /// This does not include native copy instructions.
671 bool isCopyLike() const {
672 return isCopy() || isSubregToReg();
675 /// isIdentityCopy - Return true is the instruction is an identity copy.
676 bool isIdentityCopy() const {
677 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
678 getOperand(0).getSubReg() == getOperand(1).getSubReg();
681 /// isTransient - Return true if this is a transient instruction that is
682 /// either very likely to be eliminated during register allocation (such as
683 /// copy-like instructions), or if this instruction doesn't have an
684 /// execution-time cost.
685 bool isTransient() const {
686 switch(getOpcode()) {
687 default: return false;
688 // Copy-like instructions are usually eliminated during register allocation.
689 case TargetOpcode::PHI:
690 case TargetOpcode::COPY:
691 case TargetOpcode::INSERT_SUBREG:
692 case TargetOpcode::SUBREG_TO_REG:
693 case TargetOpcode::REG_SEQUENCE:
694 // Pseudo-instructions that don't produce any real output.
695 case TargetOpcode::IMPLICIT_DEF:
696 case TargetOpcode::KILL:
697 case TargetOpcode::PROLOG_LABEL:
698 case TargetOpcode::EH_LABEL:
699 case TargetOpcode::GC_LABEL:
700 case TargetOpcode::DBG_VALUE:
705 /// Return the number of instructions inside the MI bundle, excluding the
708 /// This is the number of instructions that MachineBasicBlock::iterator
709 /// skips, 0 for unbundled instructions.
710 unsigned getBundleSize() const;
712 /// readsRegister - Return true if the MachineInstr reads the specified
713 /// register. If TargetRegisterInfo is passed, then it also checks if there
714 /// is a read of a super-register.
715 /// This does not count partial redefines of virtual registers as reads:
717 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
718 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
721 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
722 /// virtual register. Take into account that a partial define is a
723 /// read-modify-write operation.
724 bool readsVirtualRegister(unsigned Reg) const {
725 return readsWritesVirtualRegister(Reg).first;
728 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
729 /// indicating if this instruction reads or writes Reg. This also considers
731 /// If Ops is not null, all operand indices for Reg are added.
732 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
733 SmallVectorImpl<unsigned> *Ops = 0) const;
735 /// killsRegister - Return true if the MachineInstr kills the specified
736 /// register. If TargetRegisterInfo is passed, then it also checks if there is
737 /// a kill of a super-register.
738 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
739 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
742 /// definesRegister - Return true if the MachineInstr fully defines the
743 /// specified register. If TargetRegisterInfo is passed, then it also checks
744 /// if there is a def of a super-register.
745 /// NOTE: It's ignoring subreg indices on virtual registers.
746 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
747 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
750 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
751 /// or partially define) the specified register.
752 /// NOTE: It's ignoring subreg indices on virtual registers.
753 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
754 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
757 /// registerDefIsDead - Returns true if the register is dead in this machine
758 /// instruction. If TargetRegisterInfo is passed, then it also checks
759 /// if there is a dead def of a super-register.
760 bool registerDefIsDead(unsigned Reg,
761 const TargetRegisterInfo *TRI = NULL) const {
762 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
765 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
766 /// the specific register or -1 if it is not found. It further tightens
767 /// the search criteria to a use that kills the register if isKill is true.
768 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
769 const TargetRegisterInfo *TRI = NULL) const;
771 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
772 /// a pointer to the MachineOperand rather than an index.
773 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
774 const TargetRegisterInfo *TRI = NULL) {
775 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
776 return (Idx == -1) ? NULL : &getOperand(Idx);
779 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
780 /// the specified register or -1 if it is not found. If isDead is true, defs
781 /// that are not dead are skipped. If Overlap is true, then it also looks for
782 /// defs that merely overlap the specified register. If TargetRegisterInfo is
783 /// non-null, then it also checks if there is a def of a super-register.
784 /// This may also return a register mask operand when Overlap is true.
785 int findRegisterDefOperandIdx(unsigned Reg,
786 bool isDead = false, bool Overlap = false,
787 const TargetRegisterInfo *TRI = NULL) const;
789 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
790 /// a pointer to the MachineOperand rather than an index.
791 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
792 const TargetRegisterInfo *TRI = NULL) {
793 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
794 return (Idx == -1) ? NULL : &getOperand(Idx);
797 /// findFirstPredOperandIdx() - Find the index of the first operand in the
798 /// operand list that is used to represent the predicate. It returns -1 if
800 int findFirstPredOperandIdx() const;
802 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
803 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
804 /// getOperand(OpIdx) does not belong to an inline asm operand group.
806 /// If GroupNo is not NULL, it will receive the number of the operand group
807 /// containing OpIdx.
809 /// The flag operand is an immediate that can be decoded with methods like
810 /// InlineAsm::hasRegClassConstraint().
812 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
814 /// getRegClassConstraint - Compute the static register class constraint for
815 /// operand OpIdx. For normal instructions, this is derived from the
816 /// MCInstrDesc. For inline assembly it is derived from the flag words.
818 /// Returns NULL if the static register classs constraint cannot be
821 const TargetRegisterClass*
822 getRegClassConstraint(unsigned OpIdx,
823 const TargetInstrInfo *TII,
824 const TargetRegisterInfo *TRI) const;
826 /// tieOperands - Add a tie between the register operands at DefIdx and
827 /// UseIdx. The tie will cause the register allocator to ensure that the two
828 /// operands are assigned the same physical register.
830 /// Tied operands are managed automatically for explicit operands in the
831 /// MCInstrDesc. This method is for exceptional cases like inline asm.
832 void tieOperands(unsigned DefIdx, unsigned UseIdx);
834 /// findTiedOperandIdx - Given the index of a tied register operand, find the
835 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
836 /// index of the tied operand which must exist.
837 unsigned findTiedOperandIdx(unsigned OpIdx) const;
839 /// isRegTiedToUseOperand - Given the index of a register def operand,
840 /// check if the register def is tied to a source operand, due to either
841 /// two-address elimination or inline assembly constraints. Returns the
842 /// first tied use operand index by reference if UseOpIdx is not null.
843 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
844 const MachineOperand &MO = getOperand(DefOpIdx);
845 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
848 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
852 /// isRegTiedToDefOperand - Return true if the use operand of the specified
853 /// index is tied to an def operand. It also returns the def operand index by
854 /// reference if DefOpIdx is not null.
855 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
856 const MachineOperand &MO = getOperand(UseOpIdx);
857 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
860 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
864 /// clearKillInfo - Clears kill flags on all operands.
866 void clearKillInfo();
868 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
869 /// properly composing subreg indices where necessary.
870 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
871 const TargetRegisterInfo &RegInfo);
873 /// addRegisterKilled - We have determined MI kills a register. Look for the
874 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
875 /// add a implicit operand if it's not found. Returns true if the operand
876 /// exists / is added.
877 bool addRegisterKilled(unsigned IncomingReg,
878 const TargetRegisterInfo *RegInfo,
879 bool AddIfNotFound = false);
881 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
882 /// provided, this includes super-register kills.
883 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
885 /// addRegisterDead - We have determined MI defined a register without a use.
886 /// Look for the operand that defines it and mark it as IsDead. If
887 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
888 /// true if the operand exists / is added.
889 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
890 bool AddIfNotFound = false);
892 /// addRegisterDefined - We have determined MI defines a register. Make sure
893 /// there is an operand defining Reg.
894 void addRegisterDefined(unsigned IncomingReg,
895 const TargetRegisterInfo *RegInfo = 0);
897 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
898 /// dead except those in the UsedRegs list.
900 /// On instructions with register mask operands, also add implicit-def
901 /// operands for all registers in UsedRegs.
902 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
903 const TargetRegisterInfo &TRI);
905 /// isSafeToMove - Return true if it is safe to move this instruction. If
906 /// SawStore is set to true, it means that there is a store (or call) between
907 /// the instruction's location and its intended destination.
908 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
909 bool &SawStore) const;
911 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
912 /// instruction which defined the specified register instead of copying it.
913 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
914 unsigned DstReg) const;
916 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
917 /// or volatile memory reference, or if the information describing the memory
918 /// reference is not available. Return false if it is known to have no
919 /// ordered or volatile memory references.
920 bool hasOrderedMemoryRef() const;
922 /// isInvariantLoad - Return true if this instruction is loading from a
923 /// location whose value is invariant across the function. For example,
924 /// loading a value from the constant pool or from the argument area of
925 /// a function if it does not change. This should only return true of *all*
926 /// loads the instruction does are invariant (if it does multiple loads).
927 bool isInvariantLoad(AliasAnalysis *AA) const;
929 /// isConstantValuePHI - If the specified instruction is a PHI that always
930 /// merges together the same virtual register, return the register, otherwise
932 unsigned isConstantValuePHI() const;
934 /// hasUnmodeledSideEffects - Return true if this instruction has side
935 /// effects that are not modeled by mayLoad / mayStore, etc.
936 /// For all instructions, the property is encoded in MCInstrDesc::Flags
937 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
938 /// INLINEASM instruction, in which case the side effect property is encoded
939 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
941 bool hasUnmodeledSideEffects() const;
943 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
945 bool allDefsAreDead() const;
947 /// copyImplicitOps - Copy implicit register operands from specified
948 /// instruction to this instruction.
949 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
954 void print(raw_ostream &OS, const TargetMachine *TM = 0,
955 bool SkipOpers = false) const;
958 //===--------------------------------------------------------------------===//
959 // Accessors used to build up machine instructions.
961 /// Add the specified operand to the instruction. If it is an implicit
962 /// operand, it is added to the end of the operand list. If it is an
963 /// explicit operand it is added at the end of the explicit operand list
964 /// (before the first implicit operand).
966 /// MF must be the machine function that was used to allocate this
969 /// MachineInstrBuilder provides a more convenient interface for creating
970 /// instructions and adding operands.
971 void addOperand(MachineFunction &MF, const MachineOperand &Op);
973 /// Add an operand without providing an MF reference. This only works for
974 /// instructions that are inserted in a basic block.
976 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
978 void addOperand(const MachineOperand &Op);
980 /// setDesc - Replace the instruction descriptor (thus opcode) of
981 /// the current instruction with a new one.
983 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
985 /// setDebugLoc - Replace current source information with new such.
986 /// Avoid using this, the constructor argument is preferable.
988 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
990 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
991 /// fewer operand than it started with.
993 void RemoveOperand(unsigned i);
995 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
996 /// This function should be used only occasionally. The setMemRefs function
997 /// is the primary method for setting up a MachineInstr's MemRefs list.
998 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1000 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1001 /// list. This does not transfer ownership.
1002 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1003 MemRefs = NewMemRefs;
1004 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1005 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1009 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1010 /// return the MachineRegisterInfo object for the current function, otherwise
1012 MachineRegisterInfo *getRegInfo();
1014 /// untieRegOperand - Break any tie involving OpIdx.
1015 void untieRegOperand(unsigned OpIdx) {
1016 MachineOperand &MO = getOperand(OpIdx);
1017 if (MO.isReg() && MO.isTied()) {
1018 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1023 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1024 /// this instruction.
1025 void addImplicitDefUseOperands(MachineFunction &MF);
1027 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1028 /// this instruction from their respective use lists. This requires that the
1029 /// operands already be on their use lists.
1030 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1032 /// AddRegOperandsToUseLists - Add all of the register operands in
1033 /// this instruction from their respective use lists. This requires that the
1034 /// operands not be on their use lists yet.
1035 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1037 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1039 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1042 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1043 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1044 /// The hashing and equality testing functions ignore definitions so this is
1045 /// useful for CSE, etc.
1046 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1047 static inline MachineInstr *getEmptyKey() {
1051 static inline MachineInstr *getTombstoneKey() {
1052 return reinterpret_cast<MachineInstr*>(-1);
1055 static unsigned getHashValue(const MachineInstr* const &MI);
1057 static bool isEqual(const MachineInstr* const &LHS,
1058 const MachineInstr* const &RHS) {
1059 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1060 LHS == getEmptyKey() || LHS == getTombstoneKey())
1062 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1066 //===----------------------------------------------------------------------===//
1067 // Debugging Support
1069 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1074 } // End llvm namespace