2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/Target/InstInfo.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
62 class MachineOperand {
64 enum MachineOperandType {
65 MO_VirtualRegister, // virtual register for *value
66 MO_MachineRegister, // pre-assigned machine register `regNum'
74 MachineOperandType opType;
77 Value* value; // BasicBlockVal for a label operand.
78 // ConstantVal for a non-address immediate.
79 // Virtual register for an SSA operand,
80 // including hidden operands required for
81 // the generated machine code.
83 unsigned int regNum; // register number for an explicit register
85 int64_t immedVal; // constant value for an explicit constant
88 bool isDef; // is this a defition for the value
89 // made public for faster access
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType () const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
106 opType == MO_PCRelativeDisp);
109 inline unsigned int getMachineRegNum() const {
110 assert(opType == MO_MachineRegister);
113 inline int64_t getImmedValue () const {
114 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
117 inline bool opIsDef () const {
122 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
126 // These functions are provided so that a vector of operands can be
127 // statically allocated and individual ones can be initialized later.
128 // Give class MachineInstr gets access to these functions.
130 void Initialize (MachineOperandType operandType,
132 void InitializeConst (MachineOperandType operandType,
134 void InitializeReg (unsigned int regNum);
136 friend class MachineInstr;
137 friend class ValOpIterator<const MachineInstr, const Value>;
138 friend class ValOpIterator< MachineInstr, Value>;
148 MachineOperand::MachineOperand()
149 : opType(MO_VirtualRegister),
157 MachineOperand::MachineOperand(MachineOperandType operandType,
159 : opType(operandType),
167 MachineOperand::MachineOperand(const MachineOperand& mo)
172 case MO_VirtualRegister:
173 case MO_CCRegister: value = mo.value; break;
174 case MO_MachineRegister: regNum = mo.regNum; break;
175 case MO_SignExtendedImmed:
176 case MO_UnextendedImmed:
177 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
183 MachineOperand::Initialize(MachineOperandType operandType,
186 opType = operandType;
191 MachineOperand::InitializeConst(MachineOperandType operandType,
194 opType = operandType;
200 MachineOperand::InitializeReg(unsigned int _regNum)
202 opType = MO_MachineRegister;
208 //---------------------------------------------------------------------------
209 // class MachineInstr
212 // Representation of each machine instruction.
214 // MachineOpCode must be an enum, defined separately for each target.
215 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
217 // opCodeMask is used to record variants of an instruction.
218 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
219 // ANNUL: if 1: Annul delay slot instruction.
220 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
221 // Instead of creating 4 different opcodes for BNZ, we create a single
222 // opcode and set bits in opCodeMask for each of these flags.
223 //---------------------------------------------------------------------------
225 class MachineInstr : public NonCopyable {
227 MachineOpCode opCode;
228 OpCodeMask opCodeMask; // extra bits for variants of an opcode
229 vector<MachineOperand> operands;
232 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
233 typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
236 /*ctor*/ MachineInstr (MachineOpCode _opCode,
237 OpCodeMask _opCodeMask = 0x0);
238 /*ctor*/ MachineInstr (MachineOpCode _opCode,
239 unsigned numOperands,
240 OpCodeMask _opCodeMask = 0x0);
241 inline ~MachineInstr () {}
243 const MachineOpCode getOpCode () const;
245 unsigned int getNumOperands () const;
247 const MachineOperand& getOperand (unsigned int i) const;
248 MachineOperand& getOperand (unsigned int i);
250 bool operandIsDefined(unsigned int i) const;
252 void dump (unsigned int indent = 0) const;
259 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
260 friend val_op_const_iterator;
261 friend val_op_iterator;
264 // Access to set the operands when building the machine instruction
265 void SetMachineOperand(unsigned int i,
266 MachineOperand::MachineOperandType operandType,
267 Value* _val, bool isDef=false);
268 void SetMachineOperand(unsigned int i,
269 MachineOperand::MachineOperandType operandType,
270 int64_t intValue, bool isDef=false);
271 void SetMachineOperand(unsigned int i,
276 inline const MachineOpCode
277 MachineInstr::getOpCode() const
283 MachineInstr::getNumOperands() const
285 return operands.size();
288 inline MachineOperand&
289 MachineInstr::getOperand(unsigned int i)
291 assert(i < operands.size() && "getOperand() out of range!");
295 inline const MachineOperand&
296 MachineInstr::getOperand(unsigned int i) const
298 assert(i < operands.size() && "getOperand() out of range!");
303 MachineInstr::operandIsDefined(unsigned int i) const
305 return getOperand(i).opIsDef();
309 template<class _MI, class _V>
310 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
316 inline void skipToNextVal() {
317 while (i < minstr->getNumOperands() &&
318 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
319 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
320 && minstr->operands[i].value != NULL))
325 typedef ValOpIterator<_MI, _V> _Self;
327 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
328 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
332 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
333 inline _V* operator->() const { return operator*(); }
334 // inline bool isDef () const { return (((int) i) == resultPos); }
336 inline bool isDef () const { return minstr->getOperand(i).isDef; }
337 inline bool done () const { return (i == minstr->getNumOperands()); }
339 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
340 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
344 //---------------------------------------------------------------------------
345 // class MachineCodeForVMInstr
348 // Representation of the sequence of machine instructions created
349 // for a single VM instruction. Additionally records any temporary
350 // "values" used as intermediate values in this sequence.
351 // Note that such values should be treated as pure SSA values with
352 // no interpretation of their operands (i.e., as a TmpInstruction object
353 // which actually represents such a value).
355 //---------------------------------------------------------------------------
357 class MachineCodeForVMInstr: public vector<MachineInstr*>
360 vector<Value*> tempVec;
363 /*ctor*/ MachineCodeForVMInstr () {}
364 /*ctor*/ ~MachineCodeForVMInstr ();
366 const vector<Value*>&
367 getTempValues () const { return tempVec; }
369 void addTempValue (Value* val)
370 { tempVec.push_back(val); }
372 // dropAllReferences() - This function drops all references within
373 // temporary (hidden) instructions created in implementing the original
374 // VM intruction. This ensures there are no remaining "uses" within
375 // these hidden instructions, before the values of a method are freed.
377 // Make this inline because it has to be called from class Instruction
378 // and inlining it avoids a serious circurality in link order.
379 inline void dropAllReferences() {
380 for (unsigned i=0, N=tempVec.size(); i < N; i++)
381 if (Instruction *I = tempVec[i]->castInstruction())
382 I->dropAllReferences();
387 MachineCodeForVMInstr::~MachineCodeForVMInstr()
389 // Free the Value objects created to hold intermediate values
390 for (unsigned i=0, N=tempVec.size(); i < N; i++)
393 // Free the MachineInstr objects allocated, if any.
394 for (unsigned i=0, N=this->size(); i < N; i++)
399 //---------------------------------------------------------------------------
400 // class MachineCodeForBasicBlock
403 // Representation of the sequence of machine instructions created
404 // for a basic block.
405 //---------------------------------------------------------------------------
408 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
410 typedef vector<MachineInstr*>::iterator iterator;
411 typedef vector<const MachineInstr*>::const_iterator const_iterator;
415 //---------------------------------------------------------------------------
416 // Target-independent utility routines for creating machine instructions
417 //---------------------------------------------------------------------------
420 //------------------------------------------------------------------------
421 // Function Set2OperandsFromInstr
422 // Function Set3OperandsFromInstr
424 // For the common case of 2- and 3-operand arithmetic/logical instructions,
425 // set the m/c instr. operands directly from the VM instruction's operands.
426 // Check whether the first or second operand is 0 and can use a dedicated
428 // Check whether the second operand should use an immediate field or register.
429 // (First and third operands are never immediates for such instructions.)
432 // canDiscardResult: Specifies that the result operand can be discarded
433 // by using the dedicated "0"
435 // op1position, op2position and resultPosition: Specify in which position
436 // in the machine instruction the 3 operands (arg1, arg2
437 // and result) should go.
439 // RETURN VALUE: unsigned int flags, where
440 // flags & 0x01 => operand 1 is constant and needs a register
441 // flags & 0x02 => operand 2 is constant and needs a register
442 //------------------------------------------------------------------------
444 void Set2OperandsFromInstr (MachineInstr* minstr,
445 InstructionNode* vmInstrNode,
446 const TargetMachine& targetMachine,
447 bool canDiscardResult = false,
449 int resultPosition = 1);
451 void Set3OperandsFromInstr (MachineInstr* minstr,
452 InstructionNode* vmInstrNode,
453 const TargetMachine& targetMachine,
454 bool canDiscardResult = false,
457 int resultPosition = 2);
459 MachineOperand::MachineOperandType
460 ChooseRegOrImmed(Value* val,
461 MachineOpCode opCode,
462 const TargetMachine& targetMachine,
464 unsigned int& getMachineRegNum,
465 int64_t& getImmedValue);
468 ostream& operator<<(ostream& os, const MachineInstr& minstr);
471 ostream& operator<<(ostream& os, const MachineOperand& mop);
474 void PrintMachineInstructions (const Method *method);
477 //**************************************************************************/