1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// MachineInstr - Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) = delete;
97 void operator=(const MachineInstr&) = delete;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() = delete;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// MachineInstr ctor - This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
164 void setFlags(unsigned flags) {
165 // Filter out the automatically maintained flags.
166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
170 /// clearFlag - Clear a MI flag.
171 void clearFlag(MIFlag Flag) {
172 Flags &= ~((uint8_t)Flag);
175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
178 /// A bundle looks like this before it's finalized:
190 /// In this case, the first MI starts a bundle but is not inside a bundle, the
191 /// next 2 MIs are considered "inside" the bundle.
193 /// After a bundle is finalized, it looks like this:
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
210 /// a bundle, but the next three MIs are.
211 bool isInsideBundle() const {
212 return getFlag(BundledPred);
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle".
217 bool isBundled() const {
218 return isBundledWithPred() || isBundledWithSucc();
221 /// Return true if this instruction is part of a bundle, and it is not the
222 /// first instruction in the bundle.
223 bool isBundledWithPred() const { return getFlag(BundledPred); }
225 /// Return true if this instruction is part of a bundle, and it is not the
226 /// last instruction in the bundle.
227 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
229 /// Bundle this instruction with its predecessor. This can be an unbundled
230 /// instruction, or it can be the first instruction in a bundle.
231 void bundleWithPred();
233 /// Bundle this instruction with its successor. This can be an unbundled
234 /// instruction, or it can be the last instruction in a bundle.
235 void bundleWithSucc();
237 /// Break bundle above this instruction.
238 void unbundleFromPred();
240 /// Break bundle below this instruction.
241 void unbundleFromSucc();
243 /// getDebugLoc - Returns the debug location id of this MachineInstr.
245 const DebugLoc &getDebugLoc() const { return debugLoc; }
247 /// \brief Return the debug variable referenced by
248 /// this DBG_VALUE instruction.
249 DIVariable getDebugVariable() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 DIVariable Var(getOperand(2).getMetadata());
252 assert(Var.Verify() && "not a DIVariable");
256 /// \brief Return the complex address expression referenced by
257 /// this DBG_VALUE instruction.
258 DIExpression getDebugExpression() const {
259 assert(isDebugValue() && "not a DBG_VALUE");
260 return cast<MDExpression>(getOperand(3).getMetadata());
263 /// emitError - Emit an error referring to the source location of this
264 /// instruction. This should only be used for inline assembly that is somehow
265 /// impossible to compile. Other errors should have been handled much
268 /// If this method returns, the caller should try to recover from the error.
270 void emitError(StringRef Msg) const;
272 /// getDesc - Returns the target instruction descriptor of this
274 const MCInstrDesc &getDesc() const { return *MCID; }
276 /// getOpcode - Returns the opcode of this MachineInstr.
278 int getOpcode() const { return MCID->Opcode; }
280 /// Access to explicit operands of the instruction.
282 unsigned getNumOperands() const { return NumOperands; }
284 const MachineOperand& getOperand(unsigned i) const {
285 assert(i < getNumOperands() && "getOperand() out of range!");
288 MachineOperand& getOperand(unsigned i) {
289 assert(i < getNumOperands() && "getOperand() out of range!");
293 /// getNumExplicitOperands - Returns the number of non-implicit operands.
295 unsigned getNumExplicitOperands() const;
297 /// iterator/begin/end - Iterate over all operands of a machine instruction.
298 typedef MachineOperand *mop_iterator;
299 typedef const MachineOperand *const_mop_iterator;
301 mop_iterator operands_begin() { return Operands; }
302 mop_iterator operands_end() { return Operands + NumOperands; }
304 const_mop_iterator operands_begin() const { return Operands; }
305 const_mop_iterator operands_end() const { return Operands + NumOperands; }
307 iterator_range<mop_iterator> operands() {
308 return iterator_range<mop_iterator>(operands_begin(), operands_end());
310 iterator_range<const_mop_iterator> operands() const {
311 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
313 iterator_range<mop_iterator> explicit_operands() {
314 return iterator_range<mop_iterator>(
315 operands_begin(), operands_begin() + getNumExplicitOperands());
317 iterator_range<const_mop_iterator> explicit_operands() const {
318 return iterator_range<const_mop_iterator>(
319 operands_begin(), operands_begin() + getNumExplicitOperands());
321 iterator_range<mop_iterator> implicit_operands() {
322 return iterator_range<mop_iterator>(explicit_operands().end(),
325 iterator_range<const_mop_iterator> implicit_operands() const {
326 return iterator_range<const_mop_iterator>(explicit_operands().end(),
329 iterator_range<mop_iterator> defs() {
330 return iterator_range<mop_iterator>(
331 operands_begin(), operands_begin() + getDesc().getNumDefs());
333 iterator_range<const_mop_iterator> defs() const {
334 return iterator_range<const_mop_iterator>(
335 operands_begin(), operands_begin() + getDesc().getNumDefs());
337 iterator_range<mop_iterator> uses() {
338 return iterator_range<mop_iterator>(
339 operands_begin() + getDesc().getNumDefs(), operands_end());
341 iterator_range<const_mop_iterator> uses() const {
342 return iterator_range<const_mop_iterator>(
343 operands_begin() + getDesc().getNumDefs(), operands_end());
346 /// Access to memory operands of the instruction
347 mmo_iterator memoperands_begin() const { return MemRefs; }
348 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
349 bool memoperands_empty() const { return NumMemRefs == 0; }
351 iterator_range<mmo_iterator> memoperands() {
352 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
354 iterator_range<mmo_iterator> memoperands() const {
355 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
358 /// hasOneMemOperand - Return true if this instruction has exactly one
359 /// MachineMemOperand.
360 bool hasOneMemOperand() const {
361 return NumMemRefs == 1;
364 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
365 /// queries but they are bundle aware.
368 IgnoreBundle, // Ignore bundles
369 AnyInBundle, // Return true if any instruction in bundle has property
370 AllInBundle // Return true if all instructions in bundle have property
373 /// hasProperty - Return true if the instruction (or in the case of a bundle,
374 /// the instructions inside the bundle) has the specified property.
375 /// The first argument is the property being queried.
376 /// The second argument indicates whether the query should look inside
377 /// instruction bundles.
378 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
379 // Inline the fast path for unbundled or bundle-internal instructions.
380 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
381 return getDesc().getFlags() & (1 << MCFlag);
383 // If this is the first instruction in a bundle, take the slow path.
384 return hasPropertyInBundle(1 << MCFlag, Type);
387 /// isVariadic - Return true if this instruction can have a variable number of
388 /// operands. In this case, the variable operands will be after the normal
389 /// operands but before the implicit definitions and uses (if any are
391 bool isVariadic(QueryType Type = IgnoreBundle) const {
392 return hasProperty(MCID::Variadic, Type);
395 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
396 /// ARM instructions which can set condition code if 's' bit is set.
397 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
398 return hasProperty(MCID::HasOptionalDef, Type);
401 /// isPseudo - Return true if this is a pseudo instruction that doesn't
402 /// correspond to a real machine instruction.
404 bool isPseudo(QueryType Type = IgnoreBundle) const {
405 return hasProperty(MCID::Pseudo, Type);
408 bool isReturn(QueryType Type = AnyInBundle) const {
409 return hasProperty(MCID::Return, Type);
412 bool isCall(QueryType Type = AnyInBundle) const {
413 return hasProperty(MCID::Call, Type);
416 /// isBarrier - Returns true if the specified instruction stops control flow
417 /// from executing the instruction immediately following it. Examples include
418 /// unconditional branches and return instructions.
419 bool isBarrier(QueryType Type = AnyInBundle) const {
420 return hasProperty(MCID::Barrier, Type);
423 /// isTerminator - Returns true if this instruction part of the terminator for
424 /// a basic block. Typically this is things like return and branch
427 /// Various passes use this to insert code into the bottom of a basic block,
428 /// but before control flow occurs.
429 bool isTerminator(QueryType Type = AnyInBundle) const {
430 return hasProperty(MCID::Terminator, Type);
433 /// isBranch - Returns true if this is a conditional, unconditional, or
434 /// indirect branch. Predicates below can be used to discriminate between
435 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
436 /// get more information.
437 bool isBranch(QueryType Type = AnyInBundle) const {
438 return hasProperty(MCID::Branch, Type);
441 /// isIndirectBranch - Return true if this is an indirect branch, such as a
442 /// branch through a register.
443 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
444 return hasProperty(MCID::IndirectBranch, Type);
447 /// isConditionalBranch - Return true if this is a branch which may fall
448 /// through to the next instruction or may transfer control flow to some other
449 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
450 /// information about this branch.
451 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
452 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
455 /// isUnconditionalBranch - Return true if this is a branch which always
456 /// transfers control flow to some other block. The
457 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
458 /// about this branch.
459 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
460 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
463 /// Return true if this instruction has a predicate operand that
464 /// controls execution. It may be set to 'always', or may be set to other
465 /// values. There are various methods in TargetInstrInfo that can be used to
466 /// control and modify the predicate in this instruction.
467 bool isPredicable(QueryType Type = AllInBundle) const {
468 // If it's a bundle than all bundled instructions must be predicable for this
470 return hasProperty(MCID::Predicable, Type);
473 /// isCompare - Return true if this instruction is a comparison.
474 bool isCompare(QueryType Type = IgnoreBundle) const {
475 return hasProperty(MCID::Compare, Type);
478 /// isMoveImmediate - Return true if this instruction is a move immediate
479 /// (including conditional moves) instruction.
480 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
481 return hasProperty(MCID::MoveImm, Type);
484 /// isBitcast - Return true if this instruction is a bitcast instruction.
486 bool isBitcast(QueryType Type = IgnoreBundle) const {
487 return hasProperty(MCID::Bitcast, Type);
490 /// isSelect - Return true if this instruction is a select instruction.
492 bool isSelect(QueryType Type = IgnoreBundle) const {
493 return hasProperty(MCID::Select, Type);
496 /// isNotDuplicable - Return true if this instruction cannot be safely
497 /// duplicated. For example, if the instruction has a unique labels attached
498 /// to it, duplicating it would cause multiple definition errors.
499 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
500 return hasProperty(MCID::NotDuplicable, Type);
503 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
504 /// which must be filled by the code generator.
505 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
506 return hasProperty(MCID::DelaySlot, Type);
509 /// canFoldAsLoad - Return true for instructions that can be folded as
510 /// memory operands in other instructions. The most common use for this
511 /// is instructions that are simple loads from memory that don't modify
512 /// the loaded value in any way, but it can also be used for instructions
513 /// that can be expressed as constant-pool loads, such as V_SETALLONES
514 /// on x86, to allow them to be folded when it is beneficial.
515 /// This should only be set on instructions that return a value in their
516 /// only virtual register definition.
517 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
518 return hasProperty(MCID::FoldableAsLoad, Type);
521 /// \brief Return true if this instruction behaves
522 /// the same way as the generic REG_SEQUENCE instructions.
524 /// dX VMOVDRR rY, rZ
526 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
528 /// Note that for the optimizers to be able to take advantage of
529 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
530 /// override accordingly.
531 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
532 return hasProperty(MCID::RegSequence, Type);
535 /// \brief Return true if this instruction behaves
536 /// the same way as the generic EXTRACT_SUBREG instructions.
538 /// rX, rY VMOVRRD dZ
539 /// is equivalent to two EXTRACT_SUBREG:
540 /// rX = EXTRACT_SUBREG dZ, ssub_0
541 /// rY = EXTRACT_SUBREG dZ, ssub_1
543 /// Note that for the optimizers to be able to take advantage of
544 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
545 /// override accordingly.
546 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
547 return hasProperty(MCID::ExtractSubreg, Type);
550 /// \brief Return true if this instruction behaves
551 /// the same way as the generic INSERT_SUBREG instructions.
553 /// dX = VSETLNi32 dY, rZ, Imm
554 /// is equivalent to a INSERT_SUBREG:
555 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
557 /// Note that for the optimizers to be able to take advantage of
558 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
559 /// override accordingly.
560 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
561 return hasProperty(MCID::InsertSubreg, Type);
564 //===--------------------------------------------------------------------===//
565 // Side Effect Analysis
566 //===--------------------------------------------------------------------===//
568 /// mayLoad - Return true if this instruction could possibly read memory.
569 /// Instructions with this flag set are not necessarily simple load
570 /// instructions, they may load a value and modify it, for example.
571 bool mayLoad(QueryType Type = AnyInBundle) const {
573 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
574 if (ExtraInfo & InlineAsm::Extra_MayLoad)
577 return hasProperty(MCID::MayLoad, Type);
581 /// mayStore - Return true if this instruction could possibly modify memory.
582 /// Instructions with this flag set are not necessarily simple store
583 /// instructions, they may store a modified value based on their operands, or
584 /// may not actually modify anything, for example.
585 bool mayStore(QueryType Type = AnyInBundle) const {
587 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
588 if (ExtraInfo & InlineAsm::Extra_MayStore)
591 return hasProperty(MCID::MayStore, Type);
594 //===--------------------------------------------------------------------===//
595 // Flags that indicate whether an instruction can be modified by a method.
596 //===--------------------------------------------------------------------===//
598 /// isCommutable - Return true if this may be a 2- or 3-address
599 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
600 /// result if Y and Z are exchanged. If this flag is set, then the
601 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
604 /// Note that this flag may be set on instructions that are only commutable
605 /// sometimes. In these cases, the call to commuteInstruction will fail.
606 /// Also note that some instructions require non-trivial modification to
608 bool isCommutable(QueryType Type = IgnoreBundle) const {
609 return hasProperty(MCID::Commutable, Type);
612 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
613 /// which can be changed into a 3-address instruction if needed. Doing this
614 /// transformation can be profitable in the register allocator, because it
615 /// means that the instruction can use a 2-address form if possible, but
616 /// degrade into a less efficient form if the source and dest register cannot
617 /// be assigned to the same register. For example, this allows the x86
618 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
619 /// is the same speed as the shift but has bigger code size.
621 /// If this returns true, then the target must implement the
622 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
623 /// is allowed to fail if the transformation isn't valid for this specific
624 /// instruction (e.g. shl reg, 4 on x86).
626 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
627 return hasProperty(MCID::ConvertibleTo3Addr, Type);
630 /// usesCustomInsertionHook - Return true if this instruction requires
631 /// custom insertion support when the DAG scheduler is inserting it into a
632 /// machine basic block. If this is true for the instruction, it basically
633 /// means that it is a pseudo instruction used at SelectionDAG time that is
634 /// expanded out into magic code by the target when MachineInstrs are formed.
636 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
637 /// is used to insert this into the MachineBasicBlock.
638 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
639 return hasProperty(MCID::UsesCustomInserter, Type);
642 /// hasPostISelHook - Return true if this instruction requires *adjustment*
643 /// after instruction selection by calling a target hook. For example, this
644 /// can be used to fill in ARM 's' optional operand depending on whether
645 /// the conditional flag register is used.
646 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
647 return hasProperty(MCID::HasPostISelHook, Type);
650 /// isRematerializable - Returns true if this instruction is a candidate for
651 /// remat. This flag is deprecated, please don't use it anymore. If this
652 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
653 /// verify the instruction is really rematable.
654 bool isRematerializable(QueryType Type = AllInBundle) const {
655 // It's only possible to re-mat a bundle if all bundled instructions are
656 // re-materializable.
657 return hasProperty(MCID::Rematerializable, Type);
660 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
661 /// less) than a move instruction. This is useful during certain types of
662 /// optimizations (e.g., remat during two-address conversion or machine licm)
663 /// where we would like to remat or hoist the instruction, but not if it costs
664 /// more than moving the instruction into the appropriate register. Note, we
665 /// are not marking copies from and to the same register class with this flag.
666 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
667 // Only returns true for a bundle if all bundled instructions are cheap.
668 return hasProperty(MCID::CheapAsAMove, Type);
671 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
672 /// have special register allocation requirements that are not captured by the
673 /// operand register classes. e.g. ARM::STRD's two source registers must be an
674 /// even / odd pair, ARM::STM registers have to be in ascending order.
675 /// Post-register allocation passes should not attempt to change allocations
676 /// for sources of instructions with this flag.
677 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
678 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
681 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
682 /// have special register allocation requirements that are not captured by the
683 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
684 /// even / odd pair, ARM::LDM registers have to be in ascending order.
685 /// Post-register allocation passes should not attempt to change allocations
686 /// for definitions of instructions with this flag.
687 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
688 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
693 CheckDefs, // Check all operands for equality
694 CheckKillDead, // Check all operands including kill / dead markers
695 IgnoreDefs, // Ignore all definitions
696 IgnoreVRegDefs // Ignore virtual register definitions
699 /// isIdenticalTo - Return true if this instruction is identical to (same
700 /// opcode and same operands as) the specified instruction.
701 bool isIdenticalTo(const MachineInstr *Other,
702 MICheckType Check = CheckDefs) const;
704 /// Unlink 'this' from the containing basic block, and return it without
707 /// This function can not be used on bundled instructions, use
708 /// removeFromBundle() to remove individual instructions from a bundle.
709 MachineInstr *removeFromParent();
711 /// Unlink this instruction from its basic block and return it without
714 /// If the instruction is part of a bundle, the other instructions in the
715 /// bundle remain bundled.
716 MachineInstr *removeFromBundle();
718 /// Unlink 'this' from the containing basic block and delete it.
720 /// If this instruction is the header of a bundle, the whole bundle is erased.
721 /// This function can not be used for instructions inside a bundle, use
722 /// eraseFromBundle() to erase individual bundled instructions.
723 void eraseFromParent();
725 /// Unlink 'this' from the containing basic block and delete it.
727 /// For all definitions mark their uses in DBG_VALUE nodes
728 /// as undefined. Otherwise like eraseFromParent().
729 void eraseFromParentAndMarkDBGValuesForRemoval();
731 /// Unlink 'this' form its basic block and delete it.
733 /// If the instruction is part of a bundle, the other instructions in the
734 /// bundle remain bundled.
735 void eraseFromBundle();
737 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
738 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
740 /// isLabel - Returns true if the MachineInstr represents a label.
742 bool isLabel() const { return isEHLabel() || isGCLabel(); }
743 bool isCFIInstruction() const {
744 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
747 // True if the instruction represents a position in the function.
748 bool isPosition() const { return isLabel() || isCFIInstruction(); }
750 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
751 /// A DBG_VALUE is indirect iff the first operand is a register and
752 /// the second operand is an immediate.
753 bool isIndirectDebugValue() const {
754 return isDebugValue()
755 && getOperand(0).isReg()
756 && getOperand(1).isImm();
759 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
760 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
761 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
762 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
763 bool isMSInlineAsm() const {
764 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
766 bool isStackAligningInlineAsm() const;
767 InlineAsm::AsmDialect getInlineAsmDialect() const;
768 bool isInsertSubreg() const {
769 return getOpcode() == TargetOpcode::INSERT_SUBREG;
771 bool isSubregToReg() const {
772 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
774 bool isRegSequence() const {
775 return getOpcode() == TargetOpcode::REG_SEQUENCE;
777 bool isBundle() const {
778 return getOpcode() == TargetOpcode::BUNDLE;
780 bool isCopy() const {
781 return getOpcode() == TargetOpcode::COPY;
783 bool isFullCopy() const {
784 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
786 bool isExtractSubreg() const {
787 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
790 /// isCopyLike - Return true if the instruction behaves like a copy.
791 /// This does not include native copy instructions.
792 bool isCopyLike() const {
793 return isCopy() || isSubregToReg();
796 /// isIdentityCopy - Return true is the instruction is an identity copy.
797 bool isIdentityCopy() const {
798 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
799 getOperand(0).getSubReg() == getOperand(1).getSubReg();
802 /// isTransient - Return true if this is a transient instruction that is
803 /// either very likely to be eliminated during register allocation (such as
804 /// copy-like instructions), or if this instruction doesn't have an
805 /// execution-time cost.
806 bool isTransient() const {
807 switch(getOpcode()) {
808 default: return false;
809 // Copy-like instructions are usually eliminated during register allocation.
810 case TargetOpcode::PHI:
811 case TargetOpcode::COPY:
812 case TargetOpcode::INSERT_SUBREG:
813 case TargetOpcode::SUBREG_TO_REG:
814 case TargetOpcode::REG_SEQUENCE:
815 // Pseudo-instructions that don't produce any real output.
816 case TargetOpcode::IMPLICIT_DEF:
817 case TargetOpcode::KILL:
818 case TargetOpcode::CFI_INSTRUCTION:
819 case TargetOpcode::EH_LABEL:
820 case TargetOpcode::GC_LABEL:
821 case TargetOpcode::DBG_VALUE:
826 /// Return the number of instructions inside the MI bundle, excluding the
829 /// This is the number of instructions that MachineBasicBlock::iterator
830 /// skips, 0 for unbundled instructions.
831 unsigned getBundleSize() const;
833 /// readsRegister - Return true if the MachineInstr reads the specified
834 /// register. If TargetRegisterInfo is passed, then it also checks if there
835 /// is a read of a super-register.
836 /// This does not count partial redefines of virtual registers as reads:
838 bool readsRegister(unsigned Reg,
839 const TargetRegisterInfo *TRI = nullptr) const {
840 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
843 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
844 /// virtual register. Take into account that a partial define is a
845 /// read-modify-write operation.
846 bool readsVirtualRegister(unsigned Reg) const {
847 return readsWritesVirtualRegister(Reg).first;
850 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
851 /// indicating if this instruction reads or writes Reg. This also considers
853 /// If Ops is not null, all operand indices for Reg are added.
854 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
855 SmallVectorImpl<unsigned> *Ops = nullptr) const;
857 /// killsRegister - Return true if the MachineInstr kills the specified
858 /// register. If TargetRegisterInfo is passed, then it also checks if there is
859 /// a kill of a super-register.
860 bool killsRegister(unsigned Reg,
861 const TargetRegisterInfo *TRI = nullptr) const {
862 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
865 /// definesRegister - Return true if the MachineInstr fully defines the
866 /// specified register. If TargetRegisterInfo is passed, then it also checks
867 /// if there is a def of a super-register.
868 /// NOTE: It's ignoring subreg indices on virtual registers.
869 bool definesRegister(unsigned Reg,
870 const TargetRegisterInfo *TRI = nullptr) const {
871 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
874 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
875 /// or partially define) the specified register.
876 /// NOTE: It's ignoring subreg indices on virtual registers.
877 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
878 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
881 /// registerDefIsDead - Returns true if the register is dead in this machine
882 /// instruction. If TargetRegisterInfo is passed, then it also checks
883 /// if there is a dead def of a super-register.
884 bool registerDefIsDead(unsigned Reg,
885 const TargetRegisterInfo *TRI = nullptr) const {
886 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
889 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
890 /// the specific register or -1 if it is not found. It further tightens
891 /// the search criteria to a use that kills the register if isKill is true.
892 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
893 const TargetRegisterInfo *TRI = nullptr) const;
895 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
896 /// a pointer to the MachineOperand rather than an index.
897 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
898 const TargetRegisterInfo *TRI = nullptr) {
899 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
900 return (Idx == -1) ? nullptr : &getOperand(Idx);
903 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
904 /// the specified register or -1 if it is not found. If isDead is true, defs
905 /// that are not dead are skipped. If Overlap is true, then it also looks for
906 /// defs that merely overlap the specified register. If TargetRegisterInfo is
907 /// non-null, then it also checks if there is a def of a super-register.
908 /// This may also return a register mask operand when Overlap is true.
909 int findRegisterDefOperandIdx(unsigned Reg,
910 bool isDead = false, bool Overlap = false,
911 const TargetRegisterInfo *TRI = nullptr) const;
913 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
914 /// a pointer to the MachineOperand rather than an index.
915 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
916 const TargetRegisterInfo *TRI = nullptr) {
917 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
918 return (Idx == -1) ? nullptr : &getOperand(Idx);
921 /// findFirstPredOperandIdx() - Find the index of the first operand in the
922 /// operand list that is used to represent the predicate. It returns -1 if
924 int findFirstPredOperandIdx() const;
926 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
927 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
928 /// getOperand(OpIdx) does not belong to an inline asm operand group.
930 /// If GroupNo is not NULL, it will receive the number of the operand group
931 /// containing OpIdx.
933 /// The flag operand is an immediate that can be decoded with methods like
934 /// InlineAsm::hasRegClassConstraint().
936 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
938 /// getRegClassConstraint - Compute the static register class constraint for
939 /// operand OpIdx. For normal instructions, this is derived from the
940 /// MCInstrDesc. For inline assembly it is derived from the flag words.
942 /// Returns NULL if the static register classs constraint cannot be
945 const TargetRegisterClass*
946 getRegClassConstraint(unsigned OpIdx,
947 const TargetInstrInfo *TII,
948 const TargetRegisterInfo *TRI) const;
950 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
951 /// the given \p CurRC.
952 /// If \p ExploreBundle is set and MI is part of a bundle, all the
953 /// instructions inside the bundle will be taken into account. In other words,
954 /// this method accumulates all the constrains of the operand of this MI and
955 /// the related bundle if MI is a bundle or inside a bundle.
957 /// Returns the register class that statisfies both \p CurRC and the
958 /// constraints set by MI. Returns NULL if such a register class does not
961 /// \pre CurRC must not be NULL.
962 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
963 unsigned Reg, const TargetRegisterClass *CurRC,
964 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
965 bool ExploreBundle = false) const;
967 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
968 /// to the given \p CurRC.
970 /// Returns the register class that statisfies both \p CurRC and the
971 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
974 /// \pre CurRC must not be NULL.
975 /// \pre The operand at \p OpIdx must be a register.
976 const TargetRegisterClass *
977 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
978 const TargetInstrInfo *TII,
979 const TargetRegisterInfo *TRI) const;
981 /// tieOperands - Add a tie between the register operands at DefIdx and
982 /// UseIdx. The tie will cause the register allocator to ensure that the two
983 /// operands are assigned the same physical register.
985 /// Tied operands are managed automatically for explicit operands in the
986 /// MCInstrDesc. This method is for exceptional cases like inline asm.
987 void tieOperands(unsigned DefIdx, unsigned UseIdx);
989 /// findTiedOperandIdx - Given the index of a tied register operand, find the
990 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
991 /// index of the tied operand which must exist.
992 unsigned findTiedOperandIdx(unsigned OpIdx) const;
994 /// isRegTiedToUseOperand - Given the index of a register def operand,
995 /// check if the register def is tied to a source operand, due to either
996 /// two-address elimination or inline assembly constraints. Returns the
997 /// first tied use operand index by reference if UseOpIdx is not null.
998 bool isRegTiedToUseOperand(unsigned DefOpIdx,
999 unsigned *UseOpIdx = nullptr) const {
1000 const MachineOperand &MO = getOperand(DefOpIdx);
1001 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1004 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1008 /// isRegTiedToDefOperand - Return true if the use operand of the specified
1009 /// index is tied to a def operand. It also returns the def operand index by
1010 /// reference if DefOpIdx is not null.
1011 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1012 unsigned *DefOpIdx = nullptr) const {
1013 const MachineOperand &MO = getOperand(UseOpIdx);
1014 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1017 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1021 /// clearKillInfo - Clears kill flags on all operands.
1023 void clearKillInfo();
1025 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
1026 /// properly composing subreg indices where necessary.
1027 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1028 const TargetRegisterInfo &RegInfo);
1030 /// addRegisterKilled - We have determined MI kills a register. Look for the
1031 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1032 /// add a implicit operand if it's not found. Returns true if the operand
1033 /// exists / is added.
1034 bool addRegisterKilled(unsigned IncomingReg,
1035 const TargetRegisterInfo *RegInfo,
1036 bool AddIfNotFound = false);
1038 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
1039 /// provided, this includes super-register kills.
1040 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1042 /// addRegisterDead - We have determined MI defined a register without a use.
1043 /// Look for the operand that defines it and mark it as IsDead. If
1044 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1045 /// true if the operand exists / is added.
1046 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1047 bool AddIfNotFound = false);
1049 /// Clear all dead flags on operands defining register @p Reg.
1050 void clearRegisterDeads(unsigned Reg);
1052 /// Mark all subregister defs of register @p Reg with the undef flag.
1053 /// This function is used when we determined to have a subregister def in an
1054 /// otherwise undefined super register.
1055 void addRegisterDefReadUndef(unsigned Reg);
1057 /// addRegisterDefined - We have determined MI defines a register. Make sure
1058 /// there is an operand defining Reg.
1059 void addRegisterDefined(unsigned Reg,
1060 const TargetRegisterInfo *RegInfo = nullptr);
1062 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
1063 /// dead except those in the UsedRegs list.
1065 /// On instructions with register mask operands, also add implicit-def
1066 /// operands for all registers in UsedRegs.
1067 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1068 const TargetRegisterInfo &TRI);
1070 /// isSafeToMove - Return true if it is safe to move this instruction. If
1071 /// SawStore is set to true, it means that there is a store (or call) between
1072 /// the instruction's location and its intended destination.
1073 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
1074 bool &SawStore) const;
1076 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1077 /// or volatile memory reference, or if the information describing the memory
1078 /// reference is not available. Return false if it is known to have no
1079 /// ordered or volatile memory references.
1080 bool hasOrderedMemoryRef() const;
1082 /// isInvariantLoad - Return true if this instruction is loading from a
1083 /// location whose value is invariant across the function. For example,
1084 /// loading a value from the constant pool or from the argument area of
1085 /// a function if it does not change. This should only return true of *all*
1086 /// loads the instruction does are invariant (if it does multiple loads).
1087 bool isInvariantLoad(AliasAnalysis *AA) const;
1089 /// isConstantValuePHI - If the specified instruction is a PHI that always
1090 /// merges together the same virtual register, return the register, otherwise
1092 unsigned isConstantValuePHI() const;
1094 /// hasUnmodeledSideEffects - Return true if this instruction has side
1095 /// effects that are not modeled by mayLoad / mayStore, etc.
1096 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1097 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1098 /// INLINEASM instruction, in which case the side effect property is encoded
1099 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1101 bool hasUnmodeledSideEffects() const;
1103 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1105 bool allDefsAreDead() const;
1107 /// copyImplicitOps - Copy implicit register operands from specified
1108 /// instruction to this instruction.
1109 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1112 // Debugging support
1114 void print(raw_ostream &OS, bool SkipOpers = false) const;
1117 //===--------------------------------------------------------------------===//
1118 // Accessors used to build up machine instructions.
1120 /// Add the specified operand to the instruction. If it is an implicit
1121 /// operand, it is added to the end of the operand list. If it is an
1122 /// explicit operand it is added at the end of the explicit operand list
1123 /// (before the first implicit operand).
1125 /// MF must be the machine function that was used to allocate this
1128 /// MachineInstrBuilder provides a more convenient interface for creating
1129 /// instructions and adding operands.
1130 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1132 /// Add an operand without providing an MF reference. This only works for
1133 /// instructions that are inserted in a basic block.
1135 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1137 void addOperand(const MachineOperand &Op);
1139 /// setDesc - Replace the instruction descriptor (thus opcode) of
1140 /// the current instruction with a new one.
1142 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1144 /// setDebugLoc - Replace current source information with new such.
1145 /// Avoid using this, the constructor argument is preferable.
1147 void setDebugLoc(DebugLoc dl) {
1148 debugLoc = std::move(dl);
1149 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1152 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
1153 /// fewer operand than it started with.
1155 void RemoveOperand(unsigned i);
1157 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
1158 /// This function should be used only occasionally. The setMemRefs function
1159 /// is the primary method for setting up a MachineInstr's MemRefs list.
1160 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1162 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1163 /// list. This does not transfer ownership.
1164 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1165 MemRefs = NewMemRefs;
1166 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1167 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1170 /// clearMemRefs - Clear this MachineInstr's memory reference descriptor list.
1171 void clearMemRefs() {
1177 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1178 /// return the MachineRegisterInfo object for the current function, otherwise
1180 MachineRegisterInfo *getRegInfo();
1182 /// untieRegOperand - Break any tie involving OpIdx.
1183 void untieRegOperand(unsigned OpIdx) {
1184 MachineOperand &MO = getOperand(OpIdx);
1185 if (MO.isReg() && MO.isTied()) {
1186 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1191 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1192 /// this instruction.
1193 void addImplicitDefUseOperands(MachineFunction &MF);
1195 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1196 /// this instruction from their respective use lists. This requires that the
1197 /// operands already be on their use lists.
1198 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1200 /// AddRegOperandsToUseLists - Add all of the register operands in
1201 /// this instruction from their respective use lists. This requires that the
1202 /// operands not be on their use lists yet.
1203 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1205 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1207 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1209 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1210 /// this MI and the given operand index \p OpIdx.
1211 /// If the related operand does not constrained Reg, this returns CurRC.
1212 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1213 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1214 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1217 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1218 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1219 /// The hashing and equality testing functions ignore definitions so this is
1220 /// useful for CSE, etc.
1221 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1222 static inline MachineInstr *getEmptyKey() {
1226 static inline MachineInstr *getTombstoneKey() {
1227 return reinterpret_cast<MachineInstr*>(-1);
1230 static unsigned getHashValue(const MachineInstr* const &MI);
1232 static bool isEqual(const MachineInstr* const &LHS,
1233 const MachineInstr* const &RHS) {
1234 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1235 LHS == getEmptyKey() || LHS == getTombstoneKey())
1237 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1241 //===----------------------------------------------------------------------===//
1242 // Debugging Support
1244 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1249 } // End llvm namespace