1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ilist.h"
20 #include "llvm/ADT/ilist_node.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/Target/TargetInstrDesc.h"
30 class TargetInstrDesc;
31 class TargetInstrInfo;
32 class TargetRegisterInfo;
33 class MachineFunction;
35 //===----------------------------------------------------------------------===//
36 /// MachineInstr - Representation of each machine instruction.
38 class MachineInstr : public ilist_node<MachineInstr> {
39 const TargetInstrDesc *TID; // Instruction descriptor.
40 unsigned short NumImplicitOps; // Number of implicit operands (which
41 // are determined at construction time).
43 std::vector<MachineOperand> Operands; // the operands
44 std::list<MachineMemOperand> MemOperands; // information on memory references
45 MachineBasicBlock *Parent; // Pointer to the owning basic block.
47 // OperandComplete - Return true if it's illegal to add a new operand
48 bool OperandsComplete() const;
50 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
51 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
53 // Intrusive list support
54 friend struct ilist_traits<MachineInstr>;
55 friend struct ilist_traits<MachineBasicBlock>;
56 friend struct ilist_sentinel_traits<MachineInstr>;
57 void setParent(MachineBasicBlock *P) { Parent = P; }
59 /// MachineInstr ctor - This constructor creates a copy of the given
60 /// MachineInstr in the given MachineFunction.
61 MachineInstr(MachineFunction &, const MachineInstr &);
63 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
64 /// TID NULL and no operands.
67 /// MachineInstr ctor - This constructor create a MachineInstr and add the
68 /// implicit operands. It reserves space for number of operands specified by
70 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
72 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
73 /// the MachineInstr is created and added to the end of the specified basic
76 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
80 // MachineInstrs are pool-allocated and owned by MachineFunction.
81 friend class MachineFunction;
84 const MachineBasicBlock* getParent() const { return Parent; }
85 MachineBasicBlock* getParent() { return Parent; }
87 /// getDesc - Returns the target instruction descriptor of this
89 const TargetInstrDesc &getDesc() const { return *TID; }
91 /// getOpcode - Returns the opcode of this MachineInstr.
93 int getOpcode() const { return TID->Opcode; }
95 /// Access to explicit operands of the instruction.
97 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
99 const MachineOperand& getOperand(unsigned i) const {
100 assert(i < getNumOperands() && "getOperand() out of range!");
103 MachineOperand& getOperand(unsigned i) {
104 assert(i < getNumOperands() && "getOperand() out of range!");
108 /// getNumExplicitOperands - Returns the number of non-implicit operands.
110 unsigned getNumExplicitOperands() const;
112 /// Access to memory operands of the instruction
113 std::list<MachineMemOperand>::iterator memoperands_begin()
114 { return MemOperands.begin(); }
115 std::list<MachineMemOperand>::iterator memoperands_end()
116 { return MemOperands.end(); }
117 std::list<MachineMemOperand>::const_iterator memoperands_begin() const
118 { return MemOperands.begin(); }
119 std::list<MachineMemOperand>::const_iterator memoperands_end() const
120 { return MemOperands.end(); }
121 bool memoperands_empty() const { return MemOperands.empty(); }
123 /// hasOneMemOperand - Return true if this instruction has exactly one
124 /// MachineMemOperand.
125 bool hasOneMemOperand() const {
126 return !memoperands_empty() &&
127 next(memoperands_begin()) == memoperands_end();
130 /// isIdenticalTo - Return true if this instruction is identical to (same
131 /// opcode and same operands as) the specified instruction.
132 bool isIdenticalTo(const MachineInstr *Other) const {
133 if (Other->getOpcode() != getOpcode() ||
134 Other->getNumOperands() != getNumOperands())
136 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
137 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
142 /// removeFromParent - This method unlinks 'this' from the containing basic
143 /// block, and returns it, but does not delete it.
144 MachineInstr *removeFromParent();
146 /// eraseFromParent - This method unlinks 'this' from the containing basic
147 /// block and deletes it.
148 void eraseFromParent();
150 /// isLabel - Returns true if the MachineInstr represents a label.
152 bool isLabel() const;
154 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
156 bool isDebugLabel() const;
158 /// readsRegister - Return true if the MachineInstr reads the specified
159 /// register. If TargetRegisterInfo is passed, then it also checks if there
160 /// is a read of a super-register.
161 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
162 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
165 /// killsRegister - Return true if the MachineInstr kills the specified
166 /// register. If TargetRegisterInfo is passed, then it also checks if there is
167 /// a kill of a super-register.
168 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
169 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
172 /// modifiesRegister - Return true if the MachineInstr modifies the
173 /// specified register. If TargetRegisterInfo is passed, then it also checks
174 /// if there is a def of a super-register.
175 bool modifiesRegister(unsigned Reg,
176 const TargetRegisterInfo *TRI = NULL) const {
177 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
180 /// registerDefIsDead - Returns true if the register is dead in this machine
181 /// instruction. If TargetRegisterInfo is passed, then it also checks
182 /// if there is a dead def of a super-register.
183 bool registerDefIsDead(unsigned Reg,
184 const TargetRegisterInfo *TRI = NULL) const {
185 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
188 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
189 /// the specific register or -1 if it is not found. It further tightening
190 /// the search criteria to a use that kills the register if isKill is true.
191 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
192 const TargetRegisterInfo *TRI = NULL) const;
194 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
195 /// a pointer to the MachineOperand rather than an index.
196 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
197 const TargetRegisterInfo *TRI = NULL) {
198 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
199 return (Idx == -1) ? NULL : &getOperand(Idx);
202 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
203 /// the specified register or -1 if it is not found. If isDead is true, defs
204 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
205 /// also checks if there is a def of a super-register.
206 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
207 const TargetRegisterInfo *TRI = NULL) const;
209 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
210 /// a pointer to the MachineOperand rather than an index.
211 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
212 const TargetRegisterInfo *TRI = NULL) {
213 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
214 return (Idx == -1) ? NULL : &getOperand(Idx);
217 /// findFirstPredOperandIdx() - Find the index of the first operand in the
218 /// operand list that is used to represent the predicate. It returns -1 if
220 int findFirstPredOperandIdx() const;
222 /// isRegReDefinedByTwoAddr - Given the index of a register def operand,
223 /// check if the register def is a re-definition due to two addr elimination.
224 bool isRegReDefinedByTwoAddr(unsigned DefIdx) const;
226 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
228 void copyKillDeadInfo(const MachineInstr *MI);
230 /// copyPredicates - Copies predicate operand(s) from MI.
231 void copyPredicates(const MachineInstr *MI);
233 /// addRegisterKilled - We have determined MI kills a register. Look for the
234 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
235 /// add a implicit operand if it's not found. Returns true if the operand
236 /// exists / is added.
237 bool addRegisterKilled(unsigned IncomingReg,
238 const TargetRegisterInfo *RegInfo,
239 bool AddIfNotFound = false);
241 /// addRegisterDead - We have determined MI defined a register without a use.
242 /// Look for the operand that defines it and mark it as IsDead. If
243 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
244 /// true if the operand exists / is added.
245 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
246 bool AddIfNotFound = false);
248 /// isSafeToMove - Return true if it is safe to move this instruction. If
249 /// SawStore is set to true, it means that there is a store (or call) between
250 /// the instruction's location and its intended destination.
251 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) const;
253 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
254 /// instruction which defined the specified register instead of copying it.
255 bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) const;
257 /// hasVolatileMemoryRef - Return true if this instruction may have a
258 /// volatile memory reference, or if the information describing the
259 /// memory reference is not available. Return false if it is known to
260 /// have no volatile memory references.
261 bool hasVolatileMemoryRef() const;
266 void print(std::ostream *OS, const TargetMachine *TM) const {
267 if (OS) print(*OS, TM);
269 void print(std::ostream &OS, const TargetMachine *TM = 0) const;
270 void print(std::ostream *OS) const { if (OS) print(*OS); }
271 void print(raw_ostream *OS, const TargetMachine *TM) const {
272 if (OS) print(*OS, TM);
274 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
275 void print(raw_ostream *OS) const { if (OS) print(*OS); }
278 //===--------------------------------------------------------------------===//
279 // Accessors used to build up machine instructions.
281 /// addOperand - Add the specified operand to the instruction. If it is an
282 /// implicit operand, it is added to the end of the operand list. If it is
283 /// an explicit operand it is added at the end of the explicit operand list
284 /// (before the first implicit operand).
285 void addOperand(const MachineOperand &Op);
287 /// setDesc - Replace the instruction descriptor (thus opcode) of
288 /// the current instruction with a new one.
290 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
292 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
293 /// fewer operand than it started with.
295 void RemoveOperand(unsigned i);
297 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
298 /// referencing arbitrary storage.
299 void addMemOperand(MachineFunction &MF,
300 const MachineMemOperand &MO);
302 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
303 void clearMemOperands(MachineFunction &MF);
306 /// getRegInfo - If this instruction is embedded into a MachineFunction,
307 /// return the MachineRegisterInfo object for the current function, otherwise
309 MachineRegisterInfo *getRegInfo();
311 /// addImplicitDefUseOperands - Add all implicit def and use operands to
312 /// this instruction.
313 void addImplicitDefUseOperands();
315 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
316 /// this instruction from their respective use lists. This requires that the
317 /// operands already be on their use lists.
318 void RemoveRegOperandsFromUseLists();
320 /// AddRegOperandsToUseLists - Add all of the register operands in
321 /// this instruction from their respective use lists. This requires that the
322 /// operands not be on their use lists yet.
323 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
326 //===----------------------------------------------------------------------===//
329 inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
334 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
339 } // End llvm namespace