1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/DebugLoc.h"
29 #include "llvm/Target/TargetOpcodes.h"
34 template <typename T> class SmallVectorImpl;
36 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
39 class MachineFunction;
40 class MachineMemOperand;
42 //===----------------------------------------------------------------------===//
43 /// MachineInstr - Representation of each machine instruction.
45 class MachineInstr : public ilist_node<MachineInstr> {
47 typedef MachineMemOperand **mmo_iterator;
49 /// Flags to specify different kinds of comments to output in
50 /// assembly code. These flags carry semantic information not
51 /// otherwise easily derivable from the IR text.
59 FrameSetup = 1 << 0, // Instruction is used as a part of
60 // function frame setup code.
61 BundledPred = 1 << 1, // Instruction has bundled predecessors.
62 BundledSucc = 1 << 2 // Instruction has bundled successors.
65 const MCInstrDesc *MCID; // Instruction descriptor.
67 uint8_t Flags; // Various bits of additional
68 // information about machine
71 uint8_t AsmPrinterFlags; // Various bits of information used by
72 // the AsmPrinter to emit helpful
73 // comments. This is *not* semantic
74 // information. Do not use this for
75 // anything other than to convey comment
76 // information to AsmPrinter.
78 uint16_t NumMemRefs; // information on memory references
81 std::vector<MachineOperand> Operands; // the operands
82 MachineBasicBlock *Parent; // Pointer to the owning basic block.
83 DebugLoc debugLoc; // Source line information.
85 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
86 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
88 // Intrusive list support
89 friend struct ilist_traits<MachineInstr>;
90 friend struct ilist_traits<MachineBasicBlock>;
91 void setParent(MachineBasicBlock *P) { Parent = P; }
93 /// MachineInstr ctor - This constructor creates a copy of the given
94 /// MachineInstr in the given MachineFunction.
95 MachineInstr(MachineFunction &, const MachineInstr &);
97 /// MachineInstr ctor - This constructor create a MachineInstr and add the
98 /// implicit operands. It reserves space for number of operands specified by
99 /// MCInstrDesc. An explicit DebugLoc is supplied.
100 MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = false);
104 // MachineInstrs are pool-allocated and owned by MachineFunction.
105 friend class MachineFunction;
108 const MachineBasicBlock* getParent() const { return Parent; }
109 MachineBasicBlock* getParent() { return Parent; }
111 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
113 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
115 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
117 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
119 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
121 bool getAsmPrinterFlag(CommentFlag Flag) const {
122 return AsmPrinterFlags & Flag;
125 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
127 void setAsmPrinterFlag(CommentFlag Flag) {
128 AsmPrinterFlags |= (uint8_t)Flag;
131 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
133 void clearAsmPrinterFlag(CommentFlag Flag) {
134 AsmPrinterFlags &= ~Flag;
137 /// getFlags - Return the MI flags bitvector.
138 uint8_t getFlags() const {
142 /// getFlag - Return whether an MI flag is set.
143 bool getFlag(MIFlag Flag) const {
147 /// setFlag - Set a MI flag.
148 void setFlag(MIFlag Flag) {
149 Flags |= (uint8_t)Flag;
152 void setFlags(unsigned flags) {
156 /// clearFlag - Clear a MI flag.
157 void clearFlag(MIFlag Flag) {
158 Flags &= ~((uint8_t)Flag);
161 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
164 /// A bundle looks like this before it's finalized:
176 /// In this case, the first MI starts a bundle but is not inside a bundle, the
177 /// next 2 MIs are considered "inside" the bundle.
179 /// After a bundle is finalized, it looks like this:
195 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
196 /// a bundle, but the next three MIs are.
197 bool isInsideBundle() const {
198 return getFlag(BundledPred);
201 /// setIsInsideBundle - Set InsideBundle bit.
203 void setIsInsideBundle(bool Val = true) {
205 setFlag(BundledPred);
207 clearFlag(BundledPred);
210 /// isBundled - Return true if this instruction part of a bundle. This is true
211 /// if either itself or its following instruction is marked "InsideBundle".
212 bool isBundled() const;
214 /// Return true if this instruction is part of a bundle, and it is not the
215 /// first instruction in the bundle.
216 bool isBundledWithPred() const { return getFlag(BundledPred); }
218 /// Return true if this instruction is part of a bundle, and it is not the
219 /// last instruction in the bundle.
220 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
222 /// Bundle this instruction with its predecessor. This can be an unbundled
223 /// instruction, or it can be the first instruction in a bundle.
224 void bundleWithPred();
226 /// Bundle this instruction with its successor. This can be an unbundled
227 /// instruction, or it can be the last instruction in a bundle.
228 void bundleWithSucc();
230 /// Break bundle above this instruction.
231 void unbundleFromPred();
233 /// Break bundle below this instruction.
234 void unbundleFromSucc();
236 /// getDebugLoc - Returns the debug location id of this MachineInstr.
238 DebugLoc getDebugLoc() const { return debugLoc; }
240 /// emitError - Emit an error referring to the source location of this
241 /// instruction. This should only be used for inline assembly that is somehow
242 /// impossible to compile. Other errors should have been handled much
245 /// If this method returns, the caller should try to recover from the error.
247 void emitError(StringRef Msg) const;
249 /// getDesc - Returns the target instruction descriptor of this
251 const MCInstrDesc &getDesc() const { return *MCID; }
253 /// getOpcode - Returns the opcode of this MachineInstr.
255 int getOpcode() const { return MCID->Opcode; }
257 /// Access to explicit operands of the instruction.
259 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
261 const MachineOperand& getOperand(unsigned i) const {
262 assert(i < getNumOperands() && "getOperand() out of range!");
265 MachineOperand& getOperand(unsigned i) {
266 assert(i < getNumOperands() && "getOperand() out of range!");
270 /// getNumExplicitOperands - Returns the number of non-implicit operands.
272 unsigned getNumExplicitOperands() const;
274 /// iterator/begin/end - Iterate over all operands of a machine instruction.
275 typedef std::vector<MachineOperand>::iterator mop_iterator;
276 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
278 mop_iterator operands_begin() { return Operands.begin(); }
279 mop_iterator operands_end() { return Operands.end(); }
281 const_mop_iterator operands_begin() const { return Operands.begin(); }
282 const_mop_iterator operands_end() const { return Operands.end(); }
284 /// Access to memory operands of the instruction
285 mmo_iterator memoperands_begin() const { return MemRefs; }
286 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
287 bool memoperands_empty() const { return NumMemRefs == 0; }
289 /// hasOneMemOperand - Return true if this instruction has exactly one
290 /// MachineMemOperand.
291 bool hasOneMemOperand() const {
292 return NumMemRefs == 1;
295 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
296 /// queries but they are bundle aware.
299 IgnoreBundle, // Ignore bundles
300 AnyInBundle, // Return true if any instruction in bundle has property
301 AllInBundle // Return true if all instructions in bundle have property
304 /// hasProperty - Return true if the instruction (or in the case of a bundle,
305 /// the instructions inside the bundle) has the specified property.
306 /// The first argument is the property being queried.
307 /// The second argument indicates whether the query should look inside
308 /// instruction bundles.
309 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
310 // Inline the fast path.
311 if (Type == IgnoreBundle || !isBundle())
312 return getDesc().getFlags() & (1 << MCFlag);
314 // If we have a bundle, take the slow path.
315 return hasPropertyInBundle(1 << MCFlag, Type);
318 /// isVariadic - Return true if this instruction can have a variable number of
319 /// operands. In this case, the variable operands will be after the normal
320 /// operands but before the implicit definitions and uses (if any are
322 bool isVariadic(QueryType Type = IgnoreBundle) const {
323 return hasProperty(MCID::Variadic, Type);
326 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
327 /// ARM instructions which can set condition code if 's' bit is set.
328 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
329 return hasProperty(MCID::HasOptionalDef, Type);
332 /// isPseudo - Return true if this is a pseudo instruction that doesn't
333 /// correspond to a real machine instruction.
335 bool isPseudo(QueryType Type = IgnoreBundle) const {
336 return hasProperty(MCID::Pseudo, Type);
339 bool isReturn(QueryType Type = AnyInBundle) const {
340 return hasProperty(MCID::Return, Type);
343 bool isCall(QueryType Type = AnyInBundle) const {
344 return hasProperty(MCID::Call, Type);
347 /// isBarrier - Returns true if the specified instruction stops control flow
348 /// from executing the instruction immediately following it. Examples include
349 /// unconditional branches and return instructions.
350 bool isBarrier(QueryType Type = AnyInBundle) const {
351 return hasProperty(MCID::Barrier, Type);
354 /// isTerminator - Returns true if this instruction part of the terminator for
355 /// a basic block. Typically this is things like return and branch
358 /// Various passes use this to insert code into the bottom of a basic block,
359 /// but before control flow occurs.
360 bool isTerminator(QueryType Type = AnyInBundle) const {
361 return hasProperty(MCID::Terminator, Type);
364 /// isBranch - Returns true if this is a conditional, unconditional, or
365 /// indirect branch. Predicates below can be used to discriminate between
366 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
367 /// get more information.
368 bool isBranch(QueryType Type = AnyInBundle) const {
369 return hasProperty(MCID::Branch, Type);
372 /// isIndirectBranch - Return true if this is an indirect branch, such as a
373 /// branch through a register.
374 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
375 return hasProperty(MCID::IndirectBranch, Type);
378 /// isConditionalBranch - Return true if this is a branch which may fall
379 /// through to the next instruction or may transfer control flow to some other
380 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
381 /// information about this branch.
382 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
383 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
386 /// isUnconditionalBranch - Return true if this is a branch which always
387 /// transfers control flow to some other block. The
388 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
389 /// about this branch.
390 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
391 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
394 // isPredicable - Return true if this instruction has a predicate operand that
395 // controls execution. It may be set to 'always', or may be set to other
396 /// values. There are various methods in TargetInstrInfo that can be used to
397 /// control and modify the predicate in this instruction.
398 bool isPredicable(QueryType Type = AllInBundle) const {
399 // If it's a bundle than all bundled instructions must be predicable for this
401 return hasProperty(MCID::Predicable, Type);
404 /// isCompare - Return true if this instruction is a comparison.
405 bool isCompare(QueryType Type = IgnoreBundle) const {
406 return hasProperty(MCID::Compare, Type);
409 /// isMoveImmediate - Return true if this instruction is a move immediate
410 /// (including conditional moves) instruction.
411 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
412 return hasProperty(MCID::MoveImm, Type);
415 /// isBitcast - Return true if this instruction is a bitcast instruction.
417 bool isBitcast(QueryType Type = IgnoreBundle) const {
418 return hasProperty(MCID::Bitcast, Type);
421 /// isSelect - Return true if this instruction is a select instruction.
423 bool isSelect(QueryType Type = IgnoreBundle) const {
424 return hasProperty(MCID::Select, Type);
427 /// isNotDuplicable - Return true if this instruction cannot be safely
428 /// duplicated. For example, if the instruction has a unique labels attached
429 /// to it, duplicating it would cause multiple definition errors.
430 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
431 return hasProperty(MCID::NotDuplicable, Type);
434 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
435 /// which must be filled by the code generator.
436 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
437 return hasProperty(MCID::DelaySlot, Type);
440 /// canFoldAsLoad - Return true for instructions that can be folded as
441 /// memory operands in other instructions. The most common use for this
442 /// is instructions that are simple loads from memory that don't modify
443 /// the loaded value in any way, but it can also be used for instructions
444 /// that can be expressed as constant-pool loads, such as V_SETALLONES
445 /// on x86, to allow them to be folded when it is beneficial.
446 /// This should only be set on instructions that return a value in their
447 /// only virtual register definition.
448 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
449 return hasProperty(MCID::FoldableAsLoad, Type);
452 //===--------------------------------------------------------------------===//
453 // Side Effect Analysis
454 //===--------------------------------------------------------------------===//
456 /// mayLoad - Return true if this instruction could possibly read memory.
457 /// Instructions with this flag set are not necessarily simple load
458 /// instructions, they may load a value and modify it, for example.
459 bool mayLoad(QueryType Type = AnyInBundle) const {
461 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
462 if (ExtraInfo & InlineAsm::Extra_MayLoad)
465 return hasProperty(MCID::MayLoad, Type);
469 /// mayStore - Return true if this instruction could possibly modify memory.
470 /// Instructions with this flag set are not necessarily simple store
471 /// instructions, they may store a modified value based on their operands, or
472 /// may not actually modify anything, for example.
473 bool mayStore(QueryType Type = AnyInBundle) const {
475 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
476 if (ExtraInfo & InlineAsm::Extra_MayStore)
479 return hasProperty(MCID::MayStore, Type);
482 //===--------------------------------------------------------------------===//
483 // Flags that indicate whether an instruction can be modified by a method.
484 //===--------------------------------------------------------------------===//
486 /// isCommutable - Return true if this may be a 2- or 3-address
487 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
488 /// result if Y and Z are exchanged. If this flag is set, then the
489 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
492 /// Note that this flag may be set on instructions that are only commutable
493 /// sometimes. In these cases, the call to commuteInstruction will fail.
494 /// Also note that some instructions require non-trivial modification to
496 bool isCommutable(QueryType Type = IgnoreBundle) const {
497 return hasProperty(MCID::Commutable, Type);
500 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
501 /// which can be changed into a 3-address instruction if needed. Doing this
502 /// transformation can be profitable in the register allocator, because it
503 /// means that the instruction can use a 2-address form if possible, but
504 /// degrade into a less efficient form if the source and dest register cannot
505 /// be assigned to the same register. For example, this allows the x86
506 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
507 /// is the same speed as the shift but has bigger code size.
509 /// If this returns true, then the target must implement the
510 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
511 /// is allowed to fail if the transformation isn't valid for this specific
512 /// instruction (e.g. shl reg, 4 on x86).
514 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
515 return hasProperty(MCID::ConvertibleTo3Addr, Type);
518 /// usesCustomInsertionHook - Return true if this instruction requires
519 /// custom insertion support when the DAG scheduler is inserting it into a
520 /// machine basic block. If this is true for the instruction, it basically
521 /// means that it is a pseudo instruction used at SelectionDAG time that is
522 /// expanded out into magic code by the target when MachineInstrs are formed.
524 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
525 /// is used to insert this into the MachineBasicBlock.
526 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
527 return hasProperty(MCID::UsesCustomInserter, Type);
530 /// hasPostISelHook - Return true if this instruction requires *adjustment*
531 /// after instruction selection by calling a target hook. For example, this
532 /// can be used to fill in ARM 's' optional operand depending on whether
533 /// the conditional flag register is used.
534 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
535 return hasProperty(MCID::HasPostISelHook, Type);
538 /// isRematerializable - Returns true if this instruction is a candidate for
539 /// remat. This flag is deprecated, please don't use it anymore. If this
540 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
541 /// verify the instruction is really rematable.
542 bool isRematerializable(QueryType Type = AllInBundle) const {
543 // It's only possible to re-mat a bundle if all bundled instructions are
544 // re-materializable.
545 return hasProperty(MCID::Rematerializable, Type);
548 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
549 /// less) than a move instruction. This is useful during certain types of
550 /// optimizations (e.g., remat during two-address conversion or machine licm)
551 /// where we would like to remat or hoist the instruction, but not if it costs
552 /// more than moving the instruction into the appropriate register. Note, we
553 /// are not marking copies from and to the same register class with this flag.
554 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
555 // Only returns true for a bundle if all bundled instructions are cheap.
556 // FIXME: This probably requires a target hook.
557 return hasProperty(MCID::CheapAsAMove, Type);
560 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
561 /// have special register allocation requirements that are not captured by the
562 /// operand register classes. e.g. ARM::STRD's two source registers must be an
563 /// even / odd pair, ARM::STM registers have to be in ascending order.
564 /// Post-register allocation passes should not attempt to change allocations
565 /// for sources of instructions with this flag.
566 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
567 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
570 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
571 /// have special register allocation requirements that are not captured by the
572 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
573 /// even / odd pair, ARM::LDM registers have to be in ascending order.
574 /// Post-register allocation passes should not attempt to change allocations
575 /// for definitions of instructions with this flag.
576 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
577 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
582 CheckDefs, // Check all operands for equality
583 CheckKillDead, // Check all operands including kill / dead markers
584 IgnoreDefs, // Ignore all definitions
585 IgnoreVRegDefs // Ignore virtual register definitions
588 /// isIdenticalTo - Return true if this instruction is identical to (same
589 /// opcode and same operands as) the specified instruction.
590 bool isIdenticalTo(const MachineInstr *Other,
591 MICheckType Check = CheckDefs) const;
593 /// removeFromParent - This method unlinks 'this' from the containing basic
594 /// block, and returns it, but does not delete it.
595 MachineInstr *removeFromParent();
597 /// eraseFromParent - This method unlinks 'this' from the containing basic
598 /// block and deletes it.
599 void eraseFromParent();
601 /// isLabel - Returns true if the MachineInstr represents a label.
603 bool isLabel() const {
604 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
605 getOpcode() == TargetOpcode::EH_LABEL ||
606 getOpcode() == TargetOpcode::GC_LABEL;
609 bool isPrologLabel() const {
610 return getOpcode() == TargetOpcode::PROLOG_LABEL;
612 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
613 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
614 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
616 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
617 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
618 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
619 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
620 bool isStackAligningInlineAsm() const;
621 InlineAsm::AsmDialect getInlineAsmDialect() const;
622 bool isInsertSubreg() const {
623 return getOpcode() == TargetOpcode::INSERT_SUBREG;
625 bool isSubregToReg() const {
626 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
628 bool isRegSequence() const {
629 return getOpcode() == TargetOpcode::REG_SEQUENCE;
631 bool isBundle() const {
632 return getOpcode() == TargetOpcode::BUNDLE;
634 bool isCopy() const {
635 return getOpcode() == TargetOpcode::COPY;
637 bool isFullCopy() const {
638 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
641 /// isCopyLike - Return true if the instruction behaves like a copy.
642 /// This does not include native copy instructions.
643 bool isCopyLike() const {
644 return isCopy() || isSubregToReg();
647 /// isIdentityCopy - Return true is the instruction is an identity copy.
648 bool isIdentityCopy() const {
649 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
650 getOperand(0).getSubReg() == getOperand(1).getSubReg();
653 /// isTransient - Return true if this is a transient instruction that is
654 /// either very likely to be eliminated during register allocation (such as
655 /// copy-like instructions), or if this instruction doesn't have an
656 /// execution-time cost.
657 bool isTransient() const {
658 switch(getOpcode()) {
659 default: return false;
660 // Copy-like instructions are usually eliminated during register allocation.
661 case TargetOpcode::PHI:
662 case TargetOpcode::COPY:
663 case TargetOpcode::INSERT_SUBREG:
664 case TargetOpcode::SUBREG_TO_REG:
665 case TargetOpcode::REG_SEQUENCE:
666 // Pseudo-instructions that don't produce any real output.
667 case TargetOpcode::IMPLICIT_DEF:
668 case TargetOpcode::KILL:
669 case TargetOpcode::PROLOG_LABEL:
670 case TargetOpcode::EH_LABEL:
671 case TargetOpcode::GC_LABEL:
672 case TargetOpcode::DBG_VALUE:
677 /// getBundleSize - Return the number of instructions inside the MI bundle.
678 unsigned getBundleSize() const;
680 /// readsRegister - Return true if the MachineInstr reads the specified
681 /// register. If TargetRegisterInfo is passed, then it also checks if there
682 /// is a read of a super-register.
683 /// This does not count partial redefines of virtual registers as reads:
685 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
686 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
689 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
690 /// virtual register. Take into account that a partial define is a
691 /// read-modify-write operation.
692 bool readsVirtualRegister(unsigned Reg) const {
693 return readsWritesVirtualRegister(Reg).first;
696 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
697 /// indicating if this instruction reads or writes Reg. This also considers
699 /// If Ops is not null, all operand indices for Reg are added.
700 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
701 SmallVectorImpl<unsigned> *Ops = 0) const;
703 /// killsRegister - Return true if the MachineInstr kills the specified
704 /// register. If TargetRegisterInfo is passed, then it also checks if there is
705 /// a kill of a super-register.
706 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
707 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
710 /// definesRegister - Return true if the MachineInstr fully defines the
711 /// specified register. If TargetRegisterInfo is passed, then it also checks
712 /// if there is a def of a super-register.
713 /// NOTE: It's ignoring subreg indices on virtual registers.
714 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
715 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
718 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
719 /// or partially define) the specified register.
720 /// NOTE: It's ignoring subreg indices on virtual registers.
721 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
722 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
725 /// registerDefIsDead - Returns true if the register is dead in this machine
726 /// instruction. If TargetRegisterInfo is passed, then it also checks
727 /// if there is a dead def of a super-register.
728 bool registerDefIsDead(unsigned Reg,
729 const TargetRegisterInfo *TRI = NULL) const {
730 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
733 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
734 /// the specific register or -1 if it is not found. It further tightens
735 /// the search criteria to a use that kills the register if isKill is true.
736 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
737 const TargetRegisterInfo *TRI = NULL) const;
739 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
740 /// a pointer to the MachineOperand rather than an index.
741 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
742 const TargetRegisterInfo *TRI = NULL) {
743 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
744 return (Idx == -1) ? NULL : &getOperand(Idx);
747 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
748 /// the specified register or -1 if it is not found. If isDead is true, defs
749 /// that are not dead are skipped. If Overlap is true, then it also looks for
750 /// defs that merely overlap the specified register. If TargetRegisterInfo is
751 /// non-null, then it also checks if there is a def of a super-register.
752 /// This may also return a register mask operand when Overlap is true.
753 int findRegisterDefOperandIdx(unsigned Reg,
754 bool isDead = false, bool Overlap = false,
755 const TargetRegisterInfo *TRI = NULL) const;
757 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
758 /// a pointer to the MachineOperand rather than an index.
759 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
760 const TargetRegisterInfo *TRI = NULL) {
761 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
762 return (Idx == -1) ? NULL : &getOperand(Idx);
765 /// findFirstPredOperandIdx() - Find the index of the first operand in the
766 /// operand list that is used to represent the predicate. It returns -1 if
768 int findFirstPredOperandIdx() const;
770 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
771 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
772 /// getOperand(OpIdx) does not belong to an inline asm operand group.
774 /// If GroupNo is not NULL, it will receive the number of the operand group
775 /// containing OpIdx.
777 /// The flag operand is an immediate that can be decoded with methods like
778 /// InlineAsm::hasRegClassConstraint().
780 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
782 /// getRegClassConstraint - Compute the static register class constraint for
783 /// operand OpIdx. For normal instructions, this is derived from the
784 /// MCInstrDesc. For inline assembly it is derived from the flag words.
786 /// Returns NULL if the static register classs constraint cannot be
789 const TargetRegisterClass*
790 getRegClassConstraint(unsigned OpIdx,
791 const TargetInstrInfo *TII,
792 const TargetRegisterInfo *TRI) const;
794 /// tieOperands - Add a tie between the register operands at DefIdx and
795 /// UseIdx. The tie will cause the register allocator to ensure that the two
796 /// operands are assigned the same physical register.
798 /// Tied operands are managed automatically for explicit operands in the
799 /// MCInstrDesc. This method is for exceptional cases like inline asm.
800 void tieOperands(unsigned DefIdx, unsigned UseIdx);
802 /// findTiedOperandIdx - Given the index of a tied register operand, find the
803 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
804 /// index of the tied operand which must exist.
805 unsigned findTiedOperandIdx(unsigned OpIdx) const;
807 /// isRegTiedToUseOperand - Given the index of a register def operand,
808 /// check if the register def is tied to a source operand, due to either
809 /// two-address elimination or inline assembly constraints. Returns the
810 /// first tied use operand index by reference if UseOpIdx is not null.
811 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
812 const MachineOperand &MO = getOperand(DefOpIdx);
813 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
816 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
820 /// isRegTiedToDefOperand - Return true if the use operand of the specified
821 /// index is tied to an def operand. It also returns the def operand index by
822 /// reference if DefOpIdx is not null.
823 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
824 const MachineOperand &MO = getOperand(UseOpIdx);
825 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
828 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
832 /// clearKillInfo - Clears kill flags on all operands.
834 void clearKillInfo();
836 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
838 void copyKillDeadInfo(const MachineInstr *MI);
840 /// copyPredicates - Copies predicate operand(s) from MI.
841 void copyPredicates(const MachineInstr *MI);
843 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
844 /// properly composing subreg indices where necessary.
845 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
846 const TargetRegisterInfo &RegInfo);
848 /// addRegisterKilled - We have determined MI kills a register. Look for the
849 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
850 /// add a implicit operand if it's not found. Returns true if the operand
851 /// exists / is added.
852 bool addRegisterKilled(unsigned IncomingReg,
853 const TargetRegisterInfo *RegInfo,
854 bool AddIfNotFound = false);
856 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
857 /// provided, this includes super-register kills.
858 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
860 /// addRegisterDead - We have determined MI defined a register without a use.
861 /// Look for the operand that defines it and mark it as IsDead. If
862 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
863 /// true if the operand exists / is added.
864 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
865 bool AddIfNotFound = false);
867 /// addRegisterDefined - We have determined MI defines a register. Make sure
868 /// there is an operand defining Reg.
869 void addRegisterDefined(unsigned IncomingReg,
870 const TargetRegisterInfo *RegInfo = 0);
872 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
873 /// dead except those in the UsedRegs list.
875 /// On instructions with register mask operands, also add implicit-def
876 /// operands for all registers in UsedRegs.
877 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
878 const TargetRegisterInfo &TRI);
880 /// isSafeToMove - Return true if it is safe to move this instruction. If
881 /// SawStore is set to true, it means that there is a store (or call) between
882 /// the instruction's location and its intended destination.
883 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
884 bool &SawStore) const;
886 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
887 /// instruction which defined the specified register instead of copying it.
888 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
889 unsigned DstReg) const;
891 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
892 /// or volatile memory reference, or if the information describing the memory
893 /// reference is not available. Return false if it is known to have no
894 /// ordered or volatile memory references.
895 bool hasOrderedMemoryRef() const;
897 /// isInvariantLoad - Return true if this instruction is loading from a
898 /// location whose value is invariant across the function. For example,
899 /// loading a value from the constant pool or from the argument area of
900 /// a function if it does not change. This should only return true of *all*
901 /// loads the instruction does are invariant (if it does multiple loads).
902 bool isInvariantLoad(AliasAnalysis *AA) const;
904 /// isConstantValuePHI - If the specified instruction is a PHI that always
905 /// merges together the same virtual register, return the register, otherwise
907 unsigned isConstantValuePHI() const;
909 /// hasUnmodeledSideEffects - Return true if this instruction has side
910 /// effects that are not modeled by mayLoad / mayStore, etc.
911 /// For all instructions, the property is encoded in MCInstrDesc::Flags
912 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
913 /// INLINEASM instruction, in which case the side effect property is encoded
914 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
916 bool hasUnmodeledSideEffects() const;
918 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
920 bool allDefsAreDead() const;
922 /// copyImplicitOps - Copy implicit register operands from specified
923 /// instruction to this instruction.
924 void copyImplicitOps(const MachineInstr *MI);
929 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
932 //===--------------------------------------------------------------------===//
933 // Accessors used to build up machine instructions.
935 /// addOperand - Add the specified operand to the instruction. If it is an
936 /// implicit operand, it is added to the end of the operand list. If it is
937 /// an explicit operand it is added at the end of the explicit operand list
938 /// (before the first implicit operand).
939 void addOperand(const MachineOperand &Op);
941 /// setDesc - Replace the instruction descriptor (thus opcode) of
942 /// the current instruction with a new one.
944 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
946 /// setDebugLoc - Replace current source information with new such.
947 /// Avoid using this, the constructor argument is preferable.
949 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
951 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
952 /// fewer operand than it started with.
954 void RemoveOperand(unsigned i);
956 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
957 /// This function should be used only occasionally. The setMemRefs function
958 /// is the primary method for setting up a MachineInstr's MemRefs list.
959 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
961 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
962 /// list. This does not transfer ownership.
963 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
964 MemRefs = NewMemRefs;
965 NumMemRefs = NewMemRefsEnd - NewMemRefs;
969 /// getRegInfo - If this instruction is embedded into a MachineFunction,
970 /// return the MachineRegisterInfo object for the current function, otherwise
972 MachineRegisterInfo *getRegInfo();
974 /// untieRegOperand - Break any tie involving OpIdx.
975 void untieRegOperand(unsigned OpIdx) {
976 MachineOperand &MO = getOperand(OpIdx);
977 if (MO.isReg() && MO.isTied()) {
978 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
983 /// addImplicitDefUseOperands - Add all implicit def and use operands to
984 /// this instruction.
985 void addImplicitDefUseOperands();
987 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
988 /// this instruction from their respective use lists. This requires that the
989 /// operands already be on their use lists.
990 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
992 /// AddRegOperandsToUseLists - Add all of the register operands in
993 /// this instruction from their respective use lists. This requires that the
994 /// operands not be on their use lists yet.
995 void AddRegOperandsToUseLists(MachineRegisterInfo&);
997 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
999 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1002 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1003 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1004 /// The hashing and equality testing functions ignore definitions so this is
1005 /// useful for CSE, etc.
1006 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1007 static inline MachineInstr *getEmptyKey() {
1011 static inline MachineInstr *getTombstoneKey() {
1012 return reinterpret_cast<MachineInstr*>(-1);
1015 static unsigned getHashValue(const MachineInstr* const &MI);
1017 static bool isEqual(const MachineInstr* const &LHS,
1018 const MachineInstr* const &RHS) {
1019 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1020 LHS == getEmptyKey() || LHS == getTombstoneKey())
1022 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1026 //===----------------------------------------------------------------------===//
1027 // Debugging Support
1029 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1034 } // End llvm namespace