1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
56 FrameSetup = 1 << 0 // Instruction is used as a part of
57 // function frame setup code.
60 const MCInstrDesc *MCID; // Instruction descriptor.
61 uint16_t NumImplicitOps; // Number of implicit operands (which
62 // are determined at construction time).
64 uint8_t Flags; // Various bits of additional
65 // information about machine
68 uint8_t AsmPrinterFlags; // Various bits of information used by
69 // the AsmPrinter to emit helpful
70 // comments. This is *not* semantic
71 // information. Do not use this for
72 // anything other than to convey comment
73 // information to AsmPrinter.
75 std::vector<MachineOperand> Operands; // the operands
76 mmo_iterator MemRefs; // information on memory references
77 mmo_iterator MemRefsEnd;
78 MachineBasicBlock *Parent; // Pointer to the owning basic block.
79 DebugLoc debugLoc; // Source line information.
81 // OperandComplete - Return true if it's illegal to add a new operand
82 bool OperandsComplete() const;
84 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
85 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
87 // Intrusive list support
88 friend struct ilist_traits<MachineInstr>;
89 friend struct ilist_traits<MachineBasicBlock>;
90 void setParent(MachineBasicBlock *P) { Parent = P; }
92 /// MachineInstr ctor - This constructor creates a copy of the given
93 /// MachineInstr in the given MachineFunction.
94 MachineInstr(MachineFunction &, const MachineInstr &);
96 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
97 /// MCID NULL and no operands.
100 // The next two constructors have DebugLoc and non-DebugLoc versions;
101 // over time, the non-DebugLoc versions should be phased out and eventually
104 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
105 /// implicit operands. It reserves space for the number of operands specified
106 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
107 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
109 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
110 /// the MachineInstr is created and added to the end of the specified basic
111 /// block. The version with a DebugLoc should be preferred.
112 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
114 /// MachineInstr ctor - This constructor create a MachineInstr and add the
115 /// implicit operands. It reserves space for number of operands specified by
116 /// MCInstrDesc. An explicit DebugLoc is supplied.
117 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
120 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
121 /// the MachineInstr is created and added to the end of the specified basic
123 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
124 const MCInstrDesc &MCID);
128 // MachineInstrs are pool-allocated and owned by MachineFunction.
129 friend class MachineFunction;
132 const MachineBasicBlock* getParent() const { return Parent; }
133 MachineBasicBlock* getParent() { return Parent; }
135 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
137 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
139 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
141 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
143 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
145 bool getAsmPrinterFlag(CommentFlag Flag) const {
146 return AsmPrinterFlags & Flag;
149 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
151 void setAsmPrinterFlag(CommentFlag Flag) {
152 AsmPrinterFlags |= (uint8_t)Flag;
155 /// getFlags - Return the MI flags bitvector.
156 uint8_t getFlags() const {
160 /// getFlag - Return whether an MI flag is set.
161 bool getFlag(MIFlag Flag) const {
165 /// setFlag - Set a MI flag.
166 void setFlag(MIFlag Flag) {
167 Flags |= (uint8_t)Flag;
170 void setFlags(unsigned flags) {
174 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
176 void clearAsmPrinterFlag(CommentFlag Flag) {
177 AsmPrinterFlags &= ~Flag;
180 /// getDebugLoc - Returns the debug location id of this MachineInstr.
182 DebugLoc getDebugLoc() const { return debugLoc; }
184 /// emitError - Emit an error referring to the source location of this
185 /// instruction. This should only be used for inline assembly that is somehow
186 /// impossible to compile. Other errors should have been handled much
189 /// If this method returns, the caller should try to recover from the error.
191 void emitError(StringRef Msg) const;
193 /// getDesc - Returns the target instruction descriptor of this
195 const MCInstrDesc &getDesc() const { return *MCID; }
197 /// getOpcode - Returns the opcode of this MachineInstr.
199 int getOpcode() const { return MCID->Opcode; }
201 /// Access to explicit operands of the instruction.
203 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
205 const MachineOperand& getOperand(unsigned i) const {
206 assert(i < getNumOperands() && "getOperand() out of range!");
209 MachineOperand& getOperand(unsigned i) {
210 assert(i < getNumOperands() && "getOperand() out of range!");
214 /// getNumExplicitOperands - Returns the number of non-implicit operands.
216 unsigned getNumExplicitOperands() const;
218 /// iterator/begin/end - Iterate over all operands of a machine instruction.
219 typedef std::vector<MachineOperand>::iterator mop_iterator;
220 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
222 mop_iterator operands_begin() { return Operands.begin(); }
223 mop_iterator operands_end() { return Operands.end(); }
225 const_mop_iterator operands_begin() const { return Operands.begin(); }
226 const_mop_iterator operands_end() const { return Operands.end(); }
228 /// Access to memory operands of the instruction
229 mmo_iterator memoperands_begin() const { return MemRefs; }
230 mmo_iterator memoperands_end() const { return MemRefsEnd; }
231 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
233 /// hasOneMemOperand - Return true if this instruction has exactly one
234 /// MachineMemOperand.
235 bool hasOneMemOperand() const {
236 return MemRefsEnd - MemRefs == 1;
240 CheckDefs, // Check all operands for equality
241 CheckKillDead, // Check all operands including kill / dead markers
242 IgnoreDefs, // Ignore all definitions
243 IgnoreVRegDefs // Ignore virtual register definitions
246 /// isIdenticalTo - Return true if this instruction is identical to (same
247 /// opcode and same operands as) the specified instruction.
248 bool isIdenticalTo(const MachineInstr *Other,
249 MICheckType Check = CheckDefs) const;
251 /// removeFromParent - This method unlinks 'this' from the containing basic
252 /// block, and returns it, but does not delete it.
253 MachineInstr *removeFromParent();
255 /// eraseFromParent - This method unlinks 'this' from the containing basic
256 /// block and deletes it.
257 void eraseFromParent();
259 /// isLabel - Returns true if the MachineInstr represents a label.
261 bool isLabel() const {
262 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
263 getOpcode() == TargetOpcode::EH_LABEL ||
264 getOpcode() == TargetOpcode::GC_LABEL;
267 bool isPrologLabel() const {
268 return getOpcode() == TargetOpcode::PROLOG_LABEL;
270 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
271 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
272 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
274 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
275 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
276 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
277 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
278 bool isStackAligningInlineAsm() const;
279 bool isInsertSubreg() const {
280 return getOpcode() == TargetOpcode::INSERT_SUBREG;
282 bool isSubregToReg() const {
283 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
285 bool isRegSequence() const {
286 return getOpcode() == TargetOpcode::REG_SEQUENCE;
288 bool isCopy() const {
289 return getOpcode() == TargetOpcode::COPY;
291 bool isFullCopy() const {
292 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
295 /// isCopyLike - Return true if the instruction behaves like a copy.
296 /// This does not include native copy instructions.
297 bool isCopyLike() const {
298 return isCopy() || isSubregToReg();
301 /// isIdentityCopy - Return true is the instruction is an identity copy.
302 bool isIdentityCopy() const {
303 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
304 getOperand(0).getSubReg() == getOperand(1).getSubReg();
307 /// readsRegister - Return true if the MachineInstr reads the specified
308 /// register. If TargetRegisterInfo is passed, then it also checks if there
309 /// is a read of a super-register.
310 /// This does not count partial redefines of virtual registers as reads:
312 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
313 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
316 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
317 /// virtual register. Take into account that a partial define is a
318 /// read-modify-write operation.
319 bool readsVirtualRegister(unsigned Reg) const {
320 return readsWritesVirtualRegister(Reg).first;
323 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
324 /// indicating if this instruction reads or writes Reg. This also considers
326 /// If Ops is not null, all operand indices for Reg are added.
327 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
328 SmallVectorImpl<unsigned> *Ops = 0) const;
330 /// killsRegister - Return true if the MachineInstr kills the specified
331 /// register. If TargetRegisterInfo is passed, then it also checks if there is
332 /// a kill of a super-register.
333 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
334 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
337 /// definesRegister - Return true if the MachineInstr fully defines the
338 /// specified register. If TargetRegisterInfo is passed, then it also checks
339 /// if there is a def of a super-register.
340 /// NOTE: It's ignoring subreg indices on virtual registers.
341 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
342 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
345 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
346 /// or partially define) the specified register.
347 /// NOTE: It's ignoring subreg indices on virtual registers.
348 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
349 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
352 /// registerDefIsDead - Returns true if the register is dead in this machine
353 /// instruction. If TargetRegisterInfo is passed, then it also checks
354 /// if there is a dead def of a super-register.
355 bool registerDefIsDead(unsigned Reg,
356 const TargetRegisterInfo *TRI = NULL) const {
357 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
360 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
361 /// the specific register or -1 if it is not found. It further tightens
362 /// the search criteria to a use that kills the register if isKill is true.
363 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
364 const TargetRegisterInfo *TRI = NULL) const;
366 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
367 /// a pointer to the MachineOperand rather than an index.
368 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
369 const TargetRegisterInfo *TRI = NULL) {
370 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
371 return (Idx == -1) ? NULL : &getOperand(Idx);
374 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
375 /// the specified register or -1 if it is not found. If isDead is true, defs
376 /// that are not dead are skipped. If Overlap is true, then it also looks for
377 /// defs that merely overlap the specified register. If TargetRegisterInfo is
378 /// non-null, then it also checks if there is a def of a super-register.
379 int findRegisterDefOperandIdx(unsigned Reg,
380 bool isDead = false, bool Overlap = false,
381 const TargetRegisterInfo *TRI = NULL) const;
383 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
384 /// a pointer to the MachineOperand rather than an index.
385 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
386 const TargetRegisterInfo *TRI = NULL) {
387 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
388 return (Idx == -1) ? NULL : &getOperand(Idx);
391 /// findFirstPredOperandIdx() - Find the index of the first operand in the
392 /// operand list that is used to represent the predicate. It returns -1 if
394 int findFirstPredOperandIdx() const;
396 /// isRegTiedToUseOperand - Given the index of a register def operand,
397 /// check if the register def is tied to a source operand, due to either
398 /// two-address elimination or inline assembly constraints. Returns the
399 /// first tied use operand index by reference is UseOpIdx is not null.
400 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
402 /// isRegTiedToDefOperand - Return true if the use operand of the specified
403 /// index is tied to an def operand. It also returns the def operand index by
404 /// reference if DefOpIdx is not null.
405 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
407 /// clearKillInfo - Clears kill flags on all operands.
409 void clearKillInfo();
411 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
413 void copyKillDeadInfo(const MachineInstr *MI);
415 /// copyPredicates - Copies predicate operand(s) from MI.
416 void copyPredicates(const MachineInstr *MI);
418 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
419 /// properly composing subreg indices where necessary.
420 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
421 const TargetRegisterInfo &RegInfo);
423 /// addRegisterKilled - We have determined MI kills a register. Look for the
424 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
425 /// add a implicit operand if it's not found. Returns true if the operand
426 /// exists / is added.
427 bool addRegisterKilled(unsigned IncomingReg,
428 const TargetRegisterInfo *RegInfo,
429 bool AddIfNotFound = false);
431 /// addRegisterDead - We have determined MI defined a register without a use.
432 /// Look for the operand that defines it and mark it as IsDead. If
433 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
434 /// true if the operand exists / is added.
435 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
436 bool AddIfNotFound = false);
438 /// addRegisterDefined - We have determined MI defines a register. Make sure
439 /// there is an operand defining Reg.
440 void addRegisterDefined(unsigned IncomingReg,
441 const TargetRegisterInfo *RegInfo = 0);
443 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
444 /// dead except those in the UsedRegs list.
445 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
446 const TargetRegisterInfo &TRI);
448 /// isSafeToMove - Return true if it is safe to move this instruction. If
449 /// SawStore is set to true, it means that there is a store (or call) between
450 /// the instruction's location and its intended destination.
451 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
452 bool &SawStore) const;
454 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
455 /// instruction which defined the specified register instead of copying it.
456 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
457 unsigned DstReg) const;
459 /// hasVolatileMemoryRef - Return true if this instruction may have a
460 /// volatile memory reference, or if the information describing the
461 /// memory reference is not available. Return false if it is known to
462 /// have no volatile memory references.
463 bool hasVolatileMemoryRef() const;
465 /// isInvariantLoad - Return true if this instruction is loading from a
466 /// location whose value is invariant across the function. For example,
467 /// loading a value from the constant pool or from the argument area of
468 /// a function if it does not change. This should only return true of *all*
469 /// loads the instruction does are invariant (if it does multiple loads).
470 bool isInvariantLoad(AliasAnalysis *AA) const;
472 /// isConstantValuePHI - If the specified instruction is a PHI that always
473 /// merges together the same virtual register, return the register, otherwise
475 unsigned isConstantValuePHI() const;
477 /// hasUnmodeledSideEffects - Return true if this instruction has side
478 /// effects that are not modeled by mayLoad / mayStore, etc.
479 /// For all instructions, the property is encoded in MCInstrDesc::Flags
480 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
481 /// INLINEASM instruction, in which case the side effect property is encoded
482 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
484 bool hasUnmodeledSideEffects() const;
486 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
488 bool allDefsAreDead() const;
490 /// copyImplicitOps - Copy implicit register operands from specified
491 /// instruction to this instruction.
492 void copyImplicitOps(const MachineInstr *MI);
497 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
500 //===--------------------------------------------------------------------===//
501 // Accessors used to build up machine instructions.
503 /// addOperand - Add the specified operand to the instruction. If it is an
504 /// implicit operand, it is added to the end of the operand list. If it is
505 /// an explicit operand it is added at the end of the explicit operand list
506 /// (before the first implicit operand).
507 void addOperand(const MachineOperand &Op);
509 /// setDesc - Replace the instruction descriptor (thus opcode) of
510 /// the current instruction with a new one.
512 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
514 /// setDebugLoc - Replace current source information with new such.
515 /// Avoid using this, the constructor argument is preferable.
517 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
519 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
520 /// fewer operand than it started with.
522 void RemoveOperand(unsigned i);
524 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
525 /// This function should be used only occasionally. The setMemRefs function
526 /// is the primary method for setting up a MachineInstr's MemRefs list.
527 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
529 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
530 /// list. This does not transfer ownership.
531 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
532 MemRefs = NewMemRefs;
533 MemRefsEnd = NewMemRefsEnd;
537 /// getRegInfo - If this instruction is embedded into a MachineFunction,
538 /// return the MachineRegisterInfo object for the current function, otherwise
540 MachineRegisterInfo *getRegInfo();
542 /// addImplicitDefUseOperands - Add all implicit def and use operands to
543 /// this instruction.
544 void addImplicitDefUseOperands();
546 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
547 /// this instruction from their respective use lists. This requires that the
548 /// operands already be on their use lists.
549 void RemoveRegOperandsFromUseLists();
551 /// AddRegOperandsToUseLists - Add all of the register operands in
552 /// this instruction from their respective use lists. This requires that the
553 /// operands not be on their use lists yet.
554 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
557 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
558 /// MachineInstr* by *value* of the instruction rather than by pointer value.
559 /// The hashing and equality testing functions ignore definitions so this is
560 /// useful for CSE, etc.
561 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
562 static inline MachineInstr *getEmptyKey() {
566 static inline MachineInstr *getTombstoneKey() {
567 return reinterpret_cast<MachineInstr*>(-1);
570 static unsigned getHashValue(const MachineInstr* const &MI);
572 static bool isEqual(const MachineInstr* const &LHS,
573 const MachineInstr* const &RHS) {
574 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
575 LHS == getEmptyKey() || LHS == getTombstoneKey())
577 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
581 //===----------------------------------------------------------------------===//
584 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
589 } // End llvm namespace