1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "llvm/Target/MRegisterInfo.h"
14 #include "Support/iterator"
15 #include "Support/NonCopyable.h"
19 class MachineBasicBlock;
23 typedef int MachineOpCode;
25 /// MOTy - MachineOperandType - This namespace contains an enum that describes
26 /// how the machine operand is used by the instruction: is it read, defined, or
27 /// both? Note that the MachineInstr/Operator class currently uses bool
28 /// arguments to represent this information instead of an enum. Eventually this
29 /// should change over to use this _easier to read_ representation instead.
33 Use, /// This machine operand is only read by the instruction
34 Def, /// This machine operand is only written by the instruction
35 UseAndDef /// This machine operand is read AND written
39 //---------------------------------------------------------------------------
40 // class MachineOperand
43 // Representation of each machine instruction operand.
44 // This class is designed so that you can allocate a vector of operands
45 // first and initialize each one later.
47 // E.g, for this VM instruction:
48 // ptr = alloca type, numElements
49 // we generate 2 machine instructions on the SPARC:
51 // mul Constant, Numelements -> Reg
52 // add %sp, Reg -> Ptr
54 // Each instruction has 3 operands, listed above. Of those:
55 // - Reg, NumElements, and Ptr are of operand type MO_Register.
56 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
58 // For the register operands, the virtual register type is as follows:
60 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
61 // MachineInstr* minstr will point to the instruction that computes reg.
63 // - %sp will be of virtual register type MO_MachineReg.
64 // The field regNum identifies the machine register.
66 // - NumElements will be of virtual register type MO_VirtualReg.
67 // The field Value* value identifies the value.
69 // - Ptr will also be of virtual register type MO_VirtualReg.
70 // Again, the field Value* value identifies the value.
72 //---------------------------------------------------------------------------
74 struct MachineOperand {
75 enum MachineOperandType {
76 MO_VirtualRegister, // virtual register for *value
77 MO_MachineRegister, // pre-assigned machine register `regNum'
82 MO_MachineBasicBlock, // MachineBasicBlock reference
83 MO_FrameIndex, // Abstract Stack Frame Index
84 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
85 MO_ExternalSymbol, // Name of external global symbol
86 MO_GlobalAddress, // Address of a global value
90 // Bit fields of the flags variable used for different operand properties
92 DEFFLAG = 0x01, // this is a def of the operand
93 DEFUSEFLAG = 0x02, // this is both a def and a use
94 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
95 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
96 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
97 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
98 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
105 Value* value; // BasicBlockVal for a label operand.
106 // ConstantVal for a non-address immediate.
107 // Virtual register for an SSA operand,
108 // including hidden operands required for
109 // the generated machine code.
110 // LLVM global for MO_GlobalAddress.
112 int64_t immedVal; // Constant value for an explicit constant
114 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
115 std::string *SymbolName; // For MO_ExternalSymbol type
118 char flags; // see bit field definitions above
119 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
120 int regNum; // register number for an explicit register
121 // will be set for a value after reg allocation
126 opType(MO_VirtualRegister),
129 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
135 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
140 case MOTy::Use: flags = 0; break;
141 case MOTy::Def: flags = DEFFLAG; break;
142 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
143 default: assert(0 && "Invalid value for UseTy!");
147 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
148 bool isPCRelative = false)
149 : value(V), opType(OpTy), regNum(-1) {
151 case MOTy::Use: flags = 0; break;
152 case MOTy::Def: flags = DEFFLAG; break;
153 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
154 default: assert(0 && "Invalid value for UseTy!");
156 if (isPCRelative) flags |= PCRELATIVE;
159 MachineOperand(MachineBasicBlock *mbb)
160 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
162 MachineOperand(const std::string &SymName, bool isPCRelative)
163 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
164 opType(MO_ExternalSymbol), regNum(-1) {}
167 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
171 if (isExternalSymbol())
172 SymbolName = new std::string(M.getSymbolName());
176 if (isExternalSymbol())
180 const MachineOperand &operator=(const MachineOperand &MO) {
181 immedVal = MO.immedVal;
185 if (isExternalSymbol())
186 SymbolName = new std::string(MO.getSymbolName());
190 // Accessor methods. Caller is responsible for checking the
191 // operand type before invoking the corresponding accessor.
193 MachineOperandType getType() const { return opType; }
195 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
196 /// indicates whether this operand should be emitted as a PC relative value
197 /// instead of a global address. This is used for operands of the forms:
198 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
200 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
203 // This is to finally stop caring whether we have a virtual or machine
204 // register -- an easier interface is to simply call both virtual and machine
205 // registers essentially the same, yet be able to distinguish when
206 // necessary. Thus the instruction selector can just add registers without
207 // abandon, and the register allocator won't be confused.
208 bool isVirtualRegister() const {
209 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
210 && regNum >= MRegisterInfo::FirstVirtualRegister;
212 bool isPhysicalRegister() const {
213 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
214 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
216 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
217 bool isMachineRegister() const { return !isVirtualRegister(); }
218 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
219 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
220 bool isImmediate() const {
221 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
223 bool isFrameIndex() const { return opType == MO_FrameIndex; }
224 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
225 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
226 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
228 Value* getVRegValue() const {
229 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
233 Value* getVRegValueOrNull() const {
234 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
235 isPCRelativeDisp()) ? value : NULL;
237 int getMachineRegNum() const {
238 assert(opType == MO_MachineRegister);
241 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
242 MachineBasicBlock *getMachineBasicBlock() const {
243 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
246 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
247 unsigned getConstantPoolIndex() const {
248 assert(isConstantPoolIndex());
252 GlobalValue *getGlobal() const {
253 assert(isGlobalAddress());
254 return (GlobalValue*)value;
257 const std::string &getSymbolName() const {
258 assert(isExternalSymbol());
262 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
263 bool opIsDef () const { return flags & DEFFLAG; }
264 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
265 bool opHiBits32 () const { return flags & HIFLAG32; }
266 bool opLoBits32 () const { return flags & LOFLAG32; }
267 bool opHiBits64 () const { return flags & HIFLAG64; }
268 bool opLoBits64 () const { return flags & LOFLAG64; }
270 // used to check if a machine register has been allocated to this operand
271 bool hasAllocatedReg() const {
272 return (regNum >= 0 &&
273 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
274 opType == MO_MachineRegister));
277 // used to get the reg number if when one is allocated
278 int getAllocatedRegNum() const {
279 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
280 opType == MO_MachineRegister);
284 unsigned getReg() const {
285 assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
289 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
293 // Construction methods needed for fine-grain control.
294 // These must be accessed via coresponding methods in MachineInstr.
295 void markHi32() { flags |= HIFLAG32; }
296 void markLo32() { flags |= LOFLAG32; }
297 void markHi64() { flags |= HIFLAG64; }
298 void markLo64() { flags |= LOFLAG64; }
300 // Replaces the Value with its corresponding physical register after
301 // register allocation is complete
302 void setRegForValue(int reg) {
303 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
304 opType == MO_MachineRegister);
308 friend class MachineInstr;
312 //---------------------------------------------------------------------------
313 // class MachineInstr
316 // Representation of each machine instruction.
318 // MachineOpCode must be an enum, defined separately for each target.
319 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
321 // There are 2 kinds of operands:
323 // (1) Explicit operands of the machine instruction in vector operands[]
325 // (2) "Implicit operands" are values implicitly used or defined by the
326 // machine instruction, such as arguments to a CALL, return value of
327 // a CALL (if any), and return value of a RETURN.
328 //---------------------------------------------------------------------------
330 class MachineInstr: public NonCopyable { // Disable copy operations
332 MachineOpCode opCode; // the opcode
333 std::vector<MachineOperand> operands; // the operands
334 unsigned numImplicitRefs; // number of implicit operands
336 MachineOperand& getImplicitOp(unsigned i) {
337 assert(i < numImplicitRefs && "implicit ref# out of range!");
338 return operands[i + operands.size() - numImplicitRefs];
340 const MachineOperand& getImplicitOp(unsigned i) const {
341 assert(i < numImplicitRefs && "implicit ref# out of range!");
342 return operands[i + operands.size() - numImplicitRefs];
345 // regsUsed - all machine registers used for this instruction, including regs
346 // used to save values across the instruction. This is a bitset of registers.
347 std::vector<bool> regsUsed;
349 // OperandComplete - Return true if it's illegal to add a new operand
350 bool OperandsComplete() const;
353 MachineInstr(MachineOpCode Opcode);
354 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
356 /// MachineInstr ctor - This constructor only does a _reserve_ of the
357 /// operands, not a resize for them. It is expected that if you use this that
358 /// you call add* methods below to fill up the operands, instead of the Set
359 /// methods. Eventually, the "resizing" ctors will be phased out.
361 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
363 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
364 /// the MachineInstr is created and added to the end of the specified basic
367 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
372 const MachineOpCode getOpcode() const { return opCode; }
373 const MachineOpCode getOpCode() const { return opCode; }
376 // Information about explicit operands of the instruction
378 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
380 const MachineOperand& getOperand(unsigned i) const {
381 assert(i < getNumOperands() && "getOperand() out of range!");
384 MachineOperand& getOperand(unsigned i) {
385 assert(i < getNumOperands() && "getOperand() out of range!");
390 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
391 return getOperand(i).getType();
394 // FIXME: ELIMINATE: Misleading name: Definition not defined.
395 bool operandIsDefined(unsigned i) const {
396 return getOperand(i).opIsDef();
399 bool operandIsDefinedAndUsed(unsigned i) const {
400 return getOperand(i).opIsDefAndUse();
404 // Information about implicit operands of the instruction
406 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
408 const Value* getImplicitRef(unsigned i) const {
409 return getImplicitOp(i).getVRegValue();
411 Value* getImplicitRef(unsigned i) {
412 return getImplicitOp(i).getVRegValue();
415 bool implicitRefIsDefined(unsigned i) const {
416 return getImplicitOp(i).opIsDef();
418 bool implicitRefIsDefinedAndUsed(unsigned i) const {
419 return getImplicitOp(i).opIsDefAndUse();
421 inline void addImplicitRef (Value* V,
422 bool isDef=false,bool isDefAndUse=false);
423 inline void setImplicitRef (unsigned i, Value* V,
424 bool isDef=false, bool isDefAndUse=false);
427 // Information about registers used in this instruction
429 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
431 // insertUsedReg - Add a register to the Used registers set...
432 void insertUsedReg(unsigned Reg) {
433 if (Reg >= regsUsed.size())
434 regsUsed.resize(Reg+1);
435 regsUsed[Reg] = true;
441 void print(std::ostream &OS, const TargetMachine &TM) const;
443 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
446 // Define iterators to access the Value operands of the Machine Instruction.
447 // Note that these iterators only enumerate the explicit operands.
448 // begin() and end() are defined to produce these iterators...
450 template<class _MI, class _V> class ValOpIterator;
451 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
452 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
455 //===--------------------------------------------------------------------===//
456 // Accessors to add operands when building up machine instructions
459 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
462 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
463 assert(!OperandsComplete() &&
464 "Trying to add an operand to a machine instr that is already done!");
465 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
466 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
469 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
470 bool isPCRelative = false) {
471 assert(!OperandsComplete() &&
472 "Trying to add an operand to a machine instr that is already done!");
473 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
477 /// addRegOperand - Add a symbolic virtual register reference...
479 void addRegOperand(int reg, bool isDef) {
480 assert(!OperandsComplete() &&
481 "Trying to add an operand to a machine instr that is already done!");
482 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
483 isDef ? MOTy::Def : MOTy::Use));
486 /// addRegOperand - Add a symbolic virtual register reference...
488 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
489 assert(!OperandsComplete() &&
490 "Trying to add an operand to a machine instr that is already done!");
491 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
495 /// addPCDispOperand - Add a PC relative displacement operand to the MI
497 void addPCDispOperand(Value *V) {
498 assert(!OperandsComplete() &&
499 "Trying to add an operand to a machine instr that is already done!");
500 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
504 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
506 void addMachineRegOperand(int reg, bool isDef) {
507 assert(!OperandsComplete() &&
508 "Trying to add an operand to a machine instr that is already done!");
509 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
510 isDef ? MOTy::Def : MOTy::Use));
514 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
516 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
517 assert(!OperandsComplete() &&
518 "Trying to add an operand to a machine instr that is already done!");
519 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
524 /// addZeroExtImmOperand - Add a zero extended constant argument to the
525 /// machine instruction.
527 void addZeroExtImmOperand(int64_t intValue) {
528 assert(!OperandsComplete() &&
529 "Trying to add an operand to a machine instr that is already done!");
530 operands.push_back(MachineOperand(intValue,
531 MachineOperand::MO_UnextendedImmed));
534 /// addSignExtImmOperand - Add a zero extended constant argument to the
535 /// machine instruction.
537 void addSignExtImmOperand(int64_t intValue) {
538 assert(!OperandsComplete() &&
539 "Trying to add an operand to a machine instr that is already done!");
540 operands.push_back(MachineOperand(intValue,
541 MachineOperand::MO_SignExtendedImmed));
544 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
545 assert(!OperandsComplete() &&
546 "Trying to add an operand to a machine instr that is already done!");
547 operands.push_back(MachineOperand(MBB));
550 /// addFrameIndexOperand - Add an abstract frame index to the instruction
552 void addFrameIndexOperand(unsigned Idx) {
553 assert(!OperandsComplete() &&
554 "Trying to add an operand to a machine instr that is already done!");
555 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
558 /// addConstantPoolndexOperand - Add a constant pool object index to the
561 void addConstantPoolIndexOperand(unsigned I) {
562 assert(!OperandsComplete() &&
563 "Trying to add an operand to a machine instr that is already done!");
564 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
567 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
568 assert(!OperandsComplete() &&
569 "Trying to add an operand to a machine instr that is already done!");
570 operands.push_back(MachineOperand((Value*)GV,
571 MachineOperand::MO_GlobalAddress,
572 MOTy::Use, isPCRelative));
575 /// addExternalSymbolOperand - Add an external symbol operand to this instr
577 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
578 operands.push_back(MachineOperand(SymName, isPCRelative));
581 //===--------------------------------------------------------------------===//
582 // Accessors used to modify instructions in place.
584 // FIXME: Move this stuff to MachineOperand itself!
586 /// replace - Support to rewrite a machine instruction in place: for now,
587 /// simply replace() and then set new operands with Set.*Operand methods
590 void replace(MachineOpCode Opcode, unsigned numOperands);
592 /// setOpcode - Replace the opcode of the current instruction with a new one.
594 void setOpcode(unsigned Op) { opCode = Op; }
596 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
597 /// fewer operand than it started with.
599 void RemoveOperand(unsigned i) {
600 operands.erase(operands.begin()+i);
603 // Access to set the operands when building the machine instruction
605 void SetMachineOperandVal (unsigned i,
606 MachineOperand::MachineOperandType operandType,
609 bool isDefAndUse=false);
611 void SetMachineOperandConst (unsigned i,
612 MachineOperand::MachineOperandType operandType,
615 void SetMachineOperandReg (unsigned i,
620 unsigned substituteValue(const Value* oldVal, Value* newVal,
621 bool defsOnly = true);
623 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
624 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
625 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
626 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
629 // SetRegForOperand - Replaces the Value for the operand with its allocated
630 // physical register after register allocation is complete.
632 void SetRegForOperand(unsigned i, int regNum);
635 // Iterator to enumerate machine operands.
637 template<class MITy, class VTy>
638 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
642 void skipToNextVal() {
643 while (i < MI->getNumOperands() &&
644 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
645 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
646 && MI->getOperand(i).getVRegValue() != 0))
650 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
655 typedef ValOpIterator<MITy, VTy> _Self;
657 inline VTy operator*() const {
658 return MI->getOperand(i).getVRegValue();
661 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
662 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
664 inline VTy operator->() const { return operator*(); }
666 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
667 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
669 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
670 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
672 inline bool operator==(const _Self &y) const {
675 inline bool operator!=(const _Self &y) const {
676 return !operator==(y);
679 static _Self begin(MITy MI) {
682 static _Self end(MITy MI) {
683 return _Self(MI, MI->getNumOperands());
687 // define begin() and end()
688 val_op_iterator begin() { return val_op_iterator::begin(this); }
689 val_op_iterator end() { return val_op_iterator::end(this); }
691 const_val_op_iterator begin() const {
692 return const_val_op_iterator::begin(this);
694 const_val_op_iterator end() const {
695 return const_val_op_iterator::end(this);
700 // Define here to enable inlining of the functions used.
702 void MachineInstr::addImplicitRef(Value* V,
707 addRegOperand(V, isDef, isDefAndUse);
710 void MachineInstr::setImplicitRef(unsigned i,
715 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
716 SetMachineOperandVal(i + getNumOperands(),
717 MachineOperand::MO_VirtualRegister,
718 V, isDef, isDefAndUse);
722 //---------------------------------------------------------------------------
724 //---------------------------------------------------------------------------
726 std::ostream& operator<< (std::ostream& os,
727 const MachineInstr& minstr);
729 std::ostream& operator<< (std::ostream& os,
730 const MachineOperand& mop);
732 void PrintMachineInstructions (const Function *F);