1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 class MachineFunction;
38 class MachineMemOperand;
40 //===----------------------------------------------------------------------===//
41 /// MachineInstr - Representation of each machine instruction.
43 class MachineInstr : public ilist_node<MachineInstr> {
45 typedef MachineMemOperand **mmo_iterator;
47 /// Flags to specify different kinds of comments to output in
48 /// assembly code. These flags carry semantic information not
49 /// otherwise easily derivable from the IR text.
57 FrameSetup = 1 << 0, // Instruction is used as a part of
58 // function frame setup code.
59 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
60 // the first MI in a bundle)
63 const MCInstrDesc *MCID; // Instruction descriptor.
65 uint8_t Flags; // Various bits of additional
66 // information about machine
69 uint8_t AsmPrinterFlags; // Various bits of information used by
70 // the AsmPrinter to emit helpful
71 // comments. This is *not* semantic
72 // information. Do not use this for
73 // anything other than to convey comment
74 // information to AsmPrinter.
76 std::vector<MachineOperand> Operands; // the operands
77 mmo_iterator MemRefs; // information on memory references
78 mmo_iterator MemRefsEnd;
79 MachineBasicBlock *Parent; // Pointer to the owning basic block.
80 DebugLoc debugLoc; // Source line information.
82 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
83 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
85 // Intrusive list support
86 friend struct ilist_traits<MachineInstr>;
87 friend struct ilist_traits<MachineBasicBlock>;
88 void setParent(MachineBasicBlock *P) { Parent = P; }
90 /// MachineInstr ctor - This constructor creates a copy of the given
91 /// MachineInstr in the given MachineFunction.
92 MachineInstr(MachineFunction &, const MachineInstr &);
94 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
95 /// MCID NULL and no operands.
98 // The next two constructors have DebugLoc and non-DebugLoc versions;
99 // over time, the non-DebugLoc versions should be phased out and eventually
102 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
103 /// implicit operands. It reserves space for the number of operands specified
104 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
105 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
107 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
108 /// the MachineInstr is created and added to the end of the specified basic
109 /// block. The version with a DebugLoc should be preferred.
110 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
112 /// MachineInstr ctor - This constructor create a MachineInstr and add the
113 /// implicit operands. It reserves space for number of operands specified by
114 /// MCInstrDesc. An explicit DebugLoc is supplied.
115 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
118 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
119 /// the MachineInstr is created and added to the end of the specified basic
121 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
122 const MCInstrDesc &MCID);
126 // MachineInstrs are pool-allocated and owned by MachineFunction.
127 friend class MachineFunction;
130 const MachineBasicBlock* getParent() const { return Parent; }
131 MachineBasicBlock* getParent() { return Parent; }
133 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
135 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
137 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
139 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
141 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
143 bool getAsmPrinterFlag(CommentFlag Flag) const {
144 return AsmPrinterFlags & Flag;
147 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
149 void setAsmPrinterFlag(CommentFlag Flag) {
150 AsmPrinterFlags |= (uint8_t)Flag;
153 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
155 void clearAsmPrinterFlag(CommentFlag Flag) {
156 AsmPrinterFlags &= ~Flag;
159 /// getFlags - Return the MI flags bitvector.
160 uint8_t getFlags() const {
164 /// getFlag - Return whether an MI flag is set.
165 bool getFlag(MIFlag Flag) const {
169 /// setFlag - Set a MI flag.
170 void setFlag(MIFlag Flag) {
171 Flags |= (uint8_t)Flag;
174 void setFlags(unsigned flags) {
178 /// clearFlag - Clear a MI flag.
179 void clearFlag(MIFlag Flag) {
180 Flags &= ~((uint8_t)Flag);
183 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
186 /// A bundle looks like this before it's finalized:
198 /// In this case, the first MI starts a bundle but is not inside a bundle, the
199 /// next 2 MIs are considered "inside" the bundle.
201 /// After a bundle is finalized, it looks like this:
217 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
218 /// a bundle, but the next three MIs are.
219 bool isInsideBundle() const {
220 return getFlag(InsideBundle);
223 /// setIsInsideBundle - Set InsideBundle bit.
225 void setIsInsideBundle(bool Val = true) {
227 setFlag(InsideBundle);
229 clearFlag(InsideBundle);
232 /// getDebugLoc - Returns the debug location id of this MachineInstr.
234 DebugLoc getDebugLoc() const { return debugLoc; }
236 /// emitError - Emit an error referring to the source location of this
237 /// instruction. This should only be used for inline assembly that is somehow
238 /// impossible to compile. Other errors should have been handled much
241 /// If this method returns, the caller should try to recover from the error.
243 void emitError(StringRef Msg) const;
245 /// getDesc - Returns the target instruction descriptor of this
247 const MCInstrDesc &getDesc() const { return *MCID; }
249 /// getOpcode - Returns the opcode of this MachineInstr.
251 int getOpcode() const { return MCID->Opcode; }
253 /// Access to explicit operands of the instruction.
255 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
257 const MachineOperand& getOperand(unsigned i) const {
258 assert(i < getNumOperands() && "getOperand() out of range!");
261 MachineOperand& getOperand(unsigned i) {
262 assert(i < getNumOperands() && "getOperand() out of range!");
266 /// getNumExplicitOperands - Returns the number of non-implicit operands.
268 unsigned getNumExplicitOperands() const;
270 /// iterator/begin/end - Iterate over all operands of a machine instruction.
271 typedef std::vector<MachineOperand>::iterator mop_iterator;
272 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
274 mop_iterator operands_begin() { return Operands.begin(); }
275 mop_iterator operands_end() { return Operands.end(); }
277 const_mop_iterator operands_begin() const { return Operands.begin(); }
278 const_mop_iterator operands_end() const { return Operands.end(); }
280 /// Access to memory operands of the instruction
281 mmo_iterator memoperands_begin() const { return MemRefs; }
282 mmo_iterator memoperands_end() const { return MemRefsEnd; }
283 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
285 /// hasOneMemOperand - Return true if this instruction has exactly one
286 /// MachineMemOperand.
287 bool hasOneMemOperand() const {
288 return MemRefsEnd - MemRefs == 1;
291 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
292 /// queries but they are bundle aware.
295 IgnoreBundle, // Ignore bundles
296 AnyInBundle, // Return true if any instruction in bundle has property
297 AllInBundle // Return true if all instructions in bundle have property
300 /// hasProperty - Return true if the instruction (or in the case of a bundle,
301 /// the instructions inside the bundle) has the specified property.
302 /// The first argument is the property being queried.
303 /// The second argument indicates whether the query should look inside
304 /// instruction bundles.
305 /// If the third argument is true, than the query can return true when *any*
306 /// of the bundled instructions has the queried property. If it's false, then
307 /// this can return true iff *all* of the instructions have the property.
308 bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
310 /// isVariadic - Return true if this instruction can have a variable number of
311 /// operands. In this case, the variable operands will be after the normal
312 /// operands but before the implicit definitions and uses (if any are
314 bool isVariadic(QueryType Type = IgnoreBundle) const {
315 return hasProperty(MCID::Variadic, Type);
318 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
319 /// ARM instructions which can set condition code if 's' bit is set.
320 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
321 return hasProperty(MCID::HasOptionalDef, Type);
324 /// isPseudo - Return true if this is a pseudo instruction that doesn't
325 /// correspond to a real machine instruction.
327 bool isPseudo(QueryType Type = IgnoreBundle) const {
328 return hasProperty(MCID::Pseudo, Type);
331 bool isReturn(QueryType Type = AnyInBundle) const {
332 return hasProperty(MCID::Return, Type);
335 bool isCall(QueryType Type = AnyInBundle) const {
336 return hasProperty(MCID::Call, Type);
339 /// isBarrier - Returns true if the specified instruction stops control flow
340 /// from executing the instruction immediately following it. Examples include
341 /// unconditional branches and return instructions.
342 bool isBarrier(QueryType Type = AnyInBundle) const {
343 return hasProperty(MCID::Barrier, Type);
346 /// isTerminator - Returns true if this instruction part of the terminator for
347 /// a basic block. Typically this is things like return and branch
350 /// Various passes use this to insert code into the bottom of a basic block,
351 /// but before control flow occurs.
352 bool isTerminator(QueryType Type = AnyInBundle) const {
353 return hasProperty(MCID::Terminator, Type);
356 /// isBranch - Returns true if this is a conditional, unconditional, or
357 /// indirect branch. Predicates below can be used to discriminate between
358 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
359 /// get more information.
360 bool isBranch(QueryType Type = AnyInBundle) const {
361 return hasProperty(MCID::Branch, Type);
364 /// isIndirectBranch - Return true if this is an indirect branch, such as a
365 /// branch through a register.
366 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
367 return hasProperty(MCID::IndirectBranch, Type);
370 /// isConditionalBranch - Return true if this is a branch which may fall
371 /// through to the next instruction or may transfer control flow to some other
372 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
373 /// information about this branch.
374 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
375 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
378 /// isUnconditionalBranch - Return true if this is a branch which always
379 /// transfers control flow to some other block. The
380 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
381 /// about this branch.
382 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
383 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
386 // isPredicable - Return true if this instruction has a predicate operand that
387 // controls execution. It may be set to 'always', or may be set to other
388 /// values. There are various methods in TargetInstrInfo that can be used to
389 /// control and modify the predicate in this instruction.
390 bool isPredicable(QueryType Type = AllInBundle) const {
391 // If it's a bundle than all bundled instructions must be predicable for this
393 return hasProperty(MCID::Predicable, Type);
396 /// isCompare - Return true if this instruction is a comparison.
397 bool isCompare(QueryType Type = IgnoreBundle) const {
398 return hasProperty(MCID::Compare, Type);
401 /// isMoveImmediate - Return true if this instruction is a move immediate
402 /// (including conditional moves) instruction.
403 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
404 return hasProperty(MCID::MoveImm, Type);
407 /// isBitcast - Return true if this instruction is a bitcast instruction.
409 bool isBitcast(QueryType Type = IgnoreBundle) const {
410 return hasProperty(MCID::Bitcast, Type);
413 /// isNotDuplicable - Return true if this instruction cannot be safely
414 /// duplicated. For example, if the instruction has a unique labels attached
415 /// to it, duplicating it would cause multiple definition errors.
416 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
417 return hasProperty(MCID::NotDuplicable, Type);
420 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
421 /// which must be filled by the code generator.
422 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
423 return hasProperty(MCID::DelaySlot, Type);
426 /// canFoldAsLoad - Return true for instructions that can be folded as
427 /// memory operands in other instructions. The most common use for this
428 /// is instructions that are simple loads from memory that don't modify
429 /// the loaded value in any way, but it can also be used for instructions
430 /// that can be expressed as constant-pool loads, such as V_SETALLONES
431 /// on x86, to allow them to be folded when it is beneficial.
432 /// This should only be set on instructions that return a value in their
433 /// only virtual register definition.
434 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
435 return hasProperty(MCID::FoldableAsLoad, Type);
438 //===--------------------------------------------------------------------===//
439 // Side Effect Analysis
440 //===--------------------------------------------------------------------===//
442 /// mayLoad - Return true if this instruction could possibly read memory.
443 /// Instructions with this flag set are not necessarily simple load
444 /// instructions, they may load a value and modify it, for example.
445 bool mayLoad(QueryType Type = AnyInBundle) const {
446 return hasProperty(MCID::MayLoad, Type);
450 /// mayStore - Return true if this instruction could possibly modify memory.
451 /// Instructions with this flag set are not necessarily simple store
452 /// instructions, they may store a modified value based on their operands, or
453 /// may not actually modify anything, for example.
454 bool mayStore(QueryType Type = AnyInBundle) const {
455 return hasProperty(MCID::MayStore, Type);
458 //===--------------------------------------------------------------------===//
459 // Flags that indicate whether an instruction can be modified by a method.
460 //===--------------------------------------------------------------------===//
462 /// isCommutable - Return true if this may be a 2- or 3-address
463 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
464 /// result if Y and Z are exchanged. If this flag is set, then the
465 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
468 /// Note that this flag may be set on instructions that are only commutable
469 /// sometimes. In these cases, the call to commuteInstruction will fail.
470 /// Also note that some instructions require non-trivial modification to
472 bool isCommutable(QueryType Type = IgnoreBundle) const {
473 return hasProperty(MCID::Commutable, Type);
476 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
477 /// which can be changed into a 3-address instruction if needed. Doing this
478 /// transformation can be profitable in the register allocator, because it
479 /// means that the instruction can use a 2-address form if possible, but
480 /// degrade into a less efficient form if the source and dest register cannot
481 /// be assigned to the same register. For example, this allows the x86
482 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
483 /// is the same speed as the shift but has bigger code size.
485 /// If this returns true, then the target must implement the
486 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
487 /// is allowed to fail if the transformation isn't valid for this specific
488 /// instruction (e.g. shl reg, 4 on x86).
490 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
491 return hasProperty(MCID::ConvertibleTo3Addr, Type);
494 /// usesCustomInsertionHook - Return true if this instruction requires
495 /// custom insertion support when the DAG scheduler is inserting it into a
496 /// machine basic block. If this is true for the instruction, it basically
497 /// means that it is a pseudo instruction used at SelectionDAG time that is
498 /// expanded out into magic code by the target when MachineInstrs are formed.
500 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
501 /// is used to insert this into the MachineBasicBlock.
502 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
503 return hasProperty(MCID::UsesCustomInserter, Type);
506 /// hasPostISelHook - Return true if this instruction requires *adjustment*
507 /// after instruction selection by calling a target hook. For example, this
508 /// can be used to fill in ARM 's' optional operand depending on whether
509 /// the conditional flag register is used.
510 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
511 return hasProperty(MCID::HasPostISelHook, Type);
514 /// isRematerializable - Returns true if this instruction is a candidate for
515 /// remat. This flag is deprecated, please don't use it anymore. If this
516 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
517 /// verify the instruction is really rematable.
518 bool isRematerializable(QueryType Type = AllInBundle) const {
519 // It's only possible to re-mat a bundle if all bundled instructions are
520 // re-materializable.
521 return hasProperty(MCID::Rematerializable, Type);
524 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
525 /// less) than a move instruction. This is useful during certain types of
526 /// optimizations (e.g., remat during two-address conversion or machine licm)
527 /// where we would like to remat or hoist the instruction, but not if it costs
528 /// more than moving the instruction into the appropriate register. Note, we
529 /// are not marking copies from and to the same register class with this flag.
530 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
531 // Only returns true for a bundle if all bundled instructions are cheap.
532 // FIXME: This probably requires a target hook.
533 return hasProperty(MCID::CheapAsAMove, Type);
536 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
537 /// have special register allocation requirements that are not captured by the
538 /// operand register classes. e.g. ARM::STRD's two source registers must be an
539 /// even / odd pair, ARM::STM registers have to be in ascending order.
540 /// Post-register allocation passes should not attempt to change allocations
541 /// for sources of instructions with this flag.
542 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
543 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
546 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
547 /// have special register allocation requirements that are not captured by the
548 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
549 /// even / odd pair, ARM::LDM registers have to be in ascending order.
550 /// Post-register allocation passes should not attempt to change allocations
551 /// for definitions of instructions with this flag.
552 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
553 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
558 CheckDefs, // Check all operands for equality
559 CheckKillDead, // Check all operands including kill / dead markers
560 IgnoreDefs, // Ignore all definitions
561 IgnoreVRegDefs // Ignore virtual register definitions
564 /// isIdenticalTo - Return true if this instruction is identical to (same
565 /// opcode and same operands as) the specified instruction.
566 bool isIdenticalTo(const MachineInstr *Other,
567 MICheckType Check = CheckDefs) const;
569 /// removeFromParent - This method unlinks 'this' from the containing basic
570 /// block, and returns it, but does not delete it.
571 MachineInstr *removeFromParent();
573 /// eraseFromParent - This method unlinks 'this' from the containing basic
574 /// block and deletes it.
575 void eraseFromParent();
577 /// isLabel - Returns true if the MachineInstr represents a label.
579 bool isLabel() const {
580 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
581 getOpcode() == TargetOpcode::EH_LABEL ||
582 getOpcode() == TargetOpcode::GC_LABEL;
585 bool isPrologLabel() const {
586 return getOpcode() == TargetOpcode::PROLOG_LABEL;
588 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
589 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
590 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
592 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
593 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
594 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
595 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
596 bool isStackAligningInlineAsm() const;
597 bool isInsertSubreg() const {
598 return getOpcode() == TargetOpcode::INSERT_SUBREG;
600 bool isSubregToReg() const {
601 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
603 bool isRegSequence() const {
604 return getOpcode() == TargetOpcode::REG_SEQUENCE;
606 bool isBundle() const {
607 return getOpcode() == TargetOpcode::BUNDLE;
609 bool isCopy() const {
610 return getOpcode() == TargetOpcode::COPY;
612 bool isFullCopy() const {
613 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
616 /// isCopyLike - Return true if the instruction behaves like a copy.
617 /// This does not include native copy instructions.
618 bool isCopyLike() const {
619 return isCopy() || isSubregToReg();
622 /// isIdentityCopy - Return true is the instruction is an identity copy.
623 bool isIdentityCopy() const {
624 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
625 getOperand(0).getSubReg() == getOperand(1).getSubReg();
628 /// getBundleSize - Return the number of instructions inside the MI bundle.
629 unsigned getBundleSize() const;
631 /// readsRegister - Return true if the MachineInstr reads the specified
632 /// register. If TargetRegisterInfo is passed, then it also checks if there
633 /// is a read of a super-register.
634 /// This does not count partial redefines of virtual registers as reads:
636 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
637 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
640 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
641 /// virtual register. Take into account that a partial define is a
642 /// read-modify-write operation.
643 bool readsVirtualRegister(unsigned Reg) const {
644 return readsWritesVirtualRegister(Reg).first;
647 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
648 /// indicating if this instruction reads or writes Reg. This also considers
650 /// If Ops is not null, all operand indices for Reg are added.
651 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
652 SmallVectorImpl<unsigned> *Ops = 0) const;
654 /// killsRegister - Return true if the MachineInstr kills the specified
655 /// register. If TargetRegisterInfo is passed, then it also checks if there is
656 /// a kill of a super-register.
657 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
658 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
661 /// definesRegister - Return true if the MachineInstr fully defines the
662 /// specified register. If TargetRegisterInfo is passed, then it also checks
663 /// if there is a def of a super-register.
664 /// NOTE: It's ignoring subreg indices on virtual registers.
665 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
666 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
669 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
670 /// or partially define) the specified register.
671 /// NOTE: It's ignoring subreg indices on virtual registers.
672 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
673 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
676 /// registerDefIsDead - Returns true if the register is dead in this machine
677 /// instruction. If TargetRegisterInfo is passed, then it also checks
678 /// if there is a dead def of a super-register.
679 bool registerDefIsDead(unsigned Reg,
680 const TargetRegisterInfo *TRI = NULL) const {
681 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
684 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
685 /// the specific register or -1 if it is not found. It further tightens
686 /// the search criteria to a use that kills the register if isKill is true.
687 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
688 const TargetRegisterInfo *TRI = NULL) const;
690 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
691 /// a pointer to the MachineOperand rather than an index.
692 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
693 const TargetRegisterInfo *TRI = NULL) {
694 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
695 return (Idx == -1) ? NULL : &getOperand(Idx);
698 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
699 /// the specified register or -1 if it is not found. If isDead is true, defs
700 /// that are not dead are skipped. If Overlap is true, then it also looks for
701 /// defs that merely overlap the specified register. If TargetRegisterInfo is
702 /// non-null, then it also checks if there is a def of a super-register.
703 int findRegisterDefOperandIdx(unsigned Reg,
704 bool isDead = false, bool Overlap = false,
705 const TargetRegisterInfo *TRI = NULL) const;
707 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
708 /// a pointer to the MachineOperand rather than an index.
709 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
710 const TargetRegisterInfo *TRI = NULL) {
711 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
712 return (Idx == -1) ? NULL : &getOperand(Idx);
715 /// findFirstPredOperandIdx() - Find the index of the first operand in the
716 /// operand list that is used to represent the predicate. It returns -1 if
718 int findFirstPredOperandIdx() const;
720 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
721 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
722 /// getOperand(OpIdx) does not belong to an inline asm operand group.
724 /// If GroupNo is not NULL, it will receive the number of the operand group
725 /// containing OpIdx.
727 /// The flag operand is an immediate that can be decoded with methods like
728 /// InlineAsm::hasRegClassConstraint().
730 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
732 /// getRegClassConstraint - Compute the static register class constraint for
733 /// operand OpIdx. For normal instructions, this is derived from the
734 /// MCInstrDesc. For inline assembly it is derived from the flag words.
736 /// Returns NULL if the static register classs constraint cannot be
739 const TargetRegisterClass*
740 getRegClassConstraint(unsigned OpIdx,
741 const TargetInstrInfo *TII,
742 const TargetRegisterInfo *TRI) const;
744 /// isRegTiedToUseOperand - Given the index of a register def operand,
745 /// check if the register def is tied to a source operand, due to either
746 /// two-address elimination or inline assembly constraints. Returns the
747 /// first tied use operand index by reference is UseOpIdx is not null.
748 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
750 /// isRegTiedToDefOperand - Return true if the use operand of the specified
751 /// index is tied to an def operand. It also returns the def operand index by
752 /// reference if DefOpIdx is not null.
753 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
755 /// clearKillInfo - Clears kill flags on all operands.
757 void clearKillInfo();
759 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
761 void copyKillDeadInfo(const MachineInstr *MI);
763 /// copyPredicates - Copies predicate operand(s) from MI.
764 void copyPredicates(const MachineInstr *MI);
766 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
767 /// properly composing subreg indices where necessary.
768 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
769 const TargetRegisterInfo &RegInfo);
771 /// addRegisterKilled - We have determined MI kills a register. Look for the
772 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
773 /// add a implicit operand if it's not found. Returns true if the operand
774 /// exists / is added.
775 bool addRegisterKilled(unsigned IncomingReg,
776 const TargetRegisterInfo *RegInfo,
777 bool AddIfNotFound = false);
779 /// addRegisterDead - We have determined MI defined a register without a use.
780 /// Look for the operand that defines it and mark it as IsDead. If
781 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
782 /// true if the operand exists / is added.
783 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
784 bool AddIfNotFound = false);
786 /// addRegisterDefined - We have determined MI defines a register. Make sure
787 /// there is an operand defining Reg.
788 void addRegisterDefined(unsigned IncomingReg,
789 const TargetRegisterInfo *RegInfo = 0);
791 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
792 /// dead except those in the UsedRegs list.
793 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
794 const TargetRegisterInfo &TRI);
796 /// isSafeToMove - Return true if it is safe to move this instruction. If
797 /// SawStore is set to true, it means that there is a store (or call) between
798 /// the instruction's location and its intended destination.
799 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
800 bool &SawStore) const;
802 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
803 /// instruction which defined the specified register instead of copying it.
804 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
805 unsigned DstReg) const;
807 /// hasVolatileMemoryRef - Return true if this instruction may have a
808 /// volatile memory reference, or if the information describing the
809 /// memory reference is not available. Return false if it is known to
810 /// have no volatile memory references.
811 bool hasVolatileMemoryRef() const;
813 /// isInvariantLoad - Return true if this instruction is loading from a
814 /// location whose value is invariant across the function. For example,
815 /// loading a value from the constant pool or from the argument area of
816 /// a function if it does not change. This should only return true of *all*
817 /// loads the instruction does are invariant (if it does multiple loads).
818 bool isInvariantLoad(AliasAnalysis *AA) const;
820 /// isConstantValuePHI - If the specified instruction is a PHI that always
821 /// merges together the same virtual register, return the register, otherwise
823 unsigned isConstantValuePHI() const;
825 /// hasUnmodeledSideEffects - Return true if this instruction has side
826 /// effects that are not modeled by mayLoad / mayStore, etc.
827 /// For all instructions, the property is encoded in MCInstrDesc::Flags
828 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
829 /// INLINEASM instruction, in which case the side effect property is encoded
830 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
832 bool hasUnmodeledSideEffects() const;
834 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
836 bool allDefsAreDead() const;
838 /// copyImplicitOps - Copy implicit register operands from specified
839 /// instruction to this instruction.
840 void copyImplicitOps(const MachineInstr *MI);
845 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
848 //===--------------------------------------------------------------------===//
849 // Accessors used to build up machine instructions.
851 /// addOperand - Add the specified operand to the instruction. If it is an
852 /// implicit operand, it is added to the end of the operand list. If it is
853 /// an explicit operand it is added at the end of the explicit operand list
854 /// (before the first implicit operand).
855 void addOperand(const MachineOperand &Op);
857 /// setDesc - Replace the instruction descriptor (thus opcode) of
858 /// the current instruction with a new one.
860 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
862 /// setDebugLoc - Replace current source information with new such.
863 /// Avoid using this, the constructor argument is preferable.
865 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
867 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
868 /// fewer operand than it started with.
870 void RemoveOperand(unsigned i);
872 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
873 /// This function should be used only occasionally. The setMemRefs function
874 /// is the primary method for setting up a MachineInstr's MemRefs list.
875 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
877 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
878 /// list. This does not transfer ownership.
879 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
880 MemRefs = NewMemRefs;
881 MemRefsEnd = NewMemRefsEnd;
885 /// getRegInfo - If this instruction is embedded into a MachineFunction,
886 /// return the MachineRegisterInfo object for the current function, otherwise
888 MachineRegisterInfo *getRegInfo();
890 /// addImplicitDefUseOperands - Add all implicit def and use operands to
891 /// this instruction.
892 void addImplicitDefUseOperands();
894 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
895 /// this instruction from their respective use lists. This requires that the
896 /// operands already be on their use lists.
897 void RemoveRegOperandsFromUseLists();
899 /// AddRegOperandsToUseLists - Add all of the register operands in
900 /// this instruction from their respective use lists. This requires that the
901 /// operands not be on their use lists yet.
902 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
905 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
906 /// MachineInstr* by *value* of the instruction rather than by pointer value.
907 /// The hashing and equality testing functions ignore definitions so this is
908 /// useful for CSE, etc.
909 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
910 static inline MachineInstr *getEmptyKey() {
914 static inline MachineInstr *getTombstoneKey() {
915 return reinterpret_cast<MachineInstr*>(-1);
918 static unsigned getHashValue(const MachineInstr* const &MI);
920 static bool isEqual(const MachineInstr* const &LHS,
921 const MachineInstr* const &RHS) {
922 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
923 LHS == getEmptyKey() || LHS == getTombstoneKey())
925 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
929 //===----------------------------------------------------------------------===//
932 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
937 } // End llvm namespace