1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
18 class MachineBasicBlock;
21 typedef int MachineOpCode;
23 //---------------------------------------------------------------------------
24 // class MachineOperand
27 // Representation of each machine instruction operand.
28 // This class is designed so that you can allocate a vector of operands
29 // first and initialize each one later.
31 // E.g, for this VM instruction:
32 // ptr = alloca type, numElements
33 // we generate 2 machine instructions on the SPARC:
35 // mul Constant, Numelements -> Reg
36 // add %sp, Reg -> Ptr
38 // Each instruction has 3 operands, listed above. Of those:
39 // - Reg, NumElements, and Ptr are of operand type MO_Register.
40 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
42 // For the register operands, the virtual register type is as follows:
44 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
45 // MachineInstr* minstr will point to the instruction that computes reg.
47 // - %sp will be of virtual register type MO_MachineReg.
48 // The field regNum identifies the machine register.
50 // - NumElements will be of virtual register type MO_VirtualReg.
51 // The field Value* value identifies the value.
53 // - Ptr will also be of virtual register type MO_VirtualReg.
54 // Again, the field Value* value identifies the value.
56 //---------------------------------------------------------------------------
58 class MachineOperand {
60 enum MachineOperandType {
61 MO_VirtualRegister, // virtual register for *value
62 MO_MachineRegister, // pre-assigned machine register `regNum'
70 // Bit fields of the flags variable used for different operand properties
71 static const char DEFFLAG = 0x1; // this is a def of the operand
72 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
73 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
74 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
75 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
76 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
80 Value* value; // BasicBlockVal for a label operand.
81 // ConstantVal for a non-address immediate.
82 // Virtual register for an SSA operand,
83 // including hidden operands required for
84 // the generated machine code.
85 int64_t immedVal; // constant value for an explicit constant
88 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
89 char flags; // see bit field definitions above
90 int regNum; // register number for an explicit register
91 // will be set for a value after reg allocation
95 opType(MO_VirtualRegister),
99 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
105 MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
108 flags(isDef ? DEFFLAG : 0),
111 MachineOperand(Value *V, MachineOperandType OpTy,
112 bool isDef = false, bool isDNU = false)
116 flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
120 MachineOperand(const MachineOperand &M)
121 : immedVal(M.immedVal),
128 // Accessor methods. Caller is responsible for checking the
129 // operand type before invoking the corresponding accessor.
131 MachineOperandType getType() const { return opType; }
133 inline Value* getVRegValue () const {
134 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
135 opType == MO_PCRelativeDisp);
138 inline Value* getVRegValueOrNull() const {
139 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
140 opType == MO_PCRelativeDisp)? value : NULL;
142 inline int getMachineRegNum() const {
143 assert(opType == MO_MachineRegister);
146 inline int64_t getImmedValue () const {
147 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
150 bool opIsDef () const { return flags & DEFFLAG; }
151 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
152 bool opHiBits32 () const { return flags & HIFLAG32; }
153 bool opLoBits32 () const { return flags & LOFLAG32; }
154 bool opHiBits64 () const { return flags & HIFLAG64; }
155 bool opLoBits64 () const { return flags & LOFLAG64; }
157 // used to check if a machine register has been allocated to this operand
158 inline bool hasAllocatedReg() const {
159 return (regNum >= 0 &&
160 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
161 opType == MO_MachineRegister));
164 // used to get the reg number if when one is allocated
165 inline int getAllocatedRegNum() const {
166 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
167 opType == MO_MachineRegister);
172 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
176 // Construction methods needed for fine-grain control.
177 // These must be accessed via coresponding methods in MachineInstr.
178 void markDef() { flags |= DEFFLAG; }
179 void markDefAndUse() { flags |= DEFUSEFLAG; }
180 void markHi32() { flags |= HIFLAG32; }
181 void markLo32() { flags |= LOFLAG32; }
182 void markHi64() { flags |= HIFLAG64; }
183 void markLo64() { flags |= LOFLAG64; }
185 // Replaces the Value with its corresponding physical register after
186 // register allocation is complete
187 void setRegForValue(int reg) {
188 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
189 opType == MO_MachineRegister);
193 friend class MachineInstr;
197 //---------------------------------------------------------------------------
198 // class MachineInstr
201 // Representation of each machine instruction.
203 // MachineOpCode must be an enum, defined separately for each target.
204 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
206 // There are 2 kinds of operands:
208 // (1) Explicit operands of the machine instruction in vector operands[]
210 // (2) "Implicit operands" are values implicitly used or defined by the
211 // machine instruction, such as arguments to a CALL, return value of
212 // a CALL (if any), and return value of a RETURN.
213 //---------------------------------------------------------------------------
215 class MachineInstr: public NonCopyable { // Disable copy operations
217 MachineOpCode opCode; // the opcode
218 std::vector<MachineOperand> operands; // the operands
219 unsigned numImplicitRefs; // number of implicit operands
221 MachineOperand& getImplicitOp(unsigned i) {
222 assert(i < numImplicitRefs && "implicit ref# out of range!");
223 return operands[i + operands.size() - numImplicitRefs];
225 const MachineOperand& getImplicitOp(unsigned i) const {
226 assert(i < numImplicitRefs && "implicit ref# out of range!");
227 return operands[i + operands.size() - numImplicitRefs];
230 // regsUsed - all machine registers used for this instruction, including regs
231 // used to save values across the instruction. This is a bitset of registers.
232 std::vector<bool> regsUsed;
234 // OperandComplete - Return true if it's illegal to add a new operand
235 bool OperandsComplete() const;
238 MachineInstr(MachineOpCode Opcode);
239 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
241 /// MachineInstr ctor - This constructor only does a _reserve_ of the
242 /// operands, not a resize for them. It is expected that if you use this that
243 /// you call add* methods below to fill up the operands, instead of the Set
244 /// methods. Eventually, the "resizing" ctors will be phased out.
246 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
248 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
249 /// the MachineInstr is created and added to the end of the specified basic
252 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
255 /// replace - Support to rewrite a machine instruction in place: for now,
256 /// simply replace() and then set new operands with Set.*Operand methods
259 void replace(MachineOpCode Opcode, unsigned numOperands);
263 const MachineOpCode getOpcode() const { return opCode; }
264 const MachineOpCode getOpCode() const { return opCode; }
267 // Information about explicit operands of the instruction
269 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
271 const MachineOperand& getOperand(unsigned i) const {
272 assert(i < getNumOperands() && "getOperand() out of range!");
275 MachineOperand& getOperand(unsigned i) {
276 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
281 return getOperand(i).getType();
284 bool operandIsDefined(unsigned i) const {
285 return getOperand(i).opIsDef();
288 bool operandIsDefinedAndUsed(unsigned i) const {
289 return getOperand(i).opIsDefAndUse();
293 // Information about implicit operands of the instruction
295 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
297 const Value* getImplicitRef(unsigned i) const {
298 return getImplicitOp(i).getVRegValue();
300 Value* getImplicitRef(unsigned i) {
301 return getImplicitOp(i).getVRegValue();
304 bool implicitRefIsDefined(unsigned i) const {
305 return getImplicitOp(i).opIsDef();
307 bool implicitRefIsDefinedAndUsed(unsigned i) const {
308 return getImplicitOp(i).opIsDefAndUse();
310 inline void addImplicitRef (Value* V,
311 bool isDef=false,bool isDefAndUse=false);
312 inline void setImplicitRef (unsigned i, Value* V,
313 bool isDef=false, bool isDefAndUse=false);
316 // Information about registers used in this instruction
318 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
320 // insertUsedReg - Add a register to the Used registers set...
321 void insertUsedReg(unsigned Reg) {
322 if (Reg >= regsUsed.size())
323 regsUsed.resize(Reg+1);
324 regsUsed[Reg] = true;
330 void print(std::ostream &OS, const TargetMachine &TM);
332 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
335 // Define iterators to access the Value operands of the Machine Instruction.
336 // Note that these iterators only enumerate the explicit operands.
337 // begin() and end() are defined to produce these iterators...
339 template<class _MI, class _V> class ValOpIterator;
340 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
341 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
343 // Access to set the operands when building the machine instruction
345 void SetMachineOperandVal (unsigned i,
346 MachineOperand::MachineOperandType operandType,
349 bool isDefAndUse=false);
351 void SetMachineOperandConst (unsigned i,
352 MachineOperand::MachineOperandType operandType,
355 void SetMachineOperandReg (unsigned i,
359 //===--------------------------------------------------------------------===//
360 // Accessors to add operands when building up machine instructions
363 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
366 void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
367 assert(!OperandsComplete() &&
368 "Trying to add an operand to a machine instr that is already done!");
369 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
370 isDef, isDefAndUse));
373 /// addRegOperand - Add a symbolic virtual register reference...
375 void addRegOperand(int reg, bool isDef = false) {
376 assert(!OperandsComplete() &&
377 "Trying to add an operand to a machine instr that is already done!");
378 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
382 /// addPCDispOperand - Add a PC relative displacement operand to the MI
384 void addPCDispOperand(Value *V) {
385 assert(!OperandsComplete() &&
386 "Trying to add an operand to a machine instr that is already done!");
387 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
390 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
392 void addMachineRegOperand(int reg, bool isDef=false) {
393 assert(!OperandsComplete() &&
394 "Trying to add an operand to a machine instr that is already done!");
395 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
400 /// addZeroExtImmOperand - Add a zero extended constant argument to the
401 /// machine instruction.
403 void addZeroExtImmOperand(int64_t intValue) {
404 assert(!OperandsComplete() &&
405 "Trying to add an operand to a machine instr that is already done!");
406 operands.push_back(MachineOperand(intValue,
407 MachineOperand::MO_UnextendedImmed));
410 /// addSignExtImmOperand - Add a zero extended constant argument to the
411 /// machine instruction.
413 void addSignExtImmOperand(int64_t intValue) {
414 assert(!OperandsComplete() &&
415 "Trying to add an operand to a machine instr that is already done!");
416 operands.push_back(MachineOperand(intValue,
417 MachineOperand::MO_SignExtendedImmed));
421 unsigned substituteValue(const Value* oldVal, Value* newVal,
422 bool defsOnly = true);
424 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
425 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
426 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
427 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
430 // SetRegForOperand - Replaces the Value for the operand with its allocated
431 // physical register after register allocation is complete.
433 void SetRegForOperand(unsigned i, int regNum);
436 // Iterator to enumerate machine operands.
438 template<class MITy, class VTy>
439 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
443 void skipToNextVal() {
444 while (i < MI->getNumOperands() &&
445 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
446 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
447 && MI->getOperand(i).getVRegValue() != 0))
451 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
456 typedef ValOpIterator<MITy, VTy> _Self;
458 inline VTy operator*() const {
459 return MI->getOperand(i).getVRegValue();
462 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
463 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
465 inline VTy operator->() const { return operator*(); }
467 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
468 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
470 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
471 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
473 inline bool operator==(const _Self &y) const {
476 inline bool operator!=(const _Self &y) const {
477 return !operator==(y);
480 static _Self begin(MITy MI) {
483 static _Self end(MITy MI) {
484 return _Self(MI, MI->getNumOperands());
488 // define begin() and end()
489 val_op_iterator begin() { return val_op_iterator::begin(this); }
490 val_op_iterator end() { return val_op_iterator::end(this); }
492 const_val_op_iterator begin() const {
493 return const_val_op_iterator::begin(this);
495 const_val_op_iterator end() const {
496 return const_val_op_iterator::end(this);
501 // Define here to enable inlining of the functions used.
503 void MachineInstr::addImplicitRef(Value* V,
508 addRegOperand(V, isDef, isDefAndUse);
511 void MachineInstr::setImplicitRef(unsigned i,
516 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
517 SetMachineOperandVal(i + getNumImplicitRefs(),
518 MachineOperand::MO_VirtualRegister,
519 V, isDef, isDefAndUse);
523 //---------------------------------------------------------------------------
525 //---------------------------------------------------------------------------
527 std::ostream& operator<< (std::ostream& os,
528 const MachineInstr& minstr);
530 std::ostream& operator<< (std::ostream& os,
531 const MachineOperand& mop);
533 void PrintMachineInstructions (const Function *F);