1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
56 FrameSetup = 1 << 0 // Instruction is used as a part of
57 // function frame setup code.
60 const MCInstrDesc *MCID; // Instruction descriptor.
62 uint8_t Flags; // Various bits of additional
63 // information about machine
66 uint8_t AsmPrinterFlags; // Various bits of information used by
67 // the AsmPrinter to emit helpful
68 // comments. This is *not* semantic
69 // information. Do not use this for
70 // anything other than to convey comment
71 // information to AsmPrinter.
73 std::vector<MachineOperand> Operands; // the operands
74 mmo_iterator MemRefs; // information on memory references
75 mmo_iterator MemRefsEnd;
76 MachineBasicBlock *Parent; // Pointer to the owning basic block.
77 DebugLoc debugLoc; // Source line information.
79 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
80 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
82 // Intrusive list support
83 friend struct ilist_traits<MachineInstr>;
84 friend struct ilist_traits<MachineBasicBlock>;
85 void setParent(MachineBasicBlock *P) { Parent = P; }
87 /// MachineInstr ctor - This constructor creates a copy of the given
88 /// MachineInstr in the given MachineFunction.
89 MachineInstr(MachineFunction &, const MachineInstr &);
91 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
92 /// MCID NULL and no operands.
95 // The next two constructors have DebugLoc and non-DebugLoc versions;
96 // over time, the non-DebugLoc versions should be phased out and eventually
99 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
100 /// implicit operands. It reserves space for the number of operands specified
101 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
102 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
104 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
105 /// the MachineInstr is created and added to the end of the specified basic
106 /// block. The version with a DebugLoc should be preferred.
107 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
109 /// MachineInstr ctor - This constructor create a MachineInstr and add the
110 /// implicit operands. It reserves space for number of operands specified by
111 /// MCInstrDesc. An explicit DebugLoc is supplied.
112 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
115 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
116 /// the MachineInstr is created and added to the end of the specified basic
118 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
119 const MCInstrDesc &MCID);
123 // MachineInstrs are pool-allocated and owned by MachineFunction.
124 friend class MachineFunction;
127 const MachineBasicBlock* getParent() const { return Parent; }
128 MachineBasicBlock* getParent() { return Parent; }
130 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
132 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
134 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
136 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
138 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
140 bool getAsmPrinterFlag(CommentFlag Flag) const {
141 return AsmPrinterFlags & Flag;
144 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
146 void setAsmPrinterFlag(CommentFlag Flag) {
147 AsmPrinterFlags |= (uint8_t)Flag;
150 /// getFlags - Return the MI flags bitvector.
151 uint8_t getFlags() const {
155 /// getFlag - Return whether an MI flag is set.
156 bool getFlag(MIFlag Flag) const {
160 /// setFlag - Set a MI flag.
161 void setFlag(MIFlag Flag) {
162 Flags |= (uint8_t)Flag;
165 void setFlags(unsigned flags) {
169 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
171 void clearAsmPrinterFlag(CommentFlag Flag) {
172 AsmPrinterFlags &= ~Flag;
175 /// getDebugLoc - Returns the debug location id of this MachineInstr.
177 DebugLoc getDebugLoc() const { return debugLoc; }
179 /// emitError - Emit an error referring to the source location of this
180 /// instruction. This should only be used for inline assembly that is somehow
181 /// impossible to compile. Other errors should have been handled much
184 /// If this method returns, the caller should try to recover from the error.
186 void emitError(StringRef Msg) const;
188 /// getDesc - Returns the target instruction descriptor of this
190 const MCInstrDesc &getDesc() const { return *MCID; }
192 /// getOpcode - Returns the opcode of this MachineInstr.
194 int getOpcode() const { return MCID->Opcode; }
196 /// Access to explicit operands of the instruction.
198 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
200 const MachineOperand& getOperand(unsigned i) const {
201 assert(i < getNumOperands() && "getOperand() out of range!");
204 MachineOperand& getOperand(unsigned i) {
205 assert(i < getNumOperands() && "getOperand() out of range!");
209 /// getNumExplicitOperands - Returns the number of non-implicit operands.
211 unsigned getNumExplicitOperands() const;
213 /// iterator/begin/end - Iterate over all operands of a machine instruction.
214 typedef std::vector<MachineOperand>::iterator mop_iterator;
215 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
217 mop_iterator operands_begin() { return Operands.begin(); }
218 mop_iterator operands_end() { return Operands.end(); }
220 const_mop_iterator operands_begin() const { return Operands.begin(); }
221 const_mop_iterator operands_end() const { return Operands.end(); }
223 /// Access to memory operands of the instruction
224 mmo_iterator memoperands_begin() const { return MemRefs; }
225 mmo_iterator memoperands_end() const { return MemRefsEnd; }
226 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
228 /// hasOneMemOperand - Return true if this instruction has exactly one
229 /// MachineMemOperand.
230 bool hasOneMemOperand() const {
231 return MemRefsEnd - MemRefs == 1;
235 CheckDefs, // Check all operands for equality
236 CheckKillDead, // Check all operands including kill / dead markers
237 IgnoreDefs, // Ignore all definitions
238 IgnoreVRegDefs // Ignore virtual register definitions
241 /// isIdenticalTo - Return true if this instruction is identical to (same
242 /// opcode and same operands as) the specified instruction.
243 bool isIdenticalTo(const MachineInstr *Other,
244 MICheckType Check = CheckDefs) const;
246 /// removeFromParent - This method unlinks 'this' from the containing basic
247 /// block, and returns it, but does not delete it.
248 MachineInstr *removeFromParent();
250 /// eraseFromParent - This method unlinks 'this' from the containing basic
251 /// block and deletes it.
252 void eraseFromParent();
254 /// isLabel - Returns true if the MachineInstr represents a label.
256 bool isLabel() const {
257 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
258 getOpcode() == TargetOpcode::EH_LABEL ||
259 getOpcode() == TargetOpcode::GC_LABEL;
262 bool isPrologLabel() const {
263 return getOpcode() == TargetOpcode::PROLOG_LABEL;
265 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
266 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
267 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
269 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
270 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
271 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
272 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
273 bool isStackAligningInlineAsm() const;
274 bool isInsertSubreg() const {
275 return getOpcode() == TargetOpcode::INSERT_SUBREG;
277 bool isSubregToReg() const {
278 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
280 bool isRegSequence() const {
281 return getOpcode() == TargetOpcode::REG_SEQUENCE;
283 bool isCopy() const {
284 return getOpcode() == TargetOpcode::COPY;
286 bool isFullCopy() const {
287 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
290 /// isCopyLike - Return true if the instruction behaves like a copy.
291 /// This does not include native copy instructions.
292 bool isCopyLike() const {
293 return isCopy() || isSubregToReg();
296 /// isIdentityCopy - Return true is the instruction is an identity copy.
297 bool isIdentityCopy() const {
298 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
299 getOperand(0).getSubReg() == getOperand(1).getSubReg();
302 /// readsRegister - Return true if the MachineInstr reads the specified
303 /// register. If TargetRegisterInfo is passed, then it also checks if there
304 /// is a read of a super-register.
305 /// This does not count partial redefines of virtual registers as reads:
307 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
308 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
311 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
312 /// virtual register. Take into account that a partial define is a
313 /// read-modify-write operation.
314 bool readsVirtualRegister(unsigned Reg) const {
315 return readsWritesVirtualRegister(Reg).first;
318 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
319 /// indicating if this instruction reads or writes Reg. This also considers
321 /// If Ops is not null, all operand indices for Reg are added.
322 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
323 SmallVectorImpl<unsigned> *Ops = 0) const;
325 /// killsRegister - Return true if the MachineInstr kills the specified
326 /// register. If TargetRegisterInfo is passed, then it also checks if there is
327 /// a kill of a super-register.
328 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
329 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
332 /// definesRegister - Return true if the MachineInstr fully defines the
333 /// specified register. If TargetRegisterInfo is passed, then it also checks
334 /// if there is a def of a super-register.
335 /// NOTE: It's ignoring subreg indices on virtual registers.
336 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
337 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
340 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
341 /// or partially define) the specified register.
342 /// NOTE: It's ignoring subreg indices on virtual registers.
343 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
344 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
347 /// registerDefIsDead - Returns true if the register is dead in this machine
348 /// instruction. If TargetRegisterInfo is passed, then it also checks
349 /// if there is a dead def of a super-register.
350 bool registerDefIsDead(unsigned Reg,
351 const TargetRegisterInfo *TRI = NULL) const {
352 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
355 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
356 /// the specific register or -1 if it is not found. It further tightens
357 /// the search criteria to a use that kills the register if isKill is true.
358 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
359 const TargetRegisterInfo *TRI = NULL) const;
361 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
362 /// a pointer to the MachineOperand rather than an index.
363 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
364 const TargetRegisterInfo *TRI = NULL) {
365 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
366 return (Idx == -1) ? NULL : &getOperand(Idx);
369 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
370 /// the specified register or -1 if it is not found. If isDead is true, defs
371 /// that are not dead are skipped. If Overlap is true, then it also looks for
372 /// defs that merely overlap the specified register. If TargetRegisterInfo is
373 /// non-null, then it also checks if there is a def of a super-register.
374 int findRegisterDefOperandIdx(unsigned Reg,
375 bool isDead = false, bool Overlap = false,
376 const TargetRegisterInfo *TRI = NULL) const;
378 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
379 /// a pointer to the MachineOperand rather than an index.
380 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
381 const TargetRegisterInfo *TRI = NULL) {
382 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
383 return (Idx == -1) ? NULL : &getOperand(Idx);
386 /// findFirstPredOperandIdx() - Find the index of the first operand in the
387 /// operand list that is used to represent the predicate. It returns -1 if
389 int findFirstPredOperandIdx() const;
391 /// isRegTiedToUseOperand - Given the index of a register def operand,
392 /// check if the register def is tied to a source operand, due to either
393 /// two-address elimination or inline assembly constraints. Returns the
394 /// first tied use operand index by reference is UseOpIdx is not null.
395 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
397 /// isRegTiedToDefOperand - Return true if the use operand of the specified
398 /// index is tied to an def operand. It also returns the def operand index by
399 /// reference if DefOpIdx is not null.
400 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
402 /// clearKillInfo - Clears kill flags on all operands.
404 void clearKillInfo();
406 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
408 void copyKillDeadInfo(const MachineInstr *MI);
410 /// copyPredicates - Copies predicate operand(s) from MI.
411 void copyPredicates(const MachineInstr *MI);
413 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
414 /// properly composing subreg indices where necessary.
415 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
416 const TargetRegisterInfo &RegInfo);
418 /// addRegisterKilled - We have determined MI kills a register. Look for the
419 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
420 /// add a implicit operand if it's not found. Returns true if the operand
421 /// exists / is added.
422 bool addRegisterKilled(unsigned IncomingReg,
423 const TargetRegisterInfo *RegInfo,
424 bool AddIfNotFound = false);
426 /// addRegisterDead - We have determined MI defined a register without a use.
427 /// Look for the operand that defines it and mark it as IsDead. If
428 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
429 /// true if the operand exists / is added.
430 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
431 bool AddIfNotFound = false);
433 /// addRegisterDefined - We have determined MI defines a register. Make sure
434 /// there is an operand defining Reg.
435 void addRegisterDefined(unsigned IncomingReg,
436 const TargetRegisterInfo *RegInfo = 0);
438 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
439 /// dead except those in the UsedRegs list.
440 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
441 const TargetRegisterInfo &TRI);
443 /// isSafeToMove - Return true if it is safe to move this instruction. If
444 /// SawStore is set to true, it means that there is a store (or call) between
445 /// the instruction's location and its intended destination.
446 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
447 bool &SawStore) const;
449 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
450 /// instruction which defined the specified register instead of copying it.
451 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
452 unsigned DstReg) const;
454 /// hasVolatileMemoryRef - Return true if this instruction may have a
455 /// volatile memory reference, or if the information describing the
456 /// memory reference is not available. Return false if it is known to
457 /// have no volatile memory references.
458 bool hasVolatileMemoryRef() const;
460 /// isInvariantLoad - Return true if this instruction is loading from a
461 /// location whose value is invariant across the function. For example,
462 /// loading a value from the constant pool or from the argument area of
463 /// a function if it does not change. This should only return true of *all*
464 /// loads the instruction does are invariant (if it does multiple loads).
465 bool isInvariantLoad(AliasAnalysis *AA) const;
467 /// isConstantValuePHI - If the specified instruction is a PHI that always
468 /// merges together the same virtual register, return the register, otherwise
470 unsigned isConstantValuePHI() const;
472 /// hasUnmodeledSideEffects - Return true if this instruction has side
473 /// effects that are not modeled by mayLoad / mayStore, etc.
474 /// For all instructions, the property is encoded in MCInstrDesc::Flags
475 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
476 /// INLINEASM instruction, in which case the side effect property is encoded
477 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
479 bool hasUnmodeledSideEffects() const;
481 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
483 bool allDefsAreDead() const;
485 /// copyImplicitOps - Copy implicit register operands from specified
486 /// instruction to this instruction.
487 void copyImplicitOps(const MachineInstr *MI);
492 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
495 //===--------------------------------------------------------------------===//
496 // Accessors used to build up machine instructions.
498 /// addOperand - Add the specified operand to the instruction. If it is an
499 /// implicit operand, it is added to the end of the operand list. If it is
500 /// an explicit operand it is added at the end of the explicit operand list
501 /// (before the first implicit operand).
502 void addOperand(const MachineOperand &Op);
504 /// setDesc - Replace the instruction descriptor (thus opcode) of
505 /// the current instruction with a new one.
507 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
509 /// setDebugLoc - Replace current source information with new such.
510 /// Avoid using this, the constructor argument is preferable.
512 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
514 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
515 /// fewer operand than it started with.
517 void RemoveOperand(unsigned i);
519 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
520 /// This function should be used only occasionally. The setMemRefs function
521 /// is the primary method for setting up a MachineInstr's MemRefs list.
522 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
524 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
525 /// list. This does not transfer ownership.
526 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
527 MemRefs = NewMemRefs;
528 MemRefsEnd = NewMemRefsEnd;
532 /// getRegInfo - If this instruction is embedded into a MachineFunction,
533 /// return the MachineRegisterInfo object for the current function, otherwise
535 MachineRegisterInfo *getRegInfo();
537 /// addImplicitDefUseOperands - Add all implicit def and use operands to
538 /// this instruction.
539 void addImplicitDefUseOperands();
541 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
542 /// this instruction from their respective use lists. This requires that the
543 /// operands already be on their use lists.
544 void RemoveRegOperandsFromUseLists();
546 /// AddRegOperandsToUseLists - Add all of the register operands in
547 /// this instruction from their respective use lists. This requires that the
548 /// operands not be on their use lists yet.
549 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
552 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
553 /// MachineInstr* by *value* of the instruction rather than by pointer value.
554 /// The hashing and equality testing functions ignore definitions so this is
555 /// useful for CSE, etc.
556 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
557 static inline MachineInstr *getEmptyKey() {
561 static inline MachineInstr *getTombstoneKey() {
562 return reinterpret_cast<MachineInstr*>(-1);
565 static unsigned getHashValue(const MachineInstr* const &MI);
567 static bool isEqual(const MachineInstr* const &LHS,
568 const MachineInstr* const &RHS) {
569 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
570 LHS == getEmptyKey() || LHS == getTombstoneKey())
572 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
576 //===----------------------------------------------------------------------===//
579 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
584 } // End llvm namespace