1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 class MachineFunction;
38 class MachineMemOperand;
40 //===----------------------------------------------------------------------===//
41 /// MachineInstr - Representation of each machine instruction.
43 class MachineInstr : public ilist_node<MachineInstr> {
45 typedef MachineMemOperand **mmo_iterator;
47 /// Flags to specify different kinds of comments to output in
48 /// assembly code. These flags carry semantic information not
49 /// otherwise easily derivable from the IR text.
57 FrameSetup = 1 << 0, // Instruction is used as a part of
58 // function frame setup code.
59 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
60 // the first MI in a bundle)
63 const MCInstrDesc *MCID; // Instruction descriptor.
65 uint8_t Flags; // Various bits of additional
66 // information about machine
69 uint8_t AsmPrinterFlags; // Various bits of information used by
70 // the AsmPrinter to emit helpful
71 // comments. This is *not* semantic
72 // information. Do not use this for
73 // anything other than to convey comment
74 // information to AsmPrinter.
76 std::vector<MachineOperand> Operands; // the operands
77 mmo_iterator MemRefs; // information on memory references
78 mmo_iterator MemRefsEnd;
79 MachineBasicBlock *Parent; // Pointer to the owning basic block.
80 DebugLoc debugLoc; // Source line information.
82 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
83 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
85 // Intrusive list support
86 friend struct ilist_traits<MachineInstr>;
87 friend struct ilist_traits<MachineBasicBlock>;
88 void setParent(MachineBasicBlock *P) { Parent = P; }
90 /// MachineInstr ctor - This constructor creates a copy of the given
91 /// MachineInstr in the given MachineFunction.
92 MachineInstr(MachineFunction &, const MachineInstr &);
94 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
95 /// MCID NULL and no operands.
98 // The next two constructors have DebugLoc and non-DebugLoc versions;
99 // over time, the non-DebugLoc versions should be phased out and eventually
102 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
103 /// implicit operands. It reserves space for the number of operands specified
104 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
105 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
107 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
108 /// the MachineInstr is created and added to the end of the specified basic
109 /// block. The version with a DebugLoc should be preferred.
110 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
112 /// MachineInstr ctor - This constructor create a MachineInstr and add the
113 /// implicit operands. It reserves space for number of operands specified by
114 /// MCInstrDesc. An explicit DebugLoc is supplied.
115 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
118 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
119 /// the MachineInstr is created and added to the end of the specified basic
121 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
122 const MCInstrDesc &MCID);
126 // MachineInstrs are pool-allocated and owned by MachineFunction.
127 friend class MachineFunction;
130 const MachineBasicBlock* getParent() const { return Parent; }
131 MachineBasicBlock* getParent() { return Parent; }
133 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
135 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
137 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
139 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
141 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
143 bool getAsmPrinterFlag(CommentFlag Flag) const {
144 return AsmPrinterFlags & Flag;
147 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
149 void setAsmPrinterFlag(CommentFlag Flag) {
150 AsmPrinterFlags |= (uint8_t)Flag;
153 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
155 void clearAsmPrinterFlag(CommentFlag Flag) {
156 AsmPrinterFlags &= ~Flag;
159 /// getFlags - Return the MI flags bitvector.
160 uint8_t getFlags() const {
164 /// getFlag - Return whether an MI flag is set.
165 bool getFlag(MIFlag Flag) const {
169 /// setFlag - Set a MI flag.
170 void setFlag(MIFlag Flag) {
171 Flags |= (uint8_t)Flag;
174 void setFlags(unsigned flags) {
178 /// clearFlag - Clear a MI flag.
179 void clearFlag(MIFlag Flag) {
180 Flags &= ~((uint8_t)Flag);
183 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
186 /// A bundle looks like this before it's finalized:
198 /// In this case, the first MI starts a bundle but is not inside a bundle, the
199 /// next 2 MIs are considered "inside" the bundle.
201 /// After a bundle is finalized, it looks like this:
217 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
218 /// a bundle, but the next three MIs are.
219 bool isInsideBundle() const {
220 return getFlag(InsideBundle);
223 /// setIsInsideBundle - Set InsideBundle bit.
225 void setIsInsideBundle(bool Val = true) {
227 setFlag(InsideBundle);
229 clearFlag(InsideBundle);
232 /// getDebugLoc - Returns the debug location id of this MachineInstr.
234 DebugLoc getDebugLoc() const { return debugLoc; }
236 /// emitError - Emit an error referring to the source location of this
237 /// instruction. This should only be used for inline assembly that is somehow
238 /// impossible to compile. Other errors should have been handled much
241 /// If this method returns, the caller should try to recover from the error.
243 void emitError(StringRef Msg) const;
245 /// getDesc - Returns the target instruction descriptor of this
247 const MCInstrDesc &getDesc() const { return *MCID; }
249 /// getOpcode - Returns the opcode of this MachineInstr.
251 int getOpcode() const { return MCID->Opcode; }
253 /// Access to explicit operands of the instruction.
255 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
257 const MachineOperand& getOperand(unsigned i) const {
258 assert(i < getNumOperands() && "getOperand() out of range!");
261 MachineOperand& getOperand(unsigned i) {
262 assert(i < getNumOperands() && "getOperand() out of range!");
266 /// getNumExplicitOperands - Returns the number of non-implicit operands.
268 unsigned getNumExplicitOperands() const;
270 /// iterator/begin/end - Iterate over all operands of a machine instruction.
271 typedef std::vector<MachineOperand>::iterator mop_iterator;
272 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
274 mop_iterator operands_begin() { return Operands.begin(); }
275 mop_iterator operands_end() { return Operands.end(); }
277 const_mop_iterator operands_begin() const { return Operands.begin(); }
278 const_mop_iterator operands_end() const { return Operands.end(); }
280 /// Access to memory operands of the instruction
281 mmo_iterator memoperands_begin() const { return MemRefs; }
282 mmo_iterator memoperands_end() const { return MemRefsEnd; }
283 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
285 /// hasOneMemOperand - Return true if this instruction has exactly one
286 /// MachineMemOperand.
287 bool hasOneMemOperand() const {
288 return MemRefsEnd - MemRefs == 1;
291 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
292 /// queries but they are bundle aware.
295 IgnoreBundle, // Ignore bundles
296 AnyInBundle, // Return true if any instruction in bundle has property
297 AllInBundle // Return true if all instructions in bundle have property
300 /// hasProperty - Return true if the instruction (or in the case of a bundle,
301 /// the instructions inside the bundle) has the specified property.
302 /// The first argument is the property being queried.
303 /// The second argument indicates whether the query should look inside
304 /// instruction bundles.
305 bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
307 /// isVariadic - Return true if this instruction can have a variable number of
308 /// operands. In this case, the variable operands will be after the normal
309 /// operands but before the implicit definitions and uses (if any are
311 bool isVariadic(QueryType Type = IgnoreBundle) const {
312 return hasProperty(MCID::Variadic, Type);
315 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
316 /// ARM instructions which can set condition code if 's' bit is set.
317 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
318 return hasProperty(MCID::HasOptionalDef, Type);
321 /// isPseudo - Return true if this is a pseudo instruction that doesn't
322 /// correspond to a real machine instruction.
324 bool isPseudo(QueryType Type = IgnoreBundle) const {
325 return hasProperty(MCID::Pseudo, Type);
328 bool isReturn(QueryType Type = AnyInBundle) const {
329 return hasProperty(MCID::Return, Type);
332 bool isCall(QueryType Type = AnyInBundle) const {
333 return hasProperty(MCID::Call, Type);
336 /// isBarrier - Returns true if the specified instruction stops control flow
337 /// from executing the instruction immediately following it. Examples include
338 /// unconditional branches and return instructions.
339 bool isBarrier(QueryType Type = AnyInBundle) const {
340 return hasProperty(MCID::Barrier, Type);
343 /// isTerminator - Returns true if this instruction part of the terminator for
344 /// a basic block. Typically this is things like return and branch
347 /// Various passes use this to insert code into the bottom of a basic block,
348 /// but before control flow occurs.
349 bool isTerminator(QueryType Type = AnyInBundle) const {
350 return hasProperty(MCID::Terminator, Type);
353 /// isBranch - Returns true if this is a conditional, unconditional, or
354 /// indirect branch. Predicates below can be used to discriminate between
355 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
356 /// get more information.
357 bool isBranch(QueryType Type = AnyInBundle) const {
358 return hasProperty(MCID::Branch, Type);
361 /// isIndirectBranch - Return true if this is an indirect branch, such as a
362 /// branch through a register.
363 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
364 return hasProperty(MCID::IndirectBranch, Type);
367 /// isConditionalBranch - Return true if this is a branch which may fall
368 /// through to the next instruction or may transfer control flow to some other
369 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
370 /// information about this branch.
371 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
372 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
375 /// isUnconditionalBranch - Return true if this is a branch which always
376 /// transfers control flow to some other block. The
377 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
378 /// about this branch.
379 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
380 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
383 // isPredicable - Return true if this instruction has a predicate operand that
384 // controls execution. It may be set to 'always', or may be set to other
385 /// values. There are various methods in TargetInstrInfo that can be used to
386 /// control and modify the predicate in this instruction.
387 bool isPredicable(QueryType Type = AllInBundle) const {
388 // If it's a bundle than all bundled instructions must be predicable for this
390 return hasProperty(MCID::Predicable, Type);
393 /// isCompare - Return true if this instruction is a comparison.
394 bool isCompare(QueryType Type = IgnoreBundle) const {
395 return hasProperty(MCID::Compare, Type);
398 /// isMoveImmediate - Return true if this instruction is a move immediate
399 /// (including conditional moves) instruction.
400 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
401 return hasProperty(MCID::MoveImm, Type);
404 /// isBitcast - Return true if this instruction is a bitcast instruction.
406 bool isBitcast(QueryType Type = IgnoreBundle) const {
407 return hasProperty(MCID::Bitcast, Type);
410 /// isNotDuplicable - Return true if this instruction cannot be safely
411 /// duplicated. For example, if the instruction has a unique labels attached
412 /// to it, duplicating it would cause multiple definition errors.
413 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
414 return hasProperty(MCID::NotDuplicable, Type);
417 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
418 /// which must be filled by the code generator.
419 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
420 return hasProperty(MCID::DelaySlot, Type);
423 /// canFoldAsLoad - Return true for instructions that can be folded as
424 /// memory operands in other instructions. The most common use for this
425 /// is instructions that are simple loads from memory that don't modify
426 /// the loaded value in any way, but it can also be used for instructions
427 /// that can be expressed as constant-pool loads, such as V_SETALLONES
428 /// on x86, to allow them to be folded when it is beneficial.
429 /// This should only be set on instructions that return a value in their
430 /// only virtual register definition.
431 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
432 return hasProperty(MCID::FoldableAsLoad, Type);
435 //===--------------------------------------------------------------------===//
436 // Side Effect Analysis
437 //===--------------------------------------------------------------------===//
439 /// mayLoad - Return true if this instruction could possibly read memory.
440 /// Instructions with this flag set are not necessarily simple load
441 /// instructions, they may load a value and modify it, for example.
442 bool mayLoad(QueryType Type = AnyInBundle) const {
443 return hasProperty(MCID::MayLoad, Type);
447 /// mayStore - Return true if this instruction could possibly modify memory.
448 /// Instructions with this flag set are not necessarily simple store
449 /// instructions, they may store a modified value based on their operands, or
450 /// may not actually modify anything, for example.
451 bool mayStore(QueryType Type = AnyInBundle) const {
452 return hasProperty(MCID::MayStore, Type);
455 //===--------------------------------------------------------------------===//
456 // Flags that indicate whether an instruction can be modified by a method.
457 //===--------------------------------------------------------------------===//
459 /// isCommutable - Return true if this may be a 2- or 3-address
460 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
461 /// result if Y and Z are exchanged. If this flag is set, then the
462 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
465 /// Note that this flag may be set on instructions that are only commutable
466 /// sometimes. In these cases, the call to commuteInstruction will fail.
467 /// Also note that some instructions require non-trivial modification to
469 bool isCommutable(QueryType Type = IgnoreBundle) const {
470 return hasProperty(MCID::Commutable, Type);
473 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
474 /// which can be changed into a 3-address instruction if needed. Doing this
475 /// transformation can be profitable in the register allocator, because it
476 /// means that the instruction can use a 2-address form if possible, but
477 /// degrade into a less efficient form if the source and dest register cannot
478 /// be assigned to the same register. For example, this allows the x86
479 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
480 /// is the same speed as the shift but has bigger code size.
482 /// If this returns true, then the target must implement the
483 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
484 /// is allowed to fail if the transformation isn't valid for this specific
485 /// instruction (e.g. shl reg, 4 on x86).
487 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
488 return hasProperty(MCID::ConvertibleTo3Addr, Type);
491 /// usesCustomInsertionHook - Return true if this instruction requires
492 /// custom insertion support when the DAG scheduler is inserting it into a
493 /// machine basic block. If this is true for the instruction, it basically
494 /// means that it is a pseudo instruction used at SelectionDAG time that is
495 /// expanded out into magic code by the target when MachineInstrs are formed.
497 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
498 /// is used to insert this into the MachineBasicBlock.
499 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
500 return hasProperty(MCID::UsesCustomInserter, Type);
503 /// hasPostISelHook - Return true if this instruction requires *adjustment*
504 /// after instruction selection by calling a target hook. For example, this
505 /// can be used to fill in ARM 's' optional operand depending on whether
506 /// the conditional flag register is used.
507 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
508 return hasProperty(MCID::HasPostISelHook, Type);
511 /// isRematerializable - Returns true if this instruction is a candidate for
512 /// remat. This flag is deprecated, please don't use it anymore. If this
513 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
514 /// verify the instruction is really rematable.
515 bool isRematerializable(QueryType Type = AllInBundle) const {
516 // It's only possible to re-mat a bundle if all bundled instructions are
517 // re-materializable.
518 return hasProperty(MCID::Rematerializable, Type);
521 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
522 /// less) than a move instruction. This is useful during certain types of
523 /// optimizations (e.g., remat during two-address conversion or machine licm)
524 /// where we would like to remat or hoist the instruction, but not if it costs
525 /// more than moving the instruction into the appropriate register. Note, we
526 /// are not marking copies from and to the same register class with this flag.
527 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
528 // Only returns true for a bundle if all bundled instructions are cheap.
529 // FIXME: This probably requires a target hook.
530 return hasProperty(MCID::CheapAsAMove, Type);
533 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
534 /// have special register allocation requirements that are not captured by the
535 /// operand register classes. e.g. ARM::STRD's two source registers must be an
536 /// even / odd pair, ARM::STM registers have to be in ascending order.
537 /// Post-register allocation passes should not attempt to change allocations
538 /// for sources of instructions with this flag.
539 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
540 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
543 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
544 /// have special register allocation requirements that are not captured by the
545 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
546 /// even / odd pair, ARM::LDM registers have to be in ascending order.
547 /// Post-register allocation passes should not attempt to change allocations
548 /// for definitions of instructions with this flag.
549 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
550 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
555 CheckDefs, // Check all operands for equality
556 CheckKillDead, // Check all operands including kill / dead markers
557 IgnoreDefs, // Ignore all definitions
558 IgnoreVRegDefs // Ignore virtual register definitions
561 /// isIdenticalTo - Return true if this instruction is identical to (same
562 /// opcode and same operands as) the specified instruction.
563 bool isIdenticalTo(const MachineInstr *Other,
564 MICheckType Check = CheckDefs) const;
566 /// removeFromParent - This method unlinks 'this' from the containing basic
567 /// block, and returns it, but does not delete it.
568 MachineInstr *removeFromParent();
570 /// eraseFromParent - This method unlinks 'this' from the containing basic
571 /// block and deletes it.
572 void eraseFromParent();
574 /// isLabel - Returns true if the MachineInstr represents a label.
576 bool isLabel() const {
577 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
578 getOpcode() == TargetOpcode::EH_LABEL ||
579 getOpcode() == TargetOpcode::GC_LABEL;
582 bool isPrologLabel() const {
583 return getOpcode() == TargetOpcode::PROLOG_LABEL;
585 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
586 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
587 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
589 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
590 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
591 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
592 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
593 bool isStackAligningInlineAsm() const;
594 bool isInsertSubreg() const {
595 return getOpcode() == TargetOpcode::INSERT_SUBREG;
597 bool isSubregToReg() const {
598 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
600 bool isRegSequence() const {
601 return getOpcode() == TargetOpcode::REG_SEQUENCE;
603 bool isBundle() const {
604 return getOpcode() == TargetOpcode::BUNDLE;
606 bool isCopy() const {
607 return getOpcode() == TargetOpcode::COPY;
609 bool isFullCopy() const {
610 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
613 /// isCopyLike - Return true if the instruction behaves like a copy.
614 /// This does not include native copy instructions.
615 bool isCopyLike() const {
616 return isCopy() || isSubregToReg();
619 /// isIdentityCopy - Return true is the instruction is an identity copy.
620 bool isIdentityCopy() const {
621 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
622 getOperand(0).getSubReg() == getOperand(1).getSubReg();
625 /// getBundleSize - Return the number of instructions inside the MI bundle.
626 unsigned getBundleSize() const;
628 /// readsRegister - Return true if the MachineInstr reads the specified
629 /// register. If TargetRegisterInfo is passed, then it also checks if there
630 /// is a read of a super-register.
631 /// This does not count partial redefines of virtual registers as reads:
633 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
634 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
637 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
638 /// virtual register. Take into account that a partial define is a
639 /// read-modify-write operation.
640 bool readsVirtualRegister(unsigned Reg) const {
641 return readsWritesVirtualRegister(Reg).first;
644 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
645 /// indicating if this instruction reads or writes Reg. This also considers
647 /// If Ops is not null, all operand indices for Reg are added.
648 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
649 SmallVectorImpl<unsigned> *Ops = 0) const;
651 /// killsRegister - Return true if the MachineInstr kills the specified
652 /// register. If TargetRegisterInfo is passed, then it also checks if there is
653 /// a kill of a super-register.
654 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
655 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
658 /// definesRegister - Return true if the MachineInstr fully defines the
659 /// specified register. If TargetRegisterInfo is passed, then it also checks
660 /// if there is a def of a super-register.
661 /// NOTE: It's ignoring subreg indices on virtual registers.
662 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
663 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
666 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
667 /// or partially define) the specified register.
668 /// NOTE: It's ignoring subreg indices on virtual registers.
669 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
670 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
673 /// registerDefIsDead - Returns true if the register is dead in this machine
674 /// instruction. If TargetRegisterInfo is passed, then it also checks
675 /// if there is a dead def of a super-register.
676 bool registerDefIsDead(unsigned Reg,
677 const TargetRegisterInfo *TRI = NULL) const {
678 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
681 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
682 /// the specific register or -1 if it is not found. It further tightens
683 /// the search criteria to a use that kills the register if isKill is true.
684 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
685 const TargetRegisterInfo *TRI = NULL) const;
687 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
688 /// a pointer to the MachineOperand rather than an index.
689 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
690 const TargetRegisterInfo *TRI = NULL) {
691 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
692 return (Idx == -1) ? NULL : &getOperand(Idx);
695 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
696 /// the specified register or -1 if it is not found. If isDead is true, defs
697 /// that are not dead are skipped. If Overlap is true, then it also looks for
698 /// defs that merely overlap the specified register. If TargetRegisterInfo is
699 /// non-null, then it also checks if there is a def of a super-register.
700 int findRegisterDefOperandIdx(unsigned Reg,
701 bool isDead = false, bool Overlap = false,
702 const TargetRegisterInfo *TRI = NULL) const;
704 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
705 /// a pointer to the MachineOperand rather than an index.
706 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
707 const TargetRegisterInfo *TRI = NULL) {
708 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
709 return (Idx == -1) ? NULL : &getOperand(Idx);
712 /// findFirstPredOperandIdx() - Find the index of the first operand in the
713 /// operand list that is used to represent the predicate. It returns -1 if
715 int findFirstPredOperandIdx() const;
717 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
718 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
719 /// getOperand(OpIdx) does not belong to an inline asm operand group.
721 /// If GroupNo is not NULL, it will receive the number of the operand group
722 /// containing OpIdx.
724 /// The flag operand is an immediate that can be decoded with methods like
725 /// InlineAsm::hasRegClassConstraint().
727 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
729 /// getRegClassConstraint - Compute the static register class constraint for
730 /// operand OpIdx. For normal instructions, this is derived from the
731 /// MCInstrDesc. For inline assembly it is derived from the flag words.
733 /// Returns NULL if the static register classs constraint cannot be
736 const TargetRegisterClass*
737 getRegClassConstraint(unsigned OpIdx,
738 const TargetInstrInfo *TII,
739 const TargetRegisterInfo *TRI) const;
741 /// isRegTiedToUseOperand - Given the index of a register def operand,
742 /// check if the register def is tied to a source operand, due to either
743 /// two-address elimination or inline assembly constraints. Returns the
744 /// first tied use operand index by reference if UseOpIdx is not null.
745 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
747 /// isRegTiedToDefOperand - Return true if the use operand of the specified
748 /// index is tied to an def operand. It also returns the def operand index by
749 /// reference if DefOpIdx is not null.
750 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
752 /// clearKillInfo - Clears kill flags on all operands.
754 void clearKillInfo();
756 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
758 void copyKillDeadInfo(const MachineInstr *MI);
760 /// copyPredicates - Copies predicate operand(s) from MI.
761 void copyPredicates(const MachineInstr *MI);
763 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
764 /// properly composing subreg indices where necessary.
765 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
766 const TargetRegisterInfo &RegInfo);
768 /// addRegisterKilled - We have determined MI kills a register. Look for the
769 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
770 /// add a implicit operand if it's not found. Returns true if the operand
771 /// exists / is added.
772 bool addRegisterKilled(unsigned IncomingReg,
773 const TargetRegisterInfo *RegInfo,
774 bool AddIfNotFound = false);
776 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
777 /// provided, this includes super-register kills.
778 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
780 /// addRegisterDead - We have determined MI defined a register without a use.
781 /// Look for the operand that defines it and mark it as IsDead. If
782 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
783 /// true if the operand exists / is added.
784 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
785 bool AddIfNotFound = false);
787 /// addRegisterDefined - We have determined MI defines a register. Make sure
788 /// there is an operand defining Reg.
789 void addRegisterDefined(unsigned IncomingReg,
790 const TargetRegisterInfo *RegInfo = 0);
792 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
793 /// dead except those in the UsedRegs list.
794 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
795 const TargetRegisterInfo &TRI);
797 /// isSafeToMove - Return true if it is safe to move this instruction. If
798 /// SawStore is set to true, it means that there is a store (or call) between
799 /// the instruction's location and its intended destination.
800 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
801 bool &SawStore) const;
803 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
804 /// instruction which defined the specified register instead of copying it.
805 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
806 unsigned DstReg) const;
808 /// hasVolatileMemoryRef - Return true if this instruction may have a
809 /// volatile memory reference, or if the information describing the
810 /// memory reference is not available. Return false if it is known to
811 /// have no volatile memory references.
812 bool hasVolatileMemoryRef() const;
814 /// isInvariantLoad - Return true if this instruction is loading from a
815 /// location whose value is invariant across the function. For example,
816 /// loading a value from the constant pool or from the argument area of
817 /// a function if it does not change. This should only return true of *all*
818 /// loads the instruction does are invariant (if it does multiple loads).
819 bool isInvariantLoad(AliasAnalysis *AA) const;
821 /// isConstantValuePHI - If the specified instruction is a PHI that always
822 /// merges together the same virtual register, return the register, otherwise
824 unsigned isConstantValuePHI() const;
826 /// hasUnmodeledSideEffects - Return true if this instruction has side
827 /// effects that are not modeled by mayLoad / mayStore, etc.
828 /// For all instructions, the property is encoded in MCInstrDesc::Flags
829 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
830 /// INLINEASM instruction, in which case the side effect property is encoded
831 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
833 bool hasUnmodeledSideEffects() const;
835 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
837 bool allDefsAreDead() const;
839 /// copyImplicitOps - Copy implicit register operands from specified
840 /// instruction to this instruction.
841 void copyImplicitOps(const MachineInstr *MI);
846 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
849 //===--------------------------------------------------------------------===//
850 // Accessors used to build up machine instructions.
852 /// addOperand - Add the specified operand to the instruction. If it is an
853 /// implicit operand, it is added to the end of the operand list. If it is
854 /// an explicit operand it is added at the end of the explicit operand list
855 /// (before the first implicit operand).
856 void addOperand(const MachineOperand &Op);
858 /// setDesc - Replace the instruction descriptor (thus opcode) of
859 /// the current instruction with a new one.
861 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
863 /// setDebugLoc - Replace current source information with new such.
864 /// Avoid using this, the constructor argument is preferable.
866 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
868 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
869 /// fewer operand than it started with.
871 void RemoveOperand(unsigned i);
873 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
874 /// This function should be used only occasionally. The setMemRefs function
875 /// is the primary method for setting up a MachineInstr's MemRefs list.
876 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
878 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
879 /// list. This does not transfer ownership.
880 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
881 MemRefs = NewMemRefs;
882 MemRefsEnd = NewMemRefsEnd;
886 /// getRegInfo - If this instruction is embedded into a MachineFunction,
887 /// return the MachineRegisterInfo object for the current function, otherwise
889 MachineRegisterInfo *getRegInfo();
891 /// addImplicitDefUseOperands - Add all implicit def and use operands to
892 /// this instruction.
893 void addImplicitDefUseOperands();
895 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
896 /// this instruction from their respective use lists. This requires that the
897 /// operands already be on their use lists.
898 void RemoveRegOperandsFromUseLists();
900 /// AddRegOperandsToUseLists - Add all of the register operands in
901 /// this instruction from their respective use lists. This requires that the
902 /// operands not be on their use lists yet.
903 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
906 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
907 /// MachineInstr* by *value* of the instruction rather than by pointer value.
908 /// The hashing and equality testing functions ignore definitions so this is
909 /// useful for CSE, etc.
910 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
911 static inline MachineInstr *getEmptyKey() {
915 static inline MachineInstr *getTombstoneKey() {
916 return reinterpret_cast<MachineInstr*>(-1);
919 static unsigned getHashValue(const MachineInstr* const &MI);
921 static bool isEqual(const MachineInstr* const &LHS,
922 const MachineInstr* const &RHS) {
923 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
924 LHS == getEmptyKey() || LHS == getTombstoneKey())
926 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
930 //===----------------------------------------------------------------------===//
933 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
938 } // End llvm namespace