1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
55 const TargetInstrDesc *TID; // Instruction descriptor.
56 unsigned short NumImplicitOps; // Number of implicit operands (which
57 // are determined at construction time).
59 unsigned short AsmPrinterFlags; // Various bits of information used by
60 // the AsmPrinter to emit helpful
61 // comments. This is *not* semantic
62 // information. Do not use this for
63 // anything other than to convey comment
64 // information to AsmPrinter.
66 std::vector<MachineOperand> Operands; // the operands
67 mmo_iterator MemRefs; // information on memory references
68 mmo_iterator MemRefsEnd;
69 MachineBasicBlock *Parent; // Pointer to the owning basic block.
70 DebugLoc debugLoc; // Source line information.
72 // OperandComplete - Return true if it's illegal to add a new operand
73 bool OperandsComplete() const;
75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
78 // Intrusive list support
79 friend struct ilist_traits<MachineInstr>;
80 friend struct ilist_traits<MachineBasicBlock>;
81 void setParent(MachineBasicBlock *P) { Parent = P; }
83 /// MachineInstr ctor - This constructor creates a copy of the given
84 /// MachineInstr in the given MachineFunction.
85 MachineInstr(MachineFunction &, const MachineInstr &);
87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
88 /// TID NULL and no operands.
91 // The next two constructors have DebugLoc and non-DebugLoc versions;
92 // over time, the non-DebugLoc versions should be phased out and eventually
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96 /// implicit operands. It reserves space for the number of operands specified
97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
101 /// the MachineInstr is created and added to the end of the specified basic
102 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (unsigned short)Flag;
142 /// getDebugLoc - Returns the debug location id of this MachineInstr.
144 DebugLoc getDebugLoc() const { return debugLoc; }
146 /// getDesc - Returns the target instruction descriptor of this
148 const TargetInstrDesc &getDesc() const { return *TID; }
150 /// getOpcode - Returns the opcode of this MachineInstr.
152 int getOpcode() const { return TID->Opcode; }
154 /// Access to explicit operands of the instruction.
156 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
158 const MachineOperand& getOperand(unsigned i) const {
159 assert(i < getNumOperands() && "getOperand() out of range!");
162 MachineOperand& getOperand(unsigned i) {
163 assert(i < getNumOperands() && "getOperand() out of range!");
167 /// getNumExplicitOperands - Returns the number of non-implicit operands.
169 unsigned getNumExplicitOperands() const;
171 /// Access to memory operands of the instruction
172 mmo_iterator memoperands_begin() const { return MemRefs; }
173 mmo_iterator memoperands_end() const { return MemRefsEnd; }
174 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
176 /// hasOneMemOperand - Return true if this instruction has exactly one
177 /// MachineMemOperand.
178 bool hasOneMemOperand() const {
179 return MemRefsEnd - MemRefs == 1;
183 CheckDefs, // Check all operands for equality
184 IgnoreDefs, // Ignore all definitions
185 IgnoreVRegDefs // Ignore virtual register definitions
188 /// isIdenticalTo - Return true if this instruction is identical to (same
189 /// opcode and same operands as) the specified instruction.
190 bool isIdenticalTo(const MachineInstr *Other,
191 MICheckType Check = CheckDefs) const;
193 /// removeFromParent - This method unlinks 'this' from the containing basic
194 /// block, and returns it, but does not delete it.
195 MachineInstr *removeFromParent();
197 /// eraseFromParent - This method unlinks 'this' from the containing basic
198 /// block and deletes it.
199 void eraseFromParent();
201 /// isLabel - Returns true if the MachineInstr represents a label.
203 bool isLabel() const {
204 return getOpcode() == TargetOpcode::DBG_LABEL ||
205 getOpcode() == TargetOpcode::EH_LABEL ||
206 getOpcode() == TargetOpcode::GC_LABEL;
209 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
210 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
211 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
212 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
214 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
215 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
216 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
217 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
218 bool isInsertSubreg() const {
219 return getOpcode() == TargetOpcode::INSERT_SUBREG;
221 bool isSubregToReg() const {
222 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
224 bool isRegSequence() const {
225 return getOpcode() == TargetOpcode::REG_SEQUENCE;
227 bool isCopy() const {
228 return getOpcode() == TargetOpcode::COPY;
231 /// isCopyLike - Return true if the instruction behaves like a copy.
232 /// This does not include native copy instructions.
233 bool isCopyLike() const {
234 return isCopy() || isSubregToReg();
237 /// isIdentityCopy - Return true is the instruction is an identity copy.
238 bool isIdentityCopy() const {
239 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
240 getOperand(0).getSubReg() == getOperand(1).getSubReg();
243 /// readsRegister - Return true if the MachineInstr reads the specified
244 /// register. If TargetRegisterInfo is passed, then it also checks if there
245 /// is a read of a super-register.
246 /// This does not count partial redefines of virtual registers as reads:
248 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
249 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
252 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
253 /// virtual register. Take into account that a partial define is a
254 /// read-modify-write operation.
255 bool readsVirtualRegister(unsigned Reg) const {
256 return readsWritesVirtualRegister(Reg).first;
259 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
260 /// indicating if this instruction reads or writes Reg. This also considers
262 /// If Ops is not null, all operand indices for Reg are added.
263 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
264 SmallVectorImpl<unsigned> *Ops = 0) const;
266 /// killsRegister - Return true if the MachineInstr kills the specified
267 /// register. If TargetRegisterInfo is passed, then it also checks if there is
268 /// a kill of a super-register.
269 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
270 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
273 /// definesRegister - Return true if the MachineInstr fully defines the
274 /// specified register. If TargetRegisterInfo is passed, then it also checks
275 /// if there is a def of a super-register.
276 /// NOTE: It's ignoring subreg indices on virtual registers.
277 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
278 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
281 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
282 /// or partially define) the specified register.
283 /// NOTE: It's ignoring subreg indices on virtual registers.
284 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
285 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
288 /// registerDefIsDead - Returns true if the register is dead in this machine
289 /// instruction. If TargetRegisterInfo is passed, then it also checks
290 /// if there is a dead def of a super-register.
291 bool registerDefIsDead(unsigned Reg,
292 const TargetRegisterInfo *TRI = NULL) const {
293 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
296 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
297 /// the specific register or -1 if it is not found. It further tightens
298 /// the search criteria to a use that kills the register if isKill is true.
299 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
300 const TargetRegisterInfo *TRI = NULL) const;
302 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
303 /// a pointer to the MachineOperand rather than an index.
304 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
305 const TargetRegisterInfo *TRI = NULL) {
306 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
307 return (Idx == -1) ? NULL : &getOperand(Idx);
310 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
311 /// the specified register or -1 if it is not found. If isDead is true, defs
312 /// that are not dead are skipped. If Overlap is true, then it also looks for
313 /// defs that merely overlap the specified register. If TargetRegisterInfo is
314 /// non-null, then it also checks if there is a def of a super-register.
315 int findRegisterDefOperandIdx(unsigned Reg,
316 bool isDead = false, bool Overlap = false,
317 const TargetRegisterInfo *TRI = NULL) const;
319 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
320 /// a pointer to the MachineOperand rather than an index.
321 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
322 const TargetRegisterInfo *TRI = NULL) {
323 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
324 return (Idx == -1) ? NULL : &getOperand(Idx);
327 /// findFirstPredOperandIdx() - Find the index of the first operand in the
328 /// operand list that is used to represent the predicate. It returns -1 if
330 int findFirstPredOperandIdx() const;
332 /// isRegTiedToUseOperand - Given the index of a register def operand,
333 /// check if the register def is tied to a source operand, due to either
334 /// two-address elimination or inline assembly constraints. Returns the
335 /// first tied use operand index by reference is UseOpIdx is not null.
336 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
338 /// isRegTiedToDefOperand - Return true if the use operand of the specified
339 /// index is tied to an def operand. It also returns the def operand index by
340 /// reference if DefOpIdx is not null.
341 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
343 /// clearKillInfo - Clears kill flags on all operands.
345 void clearKillInfo();
347 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
349 void copyKillDeadInfo(const MachineInstr *MI);
351 /// copyPredicates - Copies predicate operand(s) from MI.
352 void copyPredicates(const MachineInstr *MI);
354 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
355 /// properly composing subreg indices where necessary.
356 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
357 const TargetRegisterInfo &RegInfo);
359 /// addRegisterKilled - We have determined MI kills a register. Look for the
360 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
361 /// add a implicit operand if it's not found. Returns true if the operand
362 /// exists / is added.
363 bool addRegisterKilled(unsigned IncomingReg,
364 const TargetRegisterInfo *RegInfo,
365 bool AddIfNotFound = false);
367 /// addRegisterDead - We have determined MI defined a register without a use.
368 /// Look for the operand that defines it and mark it as IsDead. If
369 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
370 /// true if the operand exists / is added.
371 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
372 bool AddIfNotFound = false);
374 /// addRegisterDefined - We have determined MI defines a register. Make sure
375 /// there is an operand defining Reg.
376 void addRegisterDefined(unsigned IncomingReg,
377 const TargetRegisterInfo *RegInfo = 0);
379 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
380 /// except those in the UsedRegs list.
381 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
382 const TargetRegisterInfo &TRI);
384 /// isSafeToMove - Return true if it is safe to move this instruction. If
385 /// SawStore is set to true, it means that there is a store (or call) between
386 /// the instruction's location and its intended destination.
387 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
388 bool &SawStore) const;
390 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
391 /// instruction which defined the specified register instead of copying it.
392 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
393 unsigned DstReg) const;
395 /// hasVolatileMemoryRef - Return true if this instruction may have a
396 /// volatile memory reference, or if the information describing the
397 /// memory reference is not available. Return false if it is known to
398 /// have no volatile memory references.
399 bool hasVolatileMemoryRef() const;
401 /// isInvariantLoad - Return true if this instruction is loading from a
402 /// location whose value is invariant across the function. For example,
403 /// loading a value from the constant pool or from the argument area of
404 /// a function if it does not change. This should only return true of *all*
405 /// loads the instruction does are invariant (if it does multiple loads).
406 bool isInvariantLoad(AliasAnalysis *AA) const;
408 /// isConstantValuePHI - If the specified instruction is a PHI that always
409 /// merges together the same virtual register, return the register, otherwise
411 unsigned isConstantValuePHI() const;
413 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
415 bool allDefsAreDead() const;
420 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
423 //===--------------------------------------------------------------------===//
424 // Accessors used to build up machine instructions.
426 /// addOperand - Add the specified operand to the instruction. If it is an
427 /// implicit operand, it is added to the end of the operand list. If it is
428 /// an explicit operand it is added at the end of the explicit operand list
429 /// (before the first implicit operand).
430 void addOperand(const MachineOperand &Op);
432 /// setDesc - Replace the instruction descriptor (thus opcode) of
433 /// the current instruction with a new one.
435 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
437 /// setDebugLoc - Replace current source information with new such.
438 /// Avoid using this, the constructor argument is preferable.
440 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
442 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
443 /// fewer operand than it started with.
445 void RemoveOperand(unsigned i);
447 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
448 /// This function should be used only occasionally. The setMemRefs function
449 /// is the primary method for setting up a MachineInstr's MemRefs list.
450 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
452 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
453 /// list. This does not transfer ownership.
454 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
455 MemRefs = NewMemRefs;
456 MemRefsEnd = NewMemRefsEnd;
460 /// getRegInfo - If this instruction is embedded into a MachineFunction,
461 /// return the MachineRegisterInfo object for the current function, otherwise
463 MachineRegisterInfo *getRegInfo();
465 /// addImplicitDefUseOperands - Add all implicit def and use operands to
466 /// this instruction.
467 void addImplicitDefUseOperands();
469 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
470 /// this instruction from their respective use lists. This requires that the
471 /// operands already be on their use lists.
472 void RemoveRegOperandsFromUseLists();
474 /// AddRegOperandsToUseLists - Add all of the register operands in
475 /// this instruction from their respective use lists. This requires that the
476 /// operands not be on their use lists yet.
477 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
480 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
481 /// MachineInstr* by *value* of the instruction rather than by pointer value.
482 /// The hashing and equality testing functions ignore definitions so this is
483 /// useful for CSE, etc.
484 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
485 static inline MachineInstr *getEmptyKey() {
489 static inline MachineInstr *getTombstoneKey() {
490 return reinterpret_cast<MachineInstr*>(-1);
493 static unsigned getHashValue(const MachineInstr* const &MI);
495 static bool isEqual(const MachineInstr* const &LHS,
496 const MachineInstr* const &RHS) {
497 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
498 LHS == getEmptyKey() || LHS == getTombstoneKey())
500 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
504 //===----------------------------------------------------------------------===//
507 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
512 } // End llvm namespace