1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
32 class TargetInstrDesc;
33 class TargetInstrInfo;
34 class TargetRegisterInfo;
35 class MachineFunction;
36 class MachineMemOperand;
38 //===----------------------------------------------------------------------===//
39 /// MachineInstr - Representation of each machine instruction.
41 class MachineInstr : public ilist_node<MachineInstr> {
43 typedef MachineMemOperand **mmo_iterator;
45 /// Flags to specify different kinds of comments to output in
46 /// assembly code. These flags carry semantic information not
47 /// otherwise easily derivable from the IR text.
54 const TargetInstrDesc *TID; // Instruction descriptor.
55 unsigned short NumImplicitOps; // Number of implicit operands (which
56 // are determined at construction time).
58 unsigned short AsmPrinterFlags; // Various bits of information used by
59 // the AsmPrinter to emit helpful
60 // comments. This is *not* semantic
61 // information. Do not use this for
62 // anything other than to convey comment
63 // information to AsmPrinter.
65 std::vector<MachineOperand> Operands; // the operands
66 mmo_iterator MemRefs; // information on memory references
67 mmo_iterator MemRefsEnd;
68 MachineBasicBlock *Parent; // Pointer to the owning basic block.
69 DebugLoc debugLoc; // Source line information.
71 // OperandComplete - Return true if it's illegal to add a new operand
72 bool OperandsComplete() const;
74 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
75 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
77 // Intrusive list support
78 friend struct ilist_traits<MachineInstr>;
79 friend struct ilist_traits<MachineBasicBlock>;
80 void setParent(MachineBasicBlock *P) { Parent = P; }
82 /// MachineInstr ctor - This constructor creates a copy of the given
83 /// MachineInstr in the given MachineFunction.
84 MachineInstr(MachineFunction &, const MachineInstr &);
86 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
87 /// TID NULL and no operands.
90 // The next two constructors have DebugLoc and non-DebugLoc versions;
91 // over time, the non-DebugLoc versions should be phased out and eventually
94 /// MachineInstr ctor - This constructor create a MachineInstr and add the
95 /// implicit operands. It reserves space for number of operands specified by
96 /// TargetInstrDesc. The version with a DebugLoc should be preferred.
97 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
99 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
100 /// the MachineInstr is created and added to the end of the specified basic
101 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
115 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
116 const TargetInstrDesc &TID);
120 // MachineInstrs are pool-allocated and owned by MachineFunction.
121 friend class MachineFunction;
124 const MachineBasicBlock* getParent() const { return Parent; }
125 MachineBasicBlock* getParent() { return Parent; }
127 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
129 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (unsigned short)Flag;
143 /// getDebugLoc - Returns the debug location id of this MachineInstr.
145 DebugLoc getDebugLoc() const { return debugLoc; }
147 /// getDesc - Returns the target instruction descriptor of this
149 const TargetInstrDesc &getDesc() const { return *TID; }
151 /// getOpcode - Returns the opcode of this MachineInstr.
153 int getOpcode() const { return TID->Opcode; }
155 /// Access to explicit operands of the instruction.
157 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
159 const MachineOperand& getOperand(unsigned i) const {
160 assert(i < getNumOperands() && "getOperand() out of range!");
163 MachineOperand& getOperand(unsigned i) {
164 assert(i < getNumOperands() && "getOperand() out of range!");
168 /// getNumExplicitOperands - Returns the number of non-implicit operands.
170 unsigned getNumExplicitOperands() const;
172 /// Access to memory operands of the instruction
173 mmo_iterator memoperands_begin() const { return MemRefs; }
174 mmo_iterator memoperands_end() const { return MemRefsEnd; }
175 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
177 /// hasOneMemOperand - Return true if this instruction has exactly one
178 /// MachineMemOperand.
179 bool hasOneMemOperand() const {
180 return MemRefsEnd - MemRefs == 1;
184 CheckDefs, // Check all operands for equality
185 IgnoreDefs, // Ignore all definitions
186 IgnoreVRegDefs // Ignore virtual register definitions
189 /// isIdenticalTo - Return true if this instruction is identical to (same
190 /// opcode and same operands as) the specified instruction.
191 bool isIdenticalTo(const MachineInstr *Other,
192 MICheckType Check = CheckDefs) const;
194 /// removeFromParent - This method unlinks 'this' from the containing basic
195 /// block, and returns it, but does not delete it.
196 MachineInstr *removeFromParent();
198 /// eraseFromParent - This method unlinks 'this' from the containing basic
199 /// block and deletes it.
200 void eraseFromParent();
202 /// isLabel - Returns true if the MachineInstr represents a label.
204 bool isLabel() const {
205 return getOpcode() == TargetOpcode::DBG_LABEL ||
206 getOpcode() == TargetOpcode::EH_LABEL ||
207 getOpcode() == TargetOpcode::GC_LABEL;
210 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
211 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
212 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
213 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
215 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
216 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
217 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
218 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
219 bool isExtractSubreg() const {
220 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
222 bool isInsertSubreg() const {
223 return getOpcode() == TargetOpcode::INSERT_SUBREG;
225 bool isSubregToReg() const {
226 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
229 /// readsRegister - Return true if the MachineInstr reads the specified
230 /// register. If TargetRegisterInfo is passed, then it also checks if there
231 /// is a read of a super-register.
232 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
233 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
236 /// killsRegister - Return true if the MachineInstr kills the specified
237 /// register. If TargetRegisterInfo is passed, then it also checks if there is
238 /// a kill of a super-register.
239 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
240 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
243 /// modifiesRegister - Return true if the MachineInstr modifies the
244 /// specified register. If TargetRegisterInfo is passed, then it also checks
245 /// if there is a def of a super-register.
246 bool modifiesRegister(unsigned Reg,
247 const TargetRegisterInfo *TRI = NULL) const {
248 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
251 /// registerDefIsDead - Returns true if the register is dead in this machine
252 /// instruction. If TargetRegisterInfo is passed, then it also checks
253 /// if there is a dead def of a super-register.
254 bool registerDefIsDead(unsigned Reg,
255 const TargetRegisterInfo *TRI = NULL) const {
256 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
259 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
260 /// the specific register or -1 if it is not found. It further tightens
261 /// the search criteria to a use that kills the register if isKill is true.
262 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
263 const TargetRegisterInfo *TRI = NULL) const;
265 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
266 /// a pointer to the MachineOperand rather than an index.
267 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
268 const TargetRegisterInfo *TRI = NULL) {
269 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
270 return (Idx == -1) ? NULL : &getOperand(Idx);
273 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
274 /// the specified register or -1 if it is not found. If isDead is true, defs
275 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
276 /// also checks if there is a def of a super-register.
277 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
278 const TargetRegisterInfo *TRI = NULL) const;
280 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
281 /// a pointer to the MachineOperand rather than an index.
282 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
283 const TargetRegisterInfo *TRI = NULL) {
284 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
285 return (Idx == -1) ? NULL : &getOperand(Idx);
288 /// findFirstPredOperandIdx() - Find the index of the first operand in the
289 /// operand list that is used to represent the predicate. It returns -1 if
291 int findFirstPredOperandIdx() const;
293 /// isRegTiedToUseOperand - Given the index of a register def operand,
294 /// check if the register def is tied to a source operand, due to either
295 /// two-address elimination or inline assembly constraints. Returns the
296 /// first tied use operand index by reference is UseOpIdx is not null.
297 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
299 /// isRegTiedToDefOperand - Return true if the use operand of the specified
300 /// index is tied to an def operand. It also returns the def operand index by
301 /// reference if DefOpIdx is not null.
302 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
304 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
306 void copyKillDeadInfo(const MachineInstr *MI);
308 /// copyPredicates - Copies predicate operand(s) from MI.
309 void copyPredicates(const MachineInstr *MI);
311 /// addRegisterKilled - We have determined MI kills a register. Look for the
312 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
313 /// add a implicit operand if it's not found. Returns true if the operand
314 /// exists / is added.
315 bool addRegisterKilled(unsigned IncomingReg,
316 const TargetRegisterInfo *RegInfo,
317 bool AddIfNotFound = false);
319 /// addRegisterDead - We have determined MI defined a register without a use.
320 /// Look for the operand that defines it and mark it as IsDead. If
321 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
322 /// true if the operand exists / is added.
323 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
324 bool AddIfNotFound = false);
326 /// addRegisterDefined - We have determined MI defines a register. Make sure
327 /// there is an operand defining Reg.
328 void addRegisterDefined(unsigned IncomingReg,
329 const TargetRegisterInfo *RegInfo);
331 /// isSafeToMove - Return true if it is safe to move this instruction. If
332 /// SawStore is set to true, it means that there is a store (or call) between
333 /// the instruction's location and its intended destination.
334 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
335 bool &SawStore) const;
337 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
338 /// instruction which defined the specified register instead of copying it.
339 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
340 unsigned DstReg) const;
342 /// hasVolatileMemoryRef - Return true if this instruction may have a
343 /// volatile memory reference, or if the information describing the
344 /// memory reference is not available. Return false if it is known to
345 /// have no volatile memory references.
346 bool hasVolatileMemoryRef() const;
348 /// isInvariantLoad - Return true if this instruction is loading from a
349 /// location whose value is invariant across the function. For example,
350 /// loading a value from the constant pool or from the argument area of
351 /// a function if it does not change. This should only return true of *all*
352 /// loads the instruction does are invariant (if it does multiple loads).
353 bool isInvariantLoad(AliasAnalysis *AA) const;
355 /// isConstantValuePHI - If the specified instruction is a PHI that always
356 /// merges together the same virtual register, return the register, otherwise
358 unsigned isConstantValuePHI() const;
363 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
366 //===--------------------------------------------------------------------===//
367 // Accessors used to build up machine instructions.
369 /// addOperand - Add the specified operand to the instruction. If it is an
370 /// implicit operand, it is added to the end of the operand list. If it is
371 /// an explicit operand it is added at the end of the explicit operand list
372 /// (before the first implicit operand).
373 void addOperand(const MachineOperand &Op);
375 /// setDesc - Replace the instruction descriptor (thus opcode) of
376 /// the current instruction with a new one.
378 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
380 /// setDebugLoc - Replace current source information with new such.
381 /// Avoid using this, the constructor argument is preferable.
383 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
385 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
386 /// fewer operand than it started with.
388 void RemoveOperand(unsigned i);
390 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
391 /// This function should be used only occasionally. The setMemRefs function
392 /// is the primary method for setting up a MachineInstr's MemRefs list.
393 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
395 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
396 /// list. This does not transfer ownership.
397 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
398 MemRefs = NewMemRefs;
399 MemRefsEnd = NewMemRefsEnd;
403 /// getRegInfo - If this instruction is embedded into a MachineFunction,
404 /// return the MachineRegisterInfo object for the current function, otherwise
406 MachineRegisterInfo *getRegInfo();
408 /// addImplicitDefUseOperands - Add all implicit def and use operands to
409 /// this instruction.
410 void addImplicitDefUseOperands();
412 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
413 /// this instruction from their respective use lists. This requires that the
414 /// operands already be on their use lists.
415 void RemoveRegOperandsFromUseLists();
417 /// AddRegOperandsToUseLists - Add all of the register operands in
418 /// this instruction from their respective use lists. This requires that the
419 /// operands not be on their use lists yet.
420 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
423 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
424 /// MachineInstr* by *value* of the instruction rather than by pointer value.
425 /// The hashing and equality testing functions ignore definitions so this is
426 /// useful for CSE, etc.
427 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
428 static inline MachineInstr *getEmptyKey() {
432 static inline MachineInstr *getTombstoneKey() {
433 return reinterpret_cast<MachineInstr*>(-1);
436 static unsigned getHashValue(const MachineInstr* const &MI);
438 static bool isEqual(const MachineInstr* const &LHS,
439 const MachineInstr* const &RHS) {
440 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
441 LHS == getEmptyKey() || LHS == getTombstoneKey())
443 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
447 //===----------------------------------------------------------------------===//
450 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
455 } // End llvm namespace