1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
55 const TargetInstrDesc *TID; // Instruction descriptor.
56 unsigned short NumImplicitOps; // Number of implicit operands (which
57 // are determined at construction time).
59 unsigned short AsmPrinterFlags; // Various bits of information used by
60 // the AsmPrinter to emit helpful
61 // comments. This is *not* semantic
62 // information. Do not use this for
63 // anything other than to convey comment
64 // information to AsmPrinter.
66 std::vector<MachineOperand> Operands; // the operands
67 mmo_iterator MemRefs; // information on memory references
68 mmo_iterator MemRefsEnd;
69 MachineBasicBlock *Parent; // Pointer to the owning basic block.
70 DebugLoc debugLoc; // Source line information.
72 // OperandComplete - Return true if it's illegal to add a new operand
73 bool OperandsComplete() const;
75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
78 // Intrusive list support
79 friend struct ilist_traits<MachineInstr>;
80 friend struct ilist_traits<MachineBasicBlock>;
81 void setParent(MachineBasicBlock *P) { Parent = P; }
83 /// MachineInstr ctor - This constructor creates a copy of the given
84 /// MachineInstr in the given MachineFunction.
85 MachineInstr(MachineFunction &, const MachineInstr &);
87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
88 /// TID NULL and no operands.
91 // The next two constructors have DebugLoc and non-DebugLoc versions;
92 // over time, the non-DebugLoc versions should be phased out and eventually
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96 /// implicit operands. It reserves space for the number of operands specified
97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
101 /// the MachineInstr is created and added to the end of the specified basic
102 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (unsigned short)Flag;
142 /// getDebugLoc - Returns the debug location id of this MachineInstr.
144 DebugLoc getDebugLoc() const { return debugLoc; }
146 /// getDesc - Returns the target instruction descriptor of this
148 const TargetInstrDesc &getDesc() const { return *TID; }
150 /// getOpcode - Returns the opcode of this MachineInstr.
152 int getOpcode() const { return TID->Opcode; }
154 /// Access to explicit operands of the instruction.
156 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
158 const MachineOperand& getOperand(unsigned i) const {
159 assert(i < getNumOperands() && "getOperand() out of range!");
162 MachineOperand& getOperand(unsigned i) {
163 assert(i < getNumOperands() && "getOperand() out of range!");
167 /// getNumExplicitOperands - Returns the number of non-implicit operands.
169 unsigned getNumExplicitOperands() const;
171 /// Access to memory operands of the instruction
172 mmo_iterator memoperands_begin() const { return MemRefs; }
173 mmo_iterator memoperands_end() const { return MemRefsEnd; }
174 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
176 /// hasOneMemOperand - Return true if this instruction has exactly one
177 /// MachineMemOperand.
178 bool hasOneMemOperand() const {
179 return MemRefsEnd - MemRefs == 1;
183 CheckDefs, // Check all operands for equality
184 IgnoreDefs, // Ignore all definitions
185 IgnoreVRegDefs // Ignore virtual register definitions
188 /// isIdenticalTo - Return true if this instruction is identical to (same
189 /// opcode and same operands as) the specified instruction.
190 bool isIdenticalTo(const MachineInstr *Other,
191 MICheckType Check = CheckDefs) const;
193 /// removeFromParent - This method unlinks 'this' from the containing basic
194 /// block, and returns it, but does not delete it.
195 MachineInstr *removeFromParent();
197 /// eraseFromParent - This method unlinks 'this' from the containing basic
198 /// block and deletes it.
199 void eraseFromParent();
201 /// isLabel - Returns true if the MachineInstr represents a label.
203 bool isLabel() const {
204 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
205 getOpcode() == TargetOpcode::EH_LABEL ||
206 getOpcode() == TargetOpcode::GC_LABEL;
209 bool isPrologLabel() const {
210 return getOpcode() == TargetOpcode::PROLOG_LABEL;
212 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
213 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
214 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
216 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
217 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
218 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
219 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
220 bool isInsertSubreg() const {
221 return getOpcode() == TargetOpcode::INSERT_SUBREG;
223 bool isSubregToReg() const {
224 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
226 bool isRegSequence() const {
227 return getOpcode() == TargetOpcode::REG_SEQUENCE;
229 bool isCopy() const {
230 return getOpcode() == TargetOpcode::COPY;
233 /// isCopyLike - Return true if the instruction behaves like a copy.
234 /// This does not include native copy instructions.
235 bool isCopyLike() const {
236 return isCopy() || isSubregToReg();
239 /// isIdentityCopy - Return true is the instruction is an identity copy.
240 bool isIdentityCopy() const {
241 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
242 getOperand(0).getSubReg() == getOperand(1).getSubReg();
245 /// readsRegister - Return true if the MachineInstr reads the specified
246 /// register. If TargetRegisterInfo is passed, then it also checks if there
247 /// is a read of a super-register.
248 /// This does not count partial redefines of virtual registers as reads:
250 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
251 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
254 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
255 /// virtual register. Take into account that a partial define is a
256 /// read-modify-write operation.
257 bool readsVirtualRegister(unsigned Reg) const {
258 return readsWritesVirtualRegister(Reg).first;
261 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
262 /// indicating if this instruction reads or writes Reg. This also considers
264 /// If Ops is not null, all operand indices for Reg are added.
265 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
266 SmallVectorImpl<unsigned> *Ops = 0) const;
268 /// killsRegister - Return true if the MachineInstr kills the specified
269 /// register. If TargetRegisterInfo is passed, then it also checks if there is
270 /// a kill of a super-register.
271 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
272 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
275 /// definesRegister - Return true if the MachineInstr fully defines the
276 /// specified register. If TargetRegisterInfo is passed, then it also checks
277 /// if there is a def of a super-register.
278 /// NOTE: It's ignoring subreg indices on virtual registers.
279 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
280 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
283 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
284 /// or partially define) the specified register.
285 /// NOTE: It's ignoring subreg indices on virtual registers.
286 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
287 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
290 /// registerDefIsDead - Returns true if the register is dead in this machine
291 /// instruction. If TargetRegisterInfo is passed, then it also checks
292 /// if there is a dead def of a super-register.
293 bool registerDefIsDead(unsigned Reg,
294 const TargetRegisterInfo *TRI = NULL) const {
295 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
298 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
299 /// the specific register or -1 if it is not found. It further tightens
300 /// the search criteria to a use that kills the register if isKill is true.
301 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
302 const TargetRegisterInfo *TRI = NULL) const;
304 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
305 /// a pointer to the MachineOperand rather than an index.
306 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
307 const TargetRegisterInfo *TRI = NULL) {
308 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
309 return (Idx == -1) ? NULL : &getOperand(Idx);
312 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
313 /// the specified register or -1 if it is not found. If isDead is true, defs
314 /// that are not dead are skipped. If Overlap is true, then it also looks for
315 /// defs that merely overlap the specified register. If TargetRegisterInfo is
316 /// non-null, then it also checks if there is a def of a super-register.
317 int findRegisterDefOperandIdx(unsigned Reg,
318 bool isDead = false, bool Overlap = false,
319 const TargetRegisterInfo *TRI = NULL) const;
321 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
322 /// a pointer to the MachineOperand rather than an index.
323 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
324 const TargetRegisterInfo *TRI = NULL) {
325 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
326 return (Idx == -1) ? NULL : &getOperand(Idx);
329 /// findFirstPredOperandIdx() - Find the index of the first operand in the
330 /// operand list that is used to represent the predicate. It returns -1 if
332 int findFirstPredOperandIdx() const;
334 /// isRegTiedToUseOperand - Given the index of a register def operand,
335 /// check if the register def is tied to a source operand, due to either
336 /// two-address elimination or inline assembly constraints. Returns the
337 /// first tied use operand index by reference is UseOpIdx is not null.
338 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
340 /// isRegTiedToDefOperand - Return true if the use operand of the specified
341 /// index is tied to an def operand. It also returns the def operand index by
342 /// reference if DefOpIdx is not null.
343 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
345 /// clearKillInfo - Clears kill flags on all operands.
347 void clearKillInfo();
349 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
351 void copyKillDeadInfo(const MachineInstr *MI);
353 /// copyPredicates - Copies predicate operand(s) from MI.
354 void copyPredicates(const MachineInstr *MI);
356 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
357 /// properly composing subreg indices where necessary.
358 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
359 const TargetRegisterInfo &RegInfo);
361 /// addRegisterKilled - We have determined MI kills a register. Look for the
362 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
363 /// add a implicit operand if it's not found. Returns true if the operand
364 /// exists / is added.
365 bool addRegisterKilled(unsigned IncomingReg,
366 const TargetRegisterInfo *RegInfo,
367 bool AddIfNotFound = false);
369 /// addRegisterDead - We have determined MI defined a register without a use.
370 /// Look for the operand that defines it and mark it as IsDead. If
371 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
372 /// true if the operand exists / is added.
373 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
374 bool AddIfNotFound = false);
376 /// addRegisterDefined - We have determined MI defines a register. Make sure
377 /// there is an operand defining Reg.
378 void addRegisterDefined(unsigned IncomingReg,
379 const TargetRegisterInfo *RegInfo = 0);
381 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
382 /// except those in the UsedRegs list.
383 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
384 const TargetRegisterInfo &TRI);
386 /// isSafeToMove - Return true if it is safe to move this instruction. If
387 /// SawStore is set to true, it means that there is a store (or call) between
388 /// the instruction's location and its intended destination.
389 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
390 bool &SawStore) const;
392 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
393 /// instruction which defined the specified register instead of copying it.
394 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
395 unsigned DstReg) const;
397 /// hasVolatileMemoryRef - Return true if this instruction may have a
398 /// volatile memory reference, or if the information describing the
399 /// memory reference is not available. Return false if it is known to
400 /// have no volatile memory references.
401 bool hasVolatileMemoryRef() const;
403 /// isInvariantLoad - Return true if this instruction is loading from a
404 /// location whose value is invariant across the function. For example,
405 /// loading a value from the constant pool or from the argument area of
406 /// a function if it does not change. This should only return true of *all*
407 /// loads the instruction does are invariant (if it does multiple loads).
408 bool isInvariantLoad(AliasAnalysis *AA) const;
410 /// isConstantValuePHI - If the specified instruction is a PHI that always
411 /// merges together the same virtual register, return the register, otherwise
413 unsigned isConstantValuePHI() const;
415 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
417 bool allDefsAreDead() const;
419 /// copyImplicitOps - Copy implicit register operands from specified
420 /// instruction to this instruction.
421 void copyImplicitOps(const MachineInstr *MI);
426 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
429 //===--------------------------------------------------------------------===//
430 // Accessors used to build up machine instructions.
432 /// addOperand - Add the specified operand to the instruction. If it is an
433 /// implicit operand, it is added to the end of the operand list. If it is
434 /// an explicit operand it is added at the end of the explicit operand list
435 /// (before the first implicit operand).
436 void addOperand(const MachineOperand &Op);
438 /// setDesc - Replace the instruction descriptor (thus opcode) of
439 /// the current instruction with a new one.
441 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
443 /// setDebugLoc - Replace current source information with new such.
444 /// Avoid using this, the constructor argument is preferable.
446 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
448 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
449 /// fewer operand than it started with.
451 void RemoveOperand(unsigned i);
453 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
454 /// This function should be used only occasionally. The setMemRefs function
455 /// is the primary method for setting up a MachineInstr's MemRefs list.
456 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
458 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
459 /// list. This does not transfer ownership.
460 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
461 MemRefs = NewMemRefs;
462 MemRefsEnd = NewMemRefsEnd;
466 /// getRegInfo - If this instruction is embedded into a MachineFunction,
467 /// return the MachineRegisterInfo object for the current function, otherwise
469 MachineRegisterInfo *getRegInfo();
471 /// addImplicitDefUseOperands - Add all implicit def and use operands to
472 /// this instruction.
473 void addImplicitDefUseOperands();
475 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
476 /// this instruction from their respective use lists. This requires that the
477 /// operands already be on their use lists.
478 void RemoveRegOperandsFromUseLists();
480 /// AddRegOperandsToUseLists - Add all of the register operands in
481 /// this instruction from their respective use lists. This requires that the
482 /// operands not be on their use lists yet.
483 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
486 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
487 /// MachineInstr* by *value* of the instruction rather than by pointer value.
488 /// The hashing and equality testing functions ignore definitions so this is
489 /// useful for CSE, etc.
490 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
491 static inline MachineInstr *getEmptyKey() {
495 static inline MachineInstr *getTombstoneKey() {
496 return reinterpret_cast<MachineInstr*>(-1);
499 static unsigned getHashValue(const MachineInstr* const &MI);
501 static bool isEqual(const MachineInstr* const &LHS,
502 const MachineInstr* const &RHS) {
503 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
504 LHS == getEmptyKey() || LHS == getTombstoneKey())
506 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
510 //===----------------------------------------------------------------------===//
513 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
518 } // End llvm namespace