1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
20 typedef int OpCodeMask;
21 typedef int InstrSchedClass;
23 //---------------------------------------------------------------------------
24 // class MachineOperand
27 // Representation of each machine instruction operand.
28 // This class is designed so that you can allocate a vector of operands
29 // first and initialize each one later.
31 // E.g, for this VM instruction:
32 // ptr = alloca type, numElements
33 // we generate 2 machine instructions on the SPARC:
35 // mul Constant, Numelements -> Reg
36 // add %sp, Reg -> Ptr
38 // Each instruction has 3 operands, listed above. Of those:
39 // - Reg, NumElements, and Ptr are of operand type MO_Register.
40 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
42 // For the register operands, the virtual register type is as follows:
44 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
45 // MachineInstr* minstr will point to the instruction that computes reg.
47 // - %sp will be of virtual register type MO_MachineReg.
48 // The field regNum identifies the machine register.
50 // - NumElements will be of virtual register type MO_VirtualReg.
51 // The field Value* value identifies the value.
53 // - Ptr will also be of virtual register type MO_VirtualReg.
54 // Again, the field Value* value identifies the value.
56 //---------------------------------------------------------------------------
59 class MachineOperand {
61 enum MachineOperandType {
62 MO_VirtualRegister, // virtual register for *value
63 MO_MachineRegister, // pre-assigned machine register `regNum'
71 // Bit fields of the flags variable used for different operand properties
72 static const char DEFFLAG = 0x1; // this is a def of the operand
73 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
74 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
75 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
76 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
77 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
81 Value* value; // BasicBlockVal for a label operand.
82 // ConstantVal for a non-address immediate.
83 // Virtual register for an SSA operand,
84 // including hidden operands required for
85 // the generated machine code.
86 int64_t immedVal; // constant value for an explicit constant
89 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
90 char flags; // see bit field definitions above
91 int regNum; // register number for an explicit register
92 // will be set for a value after reg allocation
94 /*ctor*/ MachineOperand ();
95 /*ctor*/ MachineOperand (MachineOperandType operandType,
97 /*copy ctor*/ MachineOperand (const MachineOperand&);
98 /*dtor*/ ~MachineOperand () {}
100 // Accessor methods. Caller is responsible for checking the
101 // operand type before invoking the corresponding accessor.
103 inline MachineOperandType getOperandType() const {
106 inline Value* getVRegValue () const {
107 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
108 opType == MO_PCRelativeDisp);
111 inline Value* getVRegValueOrNull() const {
112 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
113 opType == MO_PCRelativeDisp)? value : NULL;
115 inline int getMachineRegNum() const {
116 assert(opType == MO_MachineRegister);
119 inline int64_t getImmedValue () const {
120 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
123 inline bool opIsDef () const {
124 return flags & DEFFLAG;
126 inline bool opIsDefAndUse () const {
127 return flags & DEFUSEFLAG;
129 inline bool opHiBits32 () const {
130 return flags & HIFLAG32;
132 inline bool opLoBits32 () const {
133 return flags & LOFLAG32;
135 inline bool opHiBits64 () const {
136 return flags & HIFLAG64;
138 inline bool opLoBits64 () const {
139 return flags & LOFLAG64;
142 // used to check if a machine register has been allocated to this operand
143 inline bool hasAllocatedReg() const {
144 return (regNum >= 0 &&
145 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
146 opType == MO_MachineRegister));
149 // used to get the reg number if when one is allocated
150 inline int getAllocatedRegNum() const {
151 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
152 opType == MO_MachineRegister);
158 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
161 // These functions are provided so that a vector of operands can be
162 // statically allocated and individual ones can be initialized later.
163 // Give class MachineInstr access to these functions.
165 void Initialize (MachineOperandType operandType,
167 void InitializeConst (MachineOperandType operandType,
169 void InitializeReg (int regNum,
172 // Construction methods needed for fine-grain control.
173 // These must be accessed via coresponding methods in MachineInstr.
174 void markDef() { flags |= DEFFLAG; }
175 void markDefAndUse() { flags |= DEFUSEFLAG; }
176 void markHi32() { flags |= HIFLAG32; }
177 void markLo32() { flags |= LOFLAG32; }
178 void markHi64() { flags |= HIFLAG64; }
179 void markLo64() { flags |= LOFLAG64; }
181 // Replaces the Value with its corresponding physical register after
182 // register allocation is complete
183 void setRegForValue(int reg) {
184 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
185 opType == MO_MachineRegister);
189 friend class MachineInstr;
194 MachineOperand::MachineOperand()
195 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1)
199 MachineOperand::MachineOperand(MachineOperandType operandType,
201 : immedVal(0), opType(operandType), flags(0), regNum(-1)
205 MachineOperand::MachineOperand(const MachineOperand& mo)
206 : opType(mo.opType), flags(mo.flags)
209 case MO_VirtualRegister:
210 case MO_CCRegister: value = mo.value; break;
211 case MO_MachineRegister: regNum = mo.regNum; break;
212 case MO_SignExtendedImmed:
213 case MO_UnextendedImmed:
214 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
220 MachineOperand::Initialize(MachineOperandType operandType,
223 opType = operandType;
230 MachineOperand::InitializeConst(MachineOperandType operandType,
233 opType = operandType;
241 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
243 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
245 regNum = (int) _regNum;
250 //---------------------------------------------------------------------------
251 // class MachineInstr
254 // Representation of each machine instruction.
256 // MachineOpCode must be an enum, defined separately for each target.
257 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
259 // opCodeMask is used to record variants of an instruction.
260 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
261 // ANNUL: if 1: Annul delay slot instruction.
262 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
263 // Instead of creating 4 different opcodes for BNZ, we create a single
264 // opcode and set bits in opCodeMask for each of these flags.
266 // There are 2 kinds of operands:
268 // (1) Explicit operands of the machine instruction in vector operands[]
270 // (2) "Implicit operands" are values implicitly used or defined by the
271 // machine instruction, such as arguments to a CALL, return value of
272 // a CALL (if any), and return value of a RETURN.
273 //---------------------------------------------------------------------------
275 class MachineInstr : public Annotable, // MachineInstrs are annotable
276 public NonCopyable { // Disable copy operations
277 MachineOpCode opCode; // the opcode
278 OpCodeMask opCodeMask; // extra bits for variants of an opcode
279 std::vector<MachineOperand> operands; // the operands
283 bool isDef, isDefAndUse;
285 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
288 // implicitRefs - Values implicitly referenced by this machine instruction
290 std::vector<ImplicitRef> implicitRefs;
292 // regsUsed - all machine registers used for this instruction, including regs
293 // used to save values across the instruction. This is a bitset of registers.
294 std::vector<bool> regsUsed;
296 /*ctor*/ MachineInstr (MachineOpCode _opCode,
297 OpCodeMask _opCodeMask = 0x0);
298 /*ctor*/ MachineInstr (MachineOpCode _opCode,
299 unsigned numOperands,
300 OpCodeMask _opCodeMask = 0x0);
301 inline ~MachineInstr () {}
304 // Support to rewrite a machine instruction in place: for now, simply
305 // replace() and then set new operands with Set.*Operand methods below.
307 void replace (MachineOpCode _opCode,
308 unsigned numOperands,
309 OpCodeMask _opCodeMask = 0x0);
312 // The op code. Note that MachineOpCode is a target-specific type.
314 const MachineOpCode getOpCode () const { return opCode; }
317 // Information about explicit operands of the instruction
319 unsigned int getNumOperands () const { return operands.size(); }
321 bool operandIsDefined(unsigned i) const;
322 bool operandIsDefinedAndUsed(unsigned i) const;
324 const MachineOperand& getOperand (unsigned i) const;
325 MachineOperand& getOperand (unsigned i);
328 // Information about implicit operands of the instruction
330 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
332 bool implicitRefIsDefined(unsigned i) const;
333 bool implicitRefIsDefinedAndUsed(unsigned i) const;
335 const Value* getImplicitRef (unsigned i) const;
336 Value* getImplicitRef (unsigned i);
339 // Information about registers used in this instruction
341 const std::vector<bool> &getRegsUsed () const { return regsUsed; }
343 // insertUsedReg - Add a register to the Used registers set...
344 void insertUsedReg(unsigned Reg) {
345 if (Reg >= regsUsed.size())
346 regsUsed.resize(Reg+1);
347 regsUsed[Reg] = true;
354 friend std::ostream& operator<< (std::ostream& os,
355 const MachineInstr& minstr);
358 // Define iterators to access the Value operands of the Machine Instruction.
359 // begin() and end() are defined to produce these iterators...
361 template<class _MI, class _V> class ValOpIterator;
362 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
363 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
366 // Access to set the operands when building the machine instruction
368 void SetMachineOperandVal(unsigned i,
369 MachineOperand::MachineOperandType
373 bool isDefAndUse=false);
374 void SetMachineOperandConst(unsigned i,
375 MachineOperand::MachineOperandType
378 void SetMachineOperandReg(unsigned i, int regNum,
380 bool isDefAndUse=false,
383 void addImplicitRef (Value* val,
385 bool isDefAndUse=false);
387 void setImplicitRef (unsigned i,
390 bool isDefAndUse=false);
392 unsigned substituteValue (const Value* oldVal,
394 bool defsOnly = true);
396 void setOperandHi32 (unsigned i);
397 void setOperandLo32 (unsigned i);
398 void setOperandHi64 (unsigned i);
399 void setOperandLo64 (unsigned i);
402 // Replaces the Value for the operand with its allocated
403 // physical register after register allocation is complete.
405 void SetRegForOperand(unsigned i, int regNum);
408 // Iterator to enumerate machine operands.
410 template<class MITy, class VTy>
411 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
415 inline void skipToNextVal() {
416 while (i < MI->getNumOperands() &&
417 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
418 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
419 && MI->getOperand(i).getVRegValue() != 0))
423 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
428 typedef ValOpIterator<MITy, VTy> _Self;
430 inline VTy operator*() const {
431 return MI->getOperand(i).getVRegValue();
434 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
435 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
437 inline VTy operator->() const { return operator*(); }
439 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
440 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
442 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
443 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
445 inline bool operator==(const _Self &y) const {
448 inline bool operator!=(const _Self &y) const {
449 return !operator==(y);
452 static _Self begin(MITy MI) {
455 static _Self end(MITy MI) {
456 return _Self(MI, MI->getNumOperands());
460 // define begin() and end()
461 val_op_iterator begin() { return val_op_iterator::begin(this); }
462 val_op_iterator end() { return val_op_iterator::end(this); }
464 const_val_op_iterator begin() const {
465 return const_val_op_iterator::begin(this);
467 const_val_op_iterator end() const {
468 return const_val_op_iterator::end(this);
473 inline MachineOperand&
474 MachineInstr::getOperand(unsigned int i)
476 assert(i < operands.size() && "getOperand() out of range!");
480 inline const MachineOperand&
481 MachineInstr::getOperand(unsigned int i) const
483 assert(i < operands.size() && "getOperand() out of range!");
488 MachineInstr::operandIsDefined(unsigned int i) const
490 return getOperand(i).opIsDef();
494 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
496 return getOperand(i).opIsDefAndUse();
500 MachineInstr::implicitRefIsDefined(unsigned i) const
502 assert(i < implicitRefs.size() && "operand out of range!");
503 return implicitRefs[i].isDef;
507 MachineInstr::implicitRefIsDefinedAndUsed(unsigned i) const
509 assert(i < implicitRefs.size() && "operand out of range!");
510 return implicitRefs[i].isDefAndUse;
514 MachineInstr::getImplicitRef(unsigned i) const
516 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
517 return implicitRefs[i].Val;
521 MachineInstr::getImplicitRef(unsigned i)
523 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
524 return implicitRefs[i].Val;
528 MachineInstr::addImplicitRef(Value* val,
531 implicitRefs.push_back(ImplicitRef(val, isDef, isDefAndUse));
535 MachineInstr::setImplicitRef(unsigned int i,
540 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
541 implicitRefs[i].Val = val;
542 implicitRefs[i].isDef = isDef;
543 implicitRefs[i].isDefAndUse = isDefAndUse;
547 MachineInstr::setOperandHi32(unsigned i)
549 operands[i].markHi32();
553 MachineInstr::setOperandLo32(unsigned i)
555 operands[i].markLo32();
559 MachineInstr::setOperandHi64(unsigned i)
561 operands[i].markHi64();
565 MachineInstr::setOperandLo64(unsigned i)
567 operands[i].markLo64();
571 //---------------------------------------------------------------------------
573 //---------------------------------------------------------------------------
575 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
577 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
579 void PrintMachineInstructions(const Function *F);