1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "Support/Annotation.h"
21 #include "Support/iterator"
27 class MachineBasicBlock;
31 typedef int MachineOpCode;
33 //===----------------------------------------------------------------------===//
34 /// Special flags on instructions that modify the opcode.
35 /// These flags are unused for now, but having them enforces that some
36 /// changes will be needed if they are used.
38 enum MachineOpCodeFlags {
39 AnnulFlag, /// 1 if annul bit is set on a branch
40 PredTakenFlag, /// 1 if branch should be predicted taken
41 PredNotTakenFlag /// 1 if branch should be predicted not taken
44 //===----------------------------------------------------------------------===//
45 /// MOTy - MachineOperandType - This namespace contains an enum that describes
46 /// how the machine operand is used by the instruction: is it read, defined, or
47 /// both? Note that the MachineInstr/Operator class currently uses bool
48 /// arguments to represent this information instead of an enum. Eventually this
49 /// should change over to use this _easier to read_ representation instead.
53 Use, /// This machine operand is only read by the instruction
54 Def, /// This machine operand is only written by the instruction
55 UseAndDef /// This machine operand is read AND written
59 //===----------------------------------------------------------------------===//
60 // class MachineOperand
63 // Representation of each machine instruction operand.
64 // This class is designed so that you can allocate a vector of operands
65 // first and initialize each one later.
67 // E.g, for this VM instruction:
68 // ptr = alloca type, numElements
69 // we generate 2 machine instructions on the SPARC:
71 // mul Constant, Numelements -> Reg
72 // add %sp, Reg -> Ptr
74 // Each instruction has 3 operands, listed above. Of those:
75 // - Reg, NumElements, and Ptr are of operand type MO_Register.
76 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
78 // For the register operands, the virtual register type is as follows:
80 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
81 // MachineInstr* minstr will point to the instruction that computes reg.
83 // - %sp will be of virtual register type MO_MachineReg.
84 // The field regNum identifies the machine register.
86 // - NumElements will be of virtual register type MO_VirtualReg.
87 // The field Value* value identifies the value.
89 // - Ptr will also be of virtual register type MO_VirtualReg.
90 // Again, the field Value* value identifies the value.
92 //===----------------------------------------------------------------------===//
94 struct MachineOperand {
95 enum MachineOperandType {
96 MO_VirtualRegister, // virtual register for *value
97 MO_MachineRegister, // pre-assigned machine register `regNum'
102 MO_MachineBasicBlock, // MachineBasicBlock reference
103 MO_FrameIndex, // Abstract Stack Frame Index
104 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
105 MO_ExternalSymbol, // Name of external global symbol
106 MO_GlobalAddress, // Address of a global value
110 // Bit fields of the flags variable used for different operand properties
112 DEFFLAG = 0x01, // this is a def of the operand
113 USEFLAG = 0x02, // this is a use of the operand
114 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
115 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
116 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
117 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
118 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
123 Value* value; // BasicBlockVal for a label operand.
124 // ConstantVal for a non-address immediate.
125 // Virtual register for an SSA operand,
126 // including hidden operands required for
127 // the generated machine code.
128 // LLVM global for MO_GlobalAddress.
130 int64_t immedVal; // Constant value for an explicit constant
132 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
133 std::string *SymbolName; // For MO_ExternalSymbol type
136 char flags; // see bit field definitions above
137 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
138 int regNum; // register number for an explicit register
139 // will be set for a value after reg allocation
144 opType(MO_VirtualRegister),
147 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
153 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
158 case MOTy::Use: flags = USEFLAG; break;
159 case MOTy::Def: flags = DEFFLAG; break;
160 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
161 default: assert(0 && "Invalid value for UseTy!");
165 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
166 bool isPCRelative = false)
167 : value(V), opType(OpTy), regNum(-1) {
169 case MOTy::Use: flags = USEFLAG; break;
170 case MOTy::Def: flags = DEFFLAG; break;
171 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
172 default: assert(0 && "Invalid value for UseTy!");
174 if (isPCRelative) flags |= PCRELATIVE;
177 MachineOperand(MachineBasicBlock *mbb)
178 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
180 MachineOperand(const std::string &SymName, bool isPCRelative)
181 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
182 opType(MO_ExternalSymbol), regNum(-1) {}
185 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
189 if (isExternalSymbol())
190 SymbolName = new std::string(M.getSymbolName());
194 if (isExternalSymbol())
198 const MachineOperand &operator=(const MachineOperand &MO) {
199 if (isExternalSymbol()) // if old operand had a symbol name,
200 delete SymbolName; // release old memory
201 immedVal = MO.immedVal;
205 if (isExternalSymbol())
206 SymbolName = new std::string(MO.getSymbolName());
210 // Accessor methods. Caller is responsible for checking the
211 // operand type before invoking the corresponding accessor.
213 MachineOperandType getType() const { return opType; }
215 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
216 /// indicates whether this operand should be emitted as a PC relative value
217 /// instead of a global address. This is used for operands of the forms:
218 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
220 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
223 // This is to finally stop caring whether we have a virtual or machine
224 // register -- an easier interface is to simply call both virtual and machine
225 // registers essentially the same, yet be able to distinguish when
226 // necessary. Thus the instruction selector can just add registers without
227 // abandon, and the register allocator won't be confused.
228 bool isVirtualRegister() const {
229 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
230 && regNum >= MRegisterInfo::FirstVirtualRegister;
232 bool isPhysicalRegister() const {
233 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
234 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
236 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
237 bool isMachineRegister() const { return !isVirtualRegister(); }
238 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
239 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
240 bool isImmediate() const {
241 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
243 bool isFrameIndex() const { return opType == MO_FrameIndex; }
244 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
245 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
246 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
248 Value* getVRegValue() const {
249 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
253 Value* getVRegValueOrNull() const {
254 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
255 isPCRelativeDisp()) ? value : NULL;
257 int getMachineRegNum() const {
258 assert(opType == MO_MachineRegister);
261 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
262 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
264 MachineBasicBlock *getMachineBasicBlock() const {
265 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
268 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
269 unsigned getConstantPoolIndex() const {
270 assert(isConstantPoolIndex());
274 GlobalValue *getGlobal() const {
275 assert(isGlobalAddress());
276 return (GlobalValue*)value;
279 const std::string &getSymbolName() const {
280 assert(isExternalSymbol());
284 bool isUse () const { return flags & USEFLAG; }
285 MachineOperand& setUse () { flags |= USEFLAG; return *this; }
286 bool isDef () const { return flags & DEFFLAG; }
287 MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
288 bool isHiBits32 () const { return flags & HIFLAG32; }
289 bool isLoBits32 () const { return flags & LOFLAG32; }
290 bool isHiBits64 () const { return flags & HIFLAG64; }
291 bool isLoBits64 () const { return flags & LOFLAG64; }
293 // used to check if a machine register has been allocated to this operand
294 bool hasAllocatedReg() const {
295 return (regNum >= 0 &&
296 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
297 opType == MO_MachineRegister));
300 // used to get the reg number if when one is allocated
301 int getAllocatedRegNum() const {
302 assert(hasAllocatedReg());
306 // ********** TODO: get rid of this duplicate code! ***********
307 unsigned getReg() const {
308 return getAllocatedRegNum();
310 void setReg(unsigned Reg) {
311 assert(hasAllocatedReg() && "This operand cannot have a register number!");
315 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
319 // Construction methods needed for fine-grain control.
320 // These must be accessed via coresponding methods in MachineInstr.
321 void markHi32() { flags |= HIFLAG32; }
322 void markLo32() { flags |= LOFLAG32; }
323 void markHi64() { flags |= HIFLAG64; }
324 void markLo64() { flags |= LOFLAG64; }
326 // Replaces the Value with its corresponding physical register after
327 // register allocation is complete
328 void setRegForValue(int reg) {
329 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
330 opType == MO_MachineRegister);
334 friend class MachineInstr;
338 //===----------------------------------------------------------------------===//
339 // class MachineInstr
342 // Representation of each machine instruction.
344 // MachineOpCode must be an enum, defined separately for each target.
345 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
347 // There are 2 kinds of operands:
349 // (1) Explicit operands of the machine instruction in vector operands[]
351 // (2) "Implicit operands" are values implicitly used or defined by the
352 // machine instruction, such as arguments to a CALL, return value of
353 // a CALL (if any), and return value of a RETURN.
354 //===----------------------------------------------------------------------===//
357 int opCode; // the opcode
358 unsigned opCodeFlags; // flags modifying instrn behavior
359 std::vector<MachineOperand> operands; // the operands
360 unsigned numImplicitRefs; // number of implicit operands
362 // OperandComplete - Return true if it's illegal to add a new operand
363 bool OperandsComplete() const;
365 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
366 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
368 MachineInstr(int Opcode, unsigned numOperands);
370 /// MachineInstr ctor - This constructor only does a _reserve_ of the
371 /// operands, not a resize for them. It is expected that if you use this that
372 /// you call add* methods below to fill up the operands, instead of the Set
373 /// methods. Eventually, the "resizing" ctors will be phased out.
375 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
377 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
378 /// the MachineInstr is created and added to the end of the specified basic
381 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
386 const int getOpcode() const { return opCode; }
387 const int getOpCode() const { return opCode; }
391 unsigned getOpCodeFlags() const { return opCodeFlags; }
394 // Access to explicit operands of the instruction
396 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
398 const MachineOperand& getOperand(unsigned i) const {
399 assert(i < getNumOperands() && "getOperand() out of range!");
402 MachineOperand& getOperand(unsigned i) {
403 assert(i < getNumOperands() && "getOperand() out of range!");
408 // Access to explicit or implicit operands of the instruction
409 // This returns the i'th entry in the operand vector.
410 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
411 // depending on whether i < N or i >= N.
413 const MachineOperand& getExplOrImplOperand(unsigned i) const {
414 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
415 return (i < getNumOperands()? getOperand(i)
416 : getImplicitOp(i - getNumOperands()));
420 // Access to implicit operands of the instruction
422 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
424 MachineOperand& getImplicitOp(unsigned i) {
425 assert(i < numImplicitRefs && "implicit ref# out of range!");
426 return operands[i + operands.size() - numImplicitRefs];
428 const MachineOperand& getImplicitOp(unsigned i) const {
429 assert(i < numImplicitRefs && "implicit ref# out of range!");
430 return operands[i + operands.size() - numImplicitRefs];
433 Value* getImplicitRef(unsigned i) {
434 return getImplicitOp(i).getVRegValue();
436 const Value* getImplicitRef(unsigned i) const {
437 return getImplicitOp(i).getVRegValue();
440 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
442 addRegOperand(V, isDef, isDefAndUse);
444 void setImplicitRef(unsigned i, Value* V) {
445 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
446 SetMachineOperandVal(i + getNumOperands(),
447 MachineOperand::MO_VirtualRegister, V);
453 void print(std::ostream &OS, const TargetMachine &TM) const;
455 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
458 // Define iterators to access the Value operands of the Machine Instruction.
459 // Note that these iterators only enumerate the explicit operands.
460 // begin() and end() are defined to produce these iterators...
462 template<class _MI, class _V> class ValOpIterator;
463 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
464 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
467 //===--------------------------------------------------------------------===//
468 // Accessors to add operands when building up machine instructions
471 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
474 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
475 assert(!OperandsComplete() &&
476 "Trying to add an operand to a machine instr that is already done!");
477 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
478 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
481 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
482 bool isPCRelative = false) {
483 assert(!OperandsComplete() &&
484 "Trying to add an operand to a machine instr that is already done!");
485 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
489 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
490 assert(!OperandsComplete() &&
491 "Trying to add an operand to a machine instr that is already done!");
492 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
497 /// addRegOperand - Add a symbolic virtual register reference...
499 void addRegOperand(int reg, bool isDef) {
500 assert(!OperandsComplete() &&
501 "Trying to add an operand to a machine instr that is already done!");
502 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
503 isDef ? MOTy::Def : MOTy::Use));
506 /// addRegOperand - Add a symbolic virtual register reference...
508 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
509 assert(!OperandsComplete() &&
510 "Trying to add an operand to a machine instr that is already done!");
511 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
515 /// addPCDispOperand - Add a PC relative displacement operand to the MI
517 void addPCDispOperand(Value *V) {
518 assert(!OperandsComplete() &&
519 "Trying to add an operand to a machine instr that is already done!");
520 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
524 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
526 void addMachineRegOperand(int reg, bool isDef) {
527 assert(!OperandsComplete() &&
528 "Trying to add an operand to a machine instr that is already done!");
529 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
530 isDef ? MOTy::Def : MOTy::Use));
533 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
535 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
536 assert(!OperandsComplete() &&
537 "Trying to add an operand to a machine instr that is already done!");
538 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
542 /// addZeroExtImmOperand - Add a zero extended constant argument to the
543 /// machine instruction.
545 void addZeroExtImmOperand(int64_t intValue) {
546 assert(!OperandsComplete() &&
547 "Trying to add an operand to a machine instr that is already done!");
548 operands.push_back(MachineOperand(intValue,
549 MachineOperand::MO_UnextendedImmed));
552 /// addSignExtImmOperand - Add a zero extended constant argument to the
553 /// machine instruction.
555 void addSignExtImmOperand(int64_t intValue) {
556 assert(!OperandsComplete() &&
557 "Trying to add an operand to a machine instr that is already done!");
558 operands.push_back(MachineOperand(intValue,
559 MachineOperand::MO_SignExtendedImmed));
562 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
563 assert(!OperandsComplete() &&
564 "Trying to add an operand to a machine instr that is already done!");
565 operands.push_back(MachineOperand(MBB));
568 /// addFrameIndexOperand - Add an abstract frame index to the instruction
570 void addFrameIndexOperand(unsigned Idx) {
571 assert(!OperandsComplete() &&
572 "Trying to add an operand to a machine instr that is already done!");
573 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
576 /// addConstantPoolndexOperand - Add a constant pool object index to the
579 void addConstantPoolIndexOperand(unsigned I) {
580 assert(!OperandsComplete() &&
581 "Trying to add an operand to a machine instr that is already done!");
582 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
585 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
586 assert(!OperandsComplete() &&
587 "Trying to add an operand to a machine instr that is already done!");
588 operands.push_back(MachineOperand((Value*)GV,
589 MachineOperand::MO_GlobalAddress,
590 MOTy::Use, isPCRelative));
593 /// addExternalSymbolOperand - Add an external symbol operand to this instr
595 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
596 operands.push_back(MachineOperand(SymName, isPCRelative));
599 //===--------------------------------------------------------------------===//
600 // Accessors used to modify instructions in place.
602 // FIXME: Move this stuff to MachineOperand itself!
604 /// replace - Support to rewrite a machine instruction in place: for now,
605 /// simply replace() and then set new operands with Set.*Operand methods
608 void replace(int Opcode, unsigned numOperands);
610 /// setOpcode - Replace the opcode of the current instruction with a new one.
612 void setOpcode(unsigned Op) { opCode = Op; }
614 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
615 /// fewer operand than it started with.
617 void RemoveOperand(unsigned i) {
618 operands.erase(operands.begin()+i);
621 // Access to set the operands when building the machine instruction
623 void SetMachineOperandVal (unsigned i,
624 MachineOperand::MachineOperandType operandType,
627 void SetMachineOperandConst (unsigned i,
628 MachineOperand::MachineOperandType operandType,
631 void SetMachineOperandReg(unsigned i, int regNum);
634 unsigned substituteValue(const Value* oldVal, Value* newVal,
635 bool defsOnly, bool notDefsAndUses,
636 bool& someArgsWereIgnored);
638 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
639 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
640 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
641 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
644 // SetRegForOperand -
645 // SetRegForImplicitRef -
646 // Mark an explicit or implicit operand with its allocated physical register.
648 void SetRegForOperand(unsigned i, int regNum);
649 void SetRegForImplicitRef(unsigned i, int regNum);
652 // Iterator to enumerate machine operands.
654 template<class MITy, class VTy>
655 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
659 void skipToNextVal() {
660 while (i < MI->getNumOperands() &&
661 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
662 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
663 && MI->getOperand(i).getVRegValue() != 0))
667 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
672 typedef ValOpIterator<MITy, VTy> _Self;
674 inline VTy operator*() const {
675 return MI->getOperand(i).getVRegValue();
678 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
679 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
681 inline VTy operator->() const { return operator*(); }
683 inline bool isUse() const { return MI->getOperand(i).isUse(); }
684 inline bool isDef() const { return MI->getOperand(i).isDef(); }
686 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
687 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
689 inline bool operator==(const _Self &y) const {
692 inline bool operator!=(const _Self &y) const {
693 return !operator==(y);
696 static _Self begin(MITy MI) {
699 static _Self end(MITy MI) {
700 return _Self(MI, MI->getNumOperands());
704 // define begin() and end()
705 val_op_iterator begin() { return val_op_iterator::begin(this); }
706 val_op_iterator end() { return val_op_iterator::end(this); }
708 const_val_op_iterator begin() const {
709 return const_val_op_iterator::begin(this);
711 const_val_op_iterator end() const {
712 return const_val_op_iterator::end(this);
717 //===----------------------------------------------------------------------===//
720 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
721 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
722 void PrintMachineInstructions(const Function *F);
724 } // End llvm namespace