1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
15 #include <Support/hash_set>
18 //---------------------------------------------------------------------------
19 // class MachineOperand
22 // Representation of each machine instruction operand.
23 // This class is designed so that you can allocate a vector of operands
24 // first and initialize each one later.
26 // E.g, for this VM instruction:
27 // ptr = alloca type, numElements
28 // we generate 2 machine instructions on the SPARC:
30 // mul Constant, Numelements -> Reg
31 // add %sp, Reg -> Ptr
33 // Each instruction has 3 operands, listed above. Of those:
34 // - Reg, NumElements, and Ptr are of operand type MO_Register.
35 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
37 // For the register operands, the virtual register type is as follows:
39 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
40 // MachineInstr* minstr will point to the instruction that computes reg.
42 // - %sp will be of virtual register type MO_MachineReg.
43 // The field regNum identifies the machine register.
45 // - NumElements will be of virtual register type MO_VirtualReg.
46 // The field Value* value identifies the value.
48 // - Ptr will also be of virtual register type MO_VirtualReg.
49 // Again, the field Value* value identifies the value.
51 //---------------------------------------------------------------------------
54 class MachineOperand {
56 enum MachineOperandType {
57 MO_VirtualRegister, // virtual register for *value
58 MO_MachineRegister, // pre-assigned machine register `regNum'
66 // Bit fields of the flags variable used for different operand properties
67 static const char DEFFLAG = 0x1; // this is a def of the operand
68 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
69 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
70 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
71 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
72 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
76 Value* value; // BasicBlockVal for a label operand.
77 // ConstantVal for a non-address immediate.
78 // Virtual register for an SSA operand,
79 // including hidden operands required for
80 // the generated machine code.
81 int64_t immedVal; // constant value for an explicit constant
84 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
85 char flags; // see bit field definitions above
86 int regNum; // register number for an explicit register
87 // will be set for a value after reg allocation
89 /*ctor*/ MachineOperand ();
90 /*ctor*/ MachineOperand (MachineOperandType operandType,
92 /*copy ctor*/ MachineOperand (const MachineOperand&);
93 /*dtor*/ ~MachineOperand () {}
95 // Accessor methods. Caller is responsible for checking the
96 // operand type before invoking the corresponding accessor.
98 inline MachineOperandType getOperandType() const {
101 inline Value* getVRegValue () const {
102 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
103 opType == MO_PCRelativeDisp);
106 inline Value* getVRegValueOrNull() const {
107 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
108 opType == MO_PCRelativeDisp)? value : NULL;
110 inline int getMachineRegNum() const {
111 assert(opType == MO_MachineRegister);
114 inline int64_t getImmedValue () const {
115 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
118 inline bool opIsDef () const {
119 return flags & DEFFLAG;
121 inline bool opIsDefAndUse () const {
122 return flags & DEFUSEFLAG;
124 inline bool opHiBits32 () const {
125 return flags & HIFLAG32;
127 inline bool opLoBits32 () const {
128 return flags & LOFLAG32;
130 inline bool opHiBits64 () const {
131 return flags & HIFLAG64;
133 inline bool opLoBits64 () const {
134 return flags & LOFLAG64;
137 // used to check if a machine register has been allocated to this operand
138 inline bool hasAllocatedReg() const {
139 return (regNum >= 0 &&
140 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
141 opType == MO_MachineRegister));
144 // used to get the reg number if when one is allocated
145 inline int getAllocatedRegNum() const {
146 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
147 opType == MO_MachineRegister);
153 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
156 // These functions are provided so that a vector of operands can be
157 // statically allocated and individual ones can be initialized later.
158 // Give class MachineInstr access to these functions.
160 void Initialize (MachineOperandType operandType,
162 void InitializeConst (MachineOperandType operandType,
164 void InitializeReg (int regNum,
167 // Construction methods needed for fine-grain control.
168 // These must be accessed via coresponding methods in MachineInstr.
169 void markDef() { flags |= DEFFLAG; }
170 void markDefAndUse() { flags |= DEFUSEFLAG; }
171 void markHi32() { flags |= HIFLAG32; }
172 void markLo32() { flags |= LOFLAG32; }
173 void markHi64() { flags |= HIFLAG64; }
174 void markLo64() { flags |= LOFLAG64; }
176 // Replaces the Value with its corresponding physical register after
177 // register allocation is complete
178 void setRegForValue(int reg) {
179 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
180 opType == MO_MachineRegister);
184 friend class MachineInstr;
189 MachineOperand::MachineOperand()
190 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1)
194 MachineOperand::MachineOperand(MachineOperandType operandType,
196 : immedVal(0), opType(operandType), flags(0), regNum(-1)
200 MachineOperand::MachineOperand(const MachineOperand& mo)
201 : opType(mo.opType), flags(mo.flags)
204 case MO_VirtualRegister:
205 case MO_CCRegister: value = mo.value; break;
206 case MO_MachineRegister: regNum = mo.regNum; break;
207 case MO_SignExtendedImmed:
208 case MO_UnextendedImmed:
209 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
215 MachineOperand::Initialize(MachineOperandType operandType,
218 opType = operandType;
225 MachineOperand::InitializeConst(MachineOperandType operandType,
228 opType = operandType;
236 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
238 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
240 regNum = (int) _regNum;
245 //---------------------------------------------------------------------------
246 // class MachineInstr
249 // Representation of each machine instruction.
251 // MachineOpCode must be an enum, defined separately for each target.
252 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
254 // opCodeMask is used to record variants of an instruction.
255 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
256 // ANNUL: if 1: Annul delay slot instruction.
257 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
258 // Instead of creating 4 different opcodes for BNZ, we create a single
259 // opcode and set bits in opCodeMask for each of these flags.
261 // There are 2 kinds of operands:
263 // (1) Explicit operands of the machine instruction in vector operands[]
265 // (2) "Implicit operands" are values implicitly used or defined by the
266 // machine instruction, such as arguments to a CALL, return value of
267 // a CALL (if any), and return value of a RETURN.
268 //---------------------------------------------------------------------------
270 class MachineInstr : public Annotable, // MachineInstrs are annotable
271 public NonCopyable { // Disable copy operations
272 MachineOpCode opCode; // the opcode
273 OpCodeMask opCodeMask; // extra bits for variants of an opcode
274 std::vector<MachineOperand> operands; // the operands
275 std::vector<Value*> implicitRefs; // values implicitly referenced by this
276 std::vector<bool> implicitIsDef; // machine instruction (eg, call args)
277 std::vector<bool> implicitIsDefAndUse;
278 hash_set<int> regsUsed; // all machine registers used for this
279 // instruction, including regs used
280 // to save values across the instr.
282 /*ctor*/ MachineInstr (MachineOpCode _opCode,
283 OpCodeMask _opCodeMask = 0x0);
284 /*ctor*/ MachineInstr (MachineOpCode _opCode,
285 unsigned numOperands,
286 OpCodeMask _opCodeMask = 0x0);
287 inline ~MachineInstr () {}
290 // Support to rewrite a machine instruction in place: for now, simply
291 // replace() and then set new operands with Set.*Operand methods below.
293 void replace (MachineOpCode _opCode,
294 unsigned numOperands,
295 OpCodeMask _opCodeMask = 0x0);
298 // The op code. Note that MachineOpCode is a target-specific type.
300 const MachineOpCode getOpCode () const { return opCode; }
303 // Information about explicit operands of the instruction
305 unsigned int getNumOperands () const { return operands.size(); }
307 bool operandIsDefined(unsigned i) const;
308 bool operandIsDefinedAndUsed(unsigned i) const;
310 const MachineOperand& getOperand (unsigned i) const;
311 MachineOperand& getOperand (unsigned i);
314 // Information about implicit operands of the instruction
316 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
318 bool implicitRefIsDefined(unsigned i) const;
319 bool implicitRefIsDefinedAndUsed(unsigned i) const;
321 const Value* getImplicitRef (unsigned i) const;
322 Value* getImplicitRef (unsigned i);
325 // Information about registers used in this instruction
327 const hash_set<int>& getRegsUsed () const { return regsUsed; }
328 hash_set<int>& getRegsUsed () { return regsUsed; }
334 friend std::ostream& operator<< (std::ostream& os,
335 const MachineInstr& minstr);
338 // Define iterators to access the Value operands of the Machine Instruction.
339 // begin() and end() are defined to produce these iterators...
341 template<class _MI, class _V> class ValOpIterator;
342 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
343 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
346 // Access to set the operands when building the machine instruction
348 void SetMachineOperandVal(unsigned i,
349 MachineOperand::MachineOperandType
353 bool isDefAndUse=false);
354 void SetMachineOperandConst(unsigned i,
355 MachineOperand::MachineOperandType
358 void SetMachineOperandReg(unsigned i, int regNum,
360 bool isDefAndUse=false,
363 void addImplicitRef (Value* val,
365 bool isDefAndUse=false);
367 void setImplicitRef (unsigned i,
370 bool isDefAndUse=false);
372 unsigned substituteValue (const Value* oldVal,
374 bool defsOnly = true);
376 void setOperandHi32 (unsigned i);
377 void setOperandLo32 (unsigned i);
378 void setOperandHi64 (unsigned i);
379 void setOperandLo64 (unsigned i);
382 // Replaces the Value for the operand with its allocated
383 // physical register after register allocation is complete.
385 void SetRegForOperand(unsigned i, int regNum);
388 // Iterator to enumerate machine operands.
390 template<class MITy, class VTy>
391 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
395 inline void skipToNextVal() {
396 while (i < MI->getNumOperands() &&
397 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
398 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
399 && MI->getOperand(i).getVRegValue() != 0))
403 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
408 typedef ValOpIterator<MITy, VTy> _Self;
410 inline VTy operator*() const {
411 return MI->getOperand(i).getVRegValue();
414 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
415 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
417 inline VTy operator->() const { return operator*(); }
419 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
420 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
422 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
423 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
425 inline bool operator==(const _Self &y) const {
428 inline bool operator!=(const _Self &y) const {
429 return !operator==(y);
432 static _Self begin(MITy MI) {
435 static _Self end(MITy MI) {
436 return _Self(MI, MI->getNumOperands());
440 // define begin() and end()
441 val_op_iterator begin() { return val_op_iterator::begin(this); }
442 val_op_iterator end() { return val_op_iterator::end(this); }
444 const_val_op_iterator begin() const {
445 return const_val_op_iterator::begin(this);
447 const_val_op_iterator end() const {
448 return const_val_op_iterator::end(this);
453 inline MachineOperand&
454 MachineInstr::getOperand(unsigned int i)
456 assert(i < operands.size() && "getOperand() out of range!");
460 inline const MachineOperand&
461 MachineInstr::getOperand(unsigned int i) const
463 assert(i < operands.size() && "getOperand() out of range!");
468 MachineInstr::operandIsDefined(unsigned int i) const
470 return getOperand(i).opIsDef();
474 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
476 return getOperand(i).opIsDefAndUse();
480 MachineInstr::implicitRefIsDefined(unsigned int i) const
482 assert(i < implicitIsDef.size() && "operand out of range!");
483 return implicitIsDef[i];
487 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
489 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
490 return implicitIsDefAndUse[i];
494 MachineInstr::getImplicitRef(unsigned int i) const
496 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
497 return implicitRefs[i];
501 MachineInstr::getImplicitRef(unsigned int i)
503 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
504 return implicitRefs[i];
508 MachineInstr::addImplicitRef(Value* val,
512 implicitRefs.push_back(val);
513 implicitIsDef.push_back(isDef);
514 implicitIsDefAndUse.push_back(isDefAndUse);
518 MachineInstr::setImplicitRef(unsigned int i,
523 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
524 implicitRefs[i] = val;
525 implicitIsDef[i] = isDef;
526 implicitIsDefAndUse[i] = isDefAndUse;
530 MachineInstr::setOperandHi32(unsigned i)
532 operands[i].markHi32();
536 MachineInstr::setOperandLo32(unsigned i)
538 operands[i].markLo32();
542 MachineInstr::setOperandHi64(unsigned i)
544 operands[i].markHi64();
548 MachineInstr::setOperandLo64(unsigned i)
550 operands[i].markLo64();
554 //---------------------------------------------------------------------------
556 //---------------------------------------------------------------------------
558 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
560 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
562 void PrintMachineInstructions(const Function *F);