2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/Target/InstInfo.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
63 class MachineOperand {
65 enum MachineOperandType {
66 MO_VirtualRegister, // virtual register for *value
67 MO_MachineRegister, // pre-assigned machine register `regNum'
75 MachineOperandType opType;
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
84 unsigned int regNum; // register number for an explicit register
86 int64_t immedVal; // constant value for an explicit constant
89 bool isDef; // is this a defition for the value
90 // made public for faster access
93 /*ctor*/ MachineOperand ();
94 /*ctor*/ MachineOperand (MachineOperandType operandType,
96 /*copy ctor*/ MachineOperand (const MachineOperand&);
97 /*dtor*/ ~MachineOperand () {}
99 // Accessor methods. Caller is responsible for checking the
100 // operand type before invoking the corresponding accessor.
102 inline MachineOperandType getOperandType () const {
105 inline Value* getVRegValue () const {
106 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
107 opType == MO_PCRelativeDisp);
110 inline unsigned int getMachineRegNum() const {
111 assert(opType == MO_MachineRegister);
114 inline int64_t getImmedValue () const {
115 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
118 inline bool opIsDef () const {
123 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
127 // These functions are provided so that a vector of operands can be
128 // statically allocated and individual ones can be initialized later.
129 // Give class MachineInstr gets access to these functions.
131 void Initialize (MachineOperandType operandType,
133 void InitializeConst (MachineOperandType operandType,
135 void InitializeReg (unsigned int regNum);
137 friend class MachineInstr;
138 friend class ValOpIterator<const MachineInstr, const Value>;
139 friend class ValOpIterator< MachineInstr, Value>;
149 MachineOperand::MachineOperand()
150 : opType(MO_VirtualRegister),
158 MachineOperand::MachineOperand(MachineOperandType operandType,
160 : opType(operandType),
168 MachineOperand::MachineOperand(const MachineOperand& mo)
173 case MO_VirtualRegister:
174 case MO_CCRegister: value = mo.value; break;
175 case MO_MachineRegister: regNum = mo.regNum; break;
176 case MO_SignExtendedImmed:
177 case MO_UnextendedImmed:
178 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
184 MachineOperand::Initialize(MachineOperandType operandType,
187 opType = operandType;
192 MachineOperand::InitializeConst(MachineOperandType operandType,
195 opType = operandType;
201 MachineOperand::InitializeReg(unsigned int _regNum)
203 opType = MO_MachineRegister;
209 //---------------------------------------------------------------------------
210 // class MachineInstr
213 // Representation of each machine instruction.
215 // MachineOpCode must be an enum, defined separately for each target.
216 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
218 // opCodeMask is used to record variants of an instruction.
219 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
220 // ANNUL: if 1: Annul delay slot instruction.
221 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
222 // Instead of creating 4 different opcodes for BNZ, we create a single
223 // opcode and set bits in opCodeMask for each of these flags.
224 //---------------------------------------------------------------------------
226 class MachineInstr : public NonCopyable {
228 MachineOpCode opCode;
229 OpCodeMask opCodeMask; // extra bits for variants of an opcode
230 vector<MachineOperand> operands;
233 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
234 typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
237 /*ctor*/ MachineInstr (MachineOpCode _opCode,
238 OpCodeMask _opCodeMask = 0x0);
239 /*ctor*/ MachineInstr (MachineOpCode _opCode,
240 unsigned numOperands,
241 OpCodeMask _opCodeMask = 0x0);
242 inline ~MachineInstr () {}
244 const MachineOpCode getOpCode () const;
246 unsigned int getNumOperands () const;
248 const MachineOperand& getOperand (unsigned int i) const;
249 MachineOperand& getOperand (unsigned int i);
251 bool operandIsDefined(unsigned int i) const;
253 void dump (unsigned int indent = 0) const;
260 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
261 friend val_op_const_iterator;
262 friend val_op_iterator;
265 // Access to set the operands when building the machine instruction
266 void SetMachineOperand(unsigned int i,
267 MachineOperand::MachineOperandType operandType,
268 Value* _val, bool isDef=false);
269 void SetMachineOperand(unsigned int i,
270 MachineOperand::MachineOperandType operandType,
271 int64_t intValue, bool isDef=false);
272 void SetMachineOperand(unsigned int i,
277 inline const MachineOpCode
278 MachineInstr::getOpCode() const
284 MachineInstr::getNumOperands() const
286 return operands.size();
289 inline MachineOperand&
290 MachineInstr::getOperand(unsigned int i)
292 assert(i < operands.size() && "getOperand() out of range!");
296 inline const MachineOperand&
297 MachineInstr::getOperand(unsigned int i) const
299 assert(i < operands.size() && "getOperand() out of range!");
304 MachineInstr::operandIsDefined(unsigned int i) const
306 return getOperand(i).opIsDef();
310 template<class _MI, class _V>
311 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
317 inline void skipToNextVal() {
318 while (i < minstr->getNumOperands() &&
319 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
320 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
321 && minstr->operands[i].value != NULL))
326 typedef ValOpIterator<_MI, _V> _Self;
328 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
329 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
333 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
335 const MachineOperand & getMachineOperand() const { return minstr->getOperand(i); }
337 inline _V* operator->() const { return operator*(); }
338 // inline bool isDef () const { return (((int) i) == resultPos); }
340 inline bool isDef () const { return minstr->getOperand(i).isDef; }
341 inline bool done () const { return (i == minstr->getNumOperands()); }
343 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
344 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
348 //---------------------------------------------------------------------------
349 // class MachineCodeForVMInstr
352 // Representation of the sequence of machine instructions created
353 // for a single VM instruction. Additionally records any temporary
354 // "values" used as intermediate values in this sequence.
355 // Note that such values should be treated as pure SSA values with
356 // no interpretation of their operands (i.e., as a TmpInstruction object
357 // which actually represents such a value).
359 //---------------------------------------------------------------------------
361 class MachineCodeForVMInstr: public vector<MachineInstr*>
364 vector<Value*> tempVec;
367 /*ctor*/ MachineCodeForVMInstr () {}
368 /*ctor*/ ~MachineCodeForVMInstr ();
370 const vector<Value*>&
371 getTempValues () const { return tempVec; }
373 void addTempValue (Value* val)
374 { tempVec.push_back(val); }
376 // dropAllReferences() - This function drops all references within
377 // temporary (hidden) instructions created in implementing the original
378 // VM intruction. This ensures there are no remaining "uses" within
379 // these hidden instructions, before the values of a method are freed.
381 // Make this inline because it has to be called from class Instruction
382 // and inlining it avoids a serious circurality in link order.
383 inline void dropAllReferences() {
384 for (unsigned i=0, N=tempVec.size(); i < N; i++)
385 if (Instruction *I = tempVec[i]->castInstruction())
386 I->dropAllReferences();
391 MachineCodeForVMInstr::~MachineCodeForVMInstr()
393 // Free the Value objects created to hold intermediate values
394 for (unsigned i=0, N=tempVec.size(); i < N; i++)
397 // Free the MachineInstr objects allocated, if any.
398 for (unsigned i=0, N=this->size(); i < N; i++)
403 //---------------------------------------------------------------------------
404 // class MachineCodeForBasicBlock
407 // Representation of the sequence of machine instructions created
408 // for a basic block.
409 //---------------------------------------------------------------------------
412 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
414 typedef vector<MachineInstr*>::iterator iterator;
415 typedef vector<const MachineInstr*>::const_iterator const_iterator;
419 //---------------------------------------------------------------------------
420 // Target-independent utility routines for creating machine instructions
421 //---------------------------------------------------------------------------
424 //------------------------------------------------------------------------
425 // Function Set2OperandsFromInstr
426 // Function Set3OperandsFromInstr
428 // For the common case of 2- and 3-operand arithmetic/logical instructions,
429 // set the m/c instr. operands directly from the VM instruction's operands.
430 // Check whether the first or second operand is 0 and can use a dedicated
432 // Check whether the second operand should use an immediate field or register.
433 // (First and third operands are never immediates for such instructions.)
436 // canDiscardResult: Specifies that the result operand can be discarded
437 // by using the dedicated "0"
439 // op1position, op2position and resultPosition: Specify in which position
440 // in the machine instruction the 3 operands (arg1, arg2
441 // and result) should go.
443 // RETURN VALUE: unsigned int flags, where
444 // flags & 0x01 => operand 1 is constant and needs a register
445 // flags & 0x02 => operand 2 is constant and needs a register
446 //------------------------------------------------------------------------
448 void Set2OperandsFromInstr (MachineInstr* minstr,
449 InstructionNode* vmInstrNode,
450 const TargetMachine& targetMachine,
451 bool canDiscardResult = false,
453 int resultPosition = 1);
455 void Set3OperandsFromInstr (MachineInstr* minstr,
456 InstructionNode* vmInstrNode,
457 const TargetMachine& targetMachine,
458 bool canDiscardResult = false,
461 int resultPosition = 2);
463 MachineOperand::MachineOperandType
464 ChooseRegOrImmed(Value* val,
465 MachineOpCode opCode,
466 const TargetMachine& targetMachine,
468 unsigned int& getMachineRegNum,
469 int64_t& getImmedValue);
472 ostream& operator<<(ostream& os, const MachineInstr& minstr);
475 ostream& operator<<(ostream& os, const MachineOperand& mop);
478 void PrintMachineInstructions (const Method *method);
481 //**************************************************************************/