1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MRegisterInfo.h"
13 #include "Support/Annotation.h"
14 #include "Support/iterator"
19 class MachineBasicBlock;
23 typedef int MachineOpCode;
25 //===----------------------------------------------------------------------===//
26 /// Special flags on instructions that modify the opcode.
27 /// These flags are unused for now, but having them enforces that some
28 /// changes will be needed if they are used.
30 enum MachineOpCodeFlags {
31 AnnulFlag, /// 1 if annul bit is set on a branch
32 PredTakenFlag, /// 1 if branch should be predicted taken
33 PredNotTakenFlag /// 1 if branch should be predicted not taken
36 //===----------------------------------------------------------------------===//
37 /// MOTy - MachineOperandType - This namespace contains an enum that describes
38 /// how the machine operand is used by the instruction: is it read, defined, or
39 /// both? Note that the MachineInstr/Operator class currently uses bool
40 /// arguments to represent this information instead of an enum. Eventually this
41 /// should change over to use this _easier to read_ representation instead.
45 Use, /// This machine operand is only read by the instruction
46 Def, /// This machine operand is only written by the instruction
47 UseAndDef /// This machine operand is read AND written
51 //===----------------------------------------------------------------------===//
52 // class MachineOperand
55 // Representation of each machine instruction operand.
56 // This class is designed so that you can allocate a vector of operands
57 // first and initialize each one later.
59 // E.g, for this VM instruction:
60 // ptr = alloca type, numElements
61 // we generate 2 machine instructions on the SPARC:
63 // mul Constant, Numelements -> Reg
64 // add %sp, Reg -> Ptr
66 // Each instruction has 3 operands, listed above. Of those:
67 // - Reg, NumElements, and Ptr are of operand type MO_Register.
68 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
70 // For the register operands, the virtual register type is as follows:
72 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
73 // MachineInstr* minstr will point to the instruction that computes reg.
75 // - %sp will be of virtual register type MO_MachineReg.
76 // The field regNum identifies the machine register.
78 // - NumElements will be of virtual register type MO_VirtualReg.
79 // The field Value* value identifies the value.
81 // - Ptr will also be of virtual register type MO_VirtualReg.
82 // Again, the field Value* value identifies the value.
84 //===----------------------------------------------------------------------===//
86 struct MachineOperand {
87 enum MachineOperandType {
88 MO_VirtualRegister, // virtual register for *value
89 MO_MachineRegister, // pre-assigned machine register `regNum'
94 MO_MachineBasicBlock, // MachineBasicBlock reference
95 MO_FrameIndex, // Abstract Stack Frame Index
96 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
97 MO_ExternalSymbol, // Name of external global symbol
98 MO_GlobalAddress, // Address of a global value
102 // Bit fields of the flags variable used for different operand properties
104 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
105 DEFUSEFLAG = 0x02, // this is both a def and a use
106 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
107 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
108 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
109 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
110 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
117 Value* value; // BasicBlockVal for a label operand.
118 // ConstantVal for a non-address immediate.
119 // Virtual register for an SSA operand,
120 // including hidden operands required for
121 // the generated machine code.
122 // LLVM global for MO_GlobalAddress.
124 int64_t immedVal; // Constant value for an explicit constant
126 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
127 std::string *SymbolName; // For MO_ExternalSymbol type
130 char flags; // see bit field definitions above
131 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
132 int regNum; // register number for an explicit register
133 // will be set for a value after reg allocation
138 opType(MO_VirtualRegister),
141 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
147 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
152 case MOTy::Use: flags = 0; break;
153 case MOTy::Def: flags = DEFONLYFLAG; break;
154 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
155 default: assert(0 && "Invalid value for UseTy!");
159 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
160 bool isPCRelative = false)
161 : value(V), opType(OpTy), regNum(-1) {
163 case MOTy::Use: flags = 0; break;
164 case MOTy::Def: flags = DEFONLYFLAG; break;
165 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
166 default: assert(0 && "Invalid value for UseTy!");
168 if (isPCRelative) flags |= PCRELATIVE;
171 MachineOperand(MachineBasicBlock *mbb)
172 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
174 MachineOperand(const std::string &SymName, bool isPCRelative)
175 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
176 opType(MO_ExternalSymbol), regNum(-1) {}
179 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
183 if (isExternalSymbol())
184 SymbolName = new std::string(M.getSymbolName());
188 if (isExternalSymbol())
192 const MachineOperand &operator=(const MachineOperand &MO) {
193 immedVal = MO.immedVal;
197 if (isExternalSymbol())
198 SymbolName = new std::string(MO.getSymbolName());
202 // Accessor methods. Caller is responsible for checking the
203 // operand type before invoking the corresponding accessor.
205 MachineOperandType getType() const { return opType; }
207 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
208 /// indicates whether this operand should be emitted as a PC relative value
209 /// instead of a global address. This is used for operands of the forms:
210 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
212 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
215 // This is to finally stop caring whether we have a virtual or machine
216 // register -- an easier interface is to simply call both virtual and machine
217 // registers essentially the same, yet be able to distinguish when
218 // necessary. Thus the instruction selector can just add registers without
219 // abandon, and the register allocator won't be confused.
220 bool isVirtualRegister() const {
221 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
222 && regNum >= MRegisterInfo::FirstVirtualRegister;
224 bool isPhysicalRegister() const {
225 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
226 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
228 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
229 bool isMachineRegister() const { return !isVirtualRegister(); }
230 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
231 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
232 bool isImmediate() const {
233 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
235 bool isFrameIndex() const { return opType == MO_FrameIndex; }
236 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
237 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
238 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
240 Value* getVRegValue() const {
241 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
245 Value* getVRegValueOrNull() const {
246 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
247 isPCRelativeDisp()) ? value : NULL;
249 int getMachineRegNum() const {
250 assert(opType == MO_MachineRegister);
253 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
254 MachineBasicBlock *getMachineBasicBlock() const {
255 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
258 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
259 unsigned getConstantPoolIndex() const {
260 assert(isConstantPoolIndex());
264 GlobalValue *getGlobal() const {
265 assert(isGlobalAddress());
266 return (GlobalValue*)value;
269 const std::string &getSymbolName() const {
270 assert(isExternalSymbol());
274 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
275 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
276 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
277 bool opHiBits32 () const { return flags & HIFLAG32; }
278 bool opLoBits32 () const { return flags & LOFLAG32; }
279 bool opHiBits64 () const { return flags & HIFLAG64; }
280 bool opLoBits64 () const { return flags & LOFLAG64; }
282 // used to check if a machine register has been allocated to this operand
283 bool hasAllocatedReg() const {
284 return (regNum >= 0 &&
285 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
286 opType == MO_MachineRegister));
289 // used to get the reg number if when one is allocated
290 int getAllocatedRegNum() const {
291 assert(hasAllocatedReg());
295 // ********** TODO: get rid of this duplicate code! ***********
296 unsigned getReg() const {
297 return getAllocatedRegNum();
300 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
304 // Construction methods needed for fine-grain control.
305 // These must be accessed via coresponding methods in MachineInstr.
306 void markHi32() { flags |= HIFLAG32; }
307 void markLo32() { flags |= LOFLAG32; }
308 void markHi64() { flags |= HIFLAG64; }
309 void markLo64() { flags |= LOFLAG64; }
311 // Replaces the Value with its corresponding physical register after
312 // register allocation is complete
313 void setRegForValue(int reg) {
314 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
315 opType == MO_MachineRegister);
319 friend class MachineInstr;
323 //===----------------------------------------------------------------------===//
324 // class MachineInstr
327 // Representation of each machine instruction.
329 // MachineOpCode must be an enum, defined separately for each target.
330 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
332 // There are 2 kinds of operands:
334 // (1) Explicit operands of the machine instruction in vector operands[]
336 // (2) "Implicit operands" are values implicitly used or defined by the
337 // machine instruction, such as arguments to a CALL, return value of
338 // a CALL (if any), and return value of a RETURN.
339 //===----------------------------------------------------------------------===//
342 int opCode; // the opcode
343 unsigned opCodeFlags; // flags modifying instrn behavior
344 std::vector<MachineOperand> operands; // the operands
345 unsigned numImplicitRefs; // number of implicit operands
347 // regsUsed - all machine registers used for this instruction, including regs
348 // used to save values across the instruction. This is a bitset of registers.
349 std::set<int> regsUsed;
351 // OperandComplete - Return true if it's illegal to add a new operand
352 bool OperandsComplete() const;
354 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
355 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
357 MachineInstr(int Opcode, unsigned numOperands);
359 /// MachineInstr ctor - This constructor only does a _reserve_ of the
360 /// operands, not a resize for them. It is expected that if you use this that
361 /// you call add* methods below to fill up the operands, instead of the Set
362 /// methods. Eventually, the "resizing" ctors will be phased out.
364 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
366 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
367 /// the MachineInstr is created and added to the end of the specified basic
370 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
375 const int getOpcode() const { return opCode; }
376 const int getOpCode() const { return opCode; }
380 unsigned getOpCodeFlags() const { return opCodeFlags; }
383 // Access to explicit operands of the instruction
385 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
387 const MachineOperand& getOperand(unsigned i) const {
388 assert(i < getNumOperands() && "getOperand() out of range!");
391 MachineOperand& getOperand(unsigned i) {
392 assert(i < getNumOperands() && "getOperand() out of range!");
397 // Access to explicit or implicit operands of the instruction
398 // This returns the i'th entry in the operand vector.
399 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
400 // depending on whether i < N or i >= N.
402 const MachineOperand& getExplOrImplOperand(unsigned i) const {
403 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
404 return (i < getNumOperands()? getOperand(i)
405 : getImplicitOp(i - getNumOperands()));
409 // Access to implicit operands of the instruction
411 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
413 MachineOperand& getImplicitOp(unsigned i) {
414 assert(i < numImplicitRefs && "implicit ref# out of range!");
415 return operands[i + operands.size() - numImplicitRefs];
417 const MachineOperand& getImplicitOp(unsigned i) const {
418 assert(i < numImplicitRefs && "implicit ref# out of range!");
419 return operands[i + operands.size() - numImplicitRefs];
422 Value* getImplicitRef(unsigned i) {
423 return getImplicitOp(i).getVRegValue();
425 const Value* getImplicitRef(unsigned i) const {
426 return getImplicitOp(i).getVRegValue();
429 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
431 addRegOperand(V, isDef, isDefAndUse);
433 void setImplicitRef(unsigned i, Value* V, bool isDef=false,
434 bool isDefAndUse=false) {
435 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
436 SetMachineOperandVal(i + getNumOperands(),
437 MachineOperand::MO_VirtualRegister,
438 V, isDef, isDefAndUse);
442 // Information about registers used in this instruction.
444 const std::set<int> &getRegsUsed() const {
447 bool isRegUsed(int regNum) const {
448 return regsUsed.find(regNum) != regsUsed.end();
451 // insertusedreg - Add a register to the Used registers set...
452 void insertUsedReg(unsigned Reg) {
453 regsUsed.insert((int) Reg);
459 void print(std::ostream &OS, const TargetMachine &TM) const;
461 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
464 // Define iterators to access the Value operands of the Machine Instruction.
465 // Note that these iterators only enumerate the explicit operands.
466 // begin() and end() are defined to produce these iterators...
468 template<class _MI, class _V> class ValOpIterator;
469 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
470 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
473 //===--------------------------------------------------------------------===//
474 // Accessors to add operands when building up machine instructions
477 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
480 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
481 assert(!OperandsComplete() &&
482 "Trying to add an operand to a machine instr that is already done!");
483 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
484 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
487 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
488 bool isPCRelative = false) {
489 assert(!OperandsComplete() &&
490 "Trying to add an operand to a machine instr that is already done!");
491 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
495 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
496 assert(!OperandsComplete() &&
497 "Trying to add an operand to a machine instr that is already done!");
498 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
503 /// addRegOperand - Add a symbolic virtual register reference...
505 void addRegOperand(int reg, bool isDef) {
506 assert(!OperandsComplete() &&
507 "Trying to add an operand to a machine instr that is already done!");
508 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
509 isDef ? MOTy::Def : MOTy::Use));
512 /// addRegOperand - Add a symbolic virtual register reference...
514 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
515 assert(!OperandsComplete() &&
516 "Trying to add an operand to a machine instr that is already done!");
517 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
521 /// addPCDispOperand - Add a PC relative displacement operand to the MI
523 void addPCDispOperand(Value *V) {
524 assert(!OperandsComplete() &&
525 "Trying to add an operand to a machine instr that is already done!");
526 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
530 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
532 void addMachineRegOperand(int reg, bool isDef) {
533 assert(!OperandsComplete() &&
534 "Trying to add an operand to a machine instr that is already done!");
535 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
536 isDef ? MOTy::Def : MOTy::Use));
540 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
542 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
543 assert(!OperandsComplete() &&
544 "Trying to add an operand to a machine instr that is already done!");
545 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
550 /// addZeroExtImmOperand - Add a zero extended constant argument to the
551 /// machine instruction.
553 void addZeroExtImmOperand(int64_t intValue) {
554 assert(!OperandsComplete() &&
555 "Trying to add an operand to a machine instr that is already done!");
556 operands.push_back(MachineOperand(intValue,
557 MachineOperand::MO_UnextendedImmed));
560 /// addSignExtImmOperand - Add a zero extended constant argument to the
561 /// machine instruction.
563 void addSignExtImmOperand(int64_t intValue) {
564 assert(!OperandsComplete() &&
565 "Trying to add an operand to a machine instr that is already done!");
566 operands.push_back(MachineOperand(intValue,
567 MachineOperand::MO_SignExtendedImmed));
570 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
571 assert(!OperandsComplete() &&
572 "Trying to add an operand to a machine instr that is already done!");
573 operands.push_back(MachineOperand(MBB));
576 /// addFrameIndexOperand - Add an abstract frame index to the instruction
578 void addFrameIndexOperand(unsigned Idx) {
579 assert(!OperandsComplete() &&
580 "Trying to add an operand to a machine instr that is already done!");
581 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
584 /// addConstantPoolndexOperand - Add a constant pool object index to the
587 void addConstantPoolIndexOperand(unsigned I) {
588 assert(!OperandsComplete() &&
589 "Trying to add an operand to a machine instr that is already done!");
590 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
593 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
594 assert(!OperandsComplete() &&
595 "Trying to add an operand to a machine instr that is already done!");
596 operands.push_back(MachineOperand((Value*)GV,
597 MachineOperand::MO_GlobalAddress,
598 MOTy::Use, isPCRelative));
601 /// addExternalSymbolOperand - Add an external symbol operand to this instr
603 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
604 operands.push_back(MachineOperand(SymName, isPCRelative));
607 //===--------------------------------------------------------------------===//
608 // Accessors used to modify instructions in place.
610 // FIXME: Move this stuff to MachineOperand itself!
612 /// replace - Support to rewrite a machine instruction in place: for now,
613 /// simply replace() and then set new operands with Set.*Operand methods
616 void replace(int Opcode, unsigned numOperands);
618 /// setOpcode - Replace the opcode of the current instruction with a new one.
620 void setOpcode(unsigned Op) { opCode = Op; }
622 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
623 /// fewer operand than it started with.
625 void RemoveOperand(unsigned i) {
626 operands.erase(operands.begin()+i);
629 // Access to set the operands when building the machine instruction
631 void SetMachineOperandVal (unsigned i,
632 MachineOperand::MachineOperandType operandType,
635 bool isDefAndUse=false);
637 void SetMachineOperandConst (unsigned i,
638 MachineOperand::MachineOperandType operandType,
641 void SetMachineOperandReg (unsigned i,
646 unsigned substituteValue(const Value* oldVal, Value* newVal,
647 bool defsOnly = true);
649 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
650 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
651 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
652 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
655 // SetRegForOperand -
656 // SetRegForImplicitRef -
657 // Mark an explicit or implicit operand with its allocated physical register.
659 void SetRegForOperand(unsigned i, int regNum);
660 void SetRegForImplicitRef(unsigned i, int regNum);
663 // Iterator to enumerate machine operands.
665 template<class MITy, class VTy>
666 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
670 void skipToNextVal() {
671 while (i < MI->getNumOperands() &&
672 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
673 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
674 && MI->getOperand(i).getVRegValue() != 0))
678 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
683 typedef ValOpIterator<MITy, VTy> _Self;
685 inline VTy operator*() const {
686 return MI->getOperand(i).getVRegValue();
689 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
690 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
692 inline VTy operator->() const { return operator*(); }
694 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
695 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
696 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
698 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
699 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
701 inline bool operator==(const _Self &y) const {
704 inline bool operator!=(const _Self &y) const {
705 return !operator==(y);
708 static _Self begin(MITy MI) {
711 static _Self end(MITy MI) {
712 return _Self(MI, MI->getNumOperands());
716 // define begin() and end()
717 val_op_iterator begin() { return val_op_iterator::begin(this); }
718 val_op_iterator end() { return val_op_iterator::end(this); }
720 const_val_op_iterator begin() const {
721 return const_val_op_iterator::begin(this);
723 const_val_op_iterator end() const {
724 return const_val_op_iterator::end(this);
729 //===----------------------------------------------------------------------===//
732 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
733 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
734 void PrintMachineInstructions(const Function *F);