1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
15 #include <Support/hash_set>
19 //---------------------------------------------------------------------------
20 // class MachineOperand
23 // Representation of each machine instruction operand.
24 // This class is designed so that you can allocate a vector of operands
25 // first and initialize each one later.
27 // E.g, for this VM instruction:
28 // ptr = alloca type, numElements
29 // we generate 2 machine instructions on the SPARC:
31 // mul Constant, Numelements -> Reg
32 // add %sp, Reg -> Ptr
34 // Each instruction has 3 operands, listed above. Of those:
35 // - Reg, NumElements, and Ptr are of operand type MO_Register.
36 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
38 // For the register operands, the virtual register type is as follows:
40 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
41 // MachineInstr* minstr will point to the instruction that computes reg.
43 // - %sp will be of virtual register type MO_MachineReg.
44 // The field regNum identifies the machine register.
46 // - NumElements will be of virtual register type MO_VirtualReg.
47 // The field Value* value identifies the value.
49 // - Ptr will also be of virtual register type MO_VirtualReg.
50 // Again, the field Value* value identifies the value.
52 //---------------------------------------------------------------------------
55 class MachineOperand {
57 enum MachineOperandType {
58 MO_VirtualRegister, // virtual register for *value
59 MO_MachineRegister, // pre-assigned machine register `regNum'
67 // Bit fields of the flags variable used for different operand properties
68 static const char DEFFLAG = 0x1; // this is a def of the operand
69 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
70 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
71 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
72 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
73 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
76 MachineOperandType opType;
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 int regNum; // register number for an explicit register
88 // will be set for a value after reg allocation
89 char flags; // see bit field definitions above
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType() const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
106 opType == MO_PCRelativeDisp);
109 inline int getMachineRegNum() const {
110 assert(opType == MO_MachineRegister);
113 inline int64_t getImmedValue () const {
114 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
117 inline bool opIsDef () const {
118 return flags & DEFFLAG;
120 inline bool opIsDefAndUse () const {
121 return flags & DEFUSEFLAG;
123 inline bool opHiBits32 () const {
124 return flags & HIFLAG32;
126 inline bool opLoBits32 () const {
127 return flags & LOFLAG32;
129 inline bool opHiBits64 () const {
130 return flags & HIFLAG64;
132 inline bool opLoBits64 () const {
133 return flags & LOFLAG64;
136 // used to get the reg number if when one is allocated (must be
137 // called only after reg alloc)
138 inline int getAllocatedRegNum() const {
139 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
140 opType == MO_MachineRegister);
145 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
148 // These functions are provided so that a vector of operands can be
149 // statically allocated and individual ones can be initialized later.
150 // Give class MachineInstr access to these functions.
152 void Initialize (MachineOperandType operandType,
154 void InitializeConst (MachineOperandType operandType,
156 void InitializeReg (int regNum,
159 // Construction methods needed for fine-grain control.
160 // These must be accessed via coresponding methods in MachineInstr.
161 void markDef() { flags |= DEFFLAG; }
162 void markDefAndUse() { flags |= DEFUSEFLAG; }
163 void markHi32() { flags |= HIFLAG32; }
164 void markLo32() { flags |= LOFLAG32; }
165 void markHi64() { flags |= HIFLAG64; }
166 void markLo64() { flags |= LOFLAG64; }
168 // Replaces the Value with its corresponding physical register after
169 // register allocation is complete
170 void setRegForValue(int reg) {
171 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
172 opType == MO_MachineRegister);
176 friend class MachineInstr;
181 MachineOperand::MachineOperand()
182 : opType(MO_VirtualRegister),
189 MachineOperand::MachineOperand(MachineOperandType operandType,
191 : opType(operandType),
198 MachineOperand::MachineOperand(const MachineOperand& mo)
203 case MO_VirtualRegister:
204 case MO_CCRegister: value = mo.value; break;
205 case MO_MachineRegister: regNum = mo.regNum; break;
206 case MO_SignExtendedImmed:
207 case MO_UnextendedImmed:
208 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
214 MachineOperand::Initialize(MachineOperandType operandType,
217 opType = operandType;
224 MachineOperand::InitializeConst(MachineOperandType operandType,
227 opType = operandType;
235 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
237 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
239 regNum = (int) _regNum;
244 //---------------------------------------------------------------------------
245 // class MachineInstr
248 // Representation of each machine instruction.
250 // MachineOpCode must be an enum, defined separately for each target.
251 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
253 // opCodeMask is used to record variants of an instruction.
254 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
255 // ANNUL: if 1: Annul delay slot instruction.
256 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
257 // Instead of creating 4 different opcodes for BNZ, we create a single
258 // opcode and set bits in opCodeMask for each of these flags.
260 // There are 2 kinds of operands:
262 // (1) Explicit operands of the machine instruction in vector operands[]
264 // (2) "Implicit operands" are values implicitly used or defined by the
265 // machine instruction, such as arguments to a CALL, return value of
266 // a CALL (if any), and return value of a RETURN.
267 //---------------------------------------------------------------------------
269 class MachineInstr : public Annotable, // Values are annotable
270 public NonCopyableV { // Disable copy operations
271 MachineOpCode opCode; // the opcode
272 OpCodeMask opCodeMask; // extra bits for variants of an opcode
273 vector<MachineOperand> operands; // the operands
274 vector<Value*> implicitRefs; // values implicitly referenced by this
275 vector<bool> implicitIsDef; // machine instruction (eg, call args)
276 vector<bool> implicitIsDefAndUse; //
277 hash_set<int> regsUsed; // all machine registers used for this
278 // instruction, including regs used
279 // to save values across the instr.
281 /*ctor*/ MachineInstr (MachineOpCode _opCode,
282 OpCodeMask _opCodeMask = 0x0);
283 /*ctor*/ MachineInstr (MachineOpCode _opCode,
284 unsigned numOperands,
285 OpCodeMask _opCodeMask = 0x0);
286 inline ~MachineInstr () {}
287 const MachineOpCode getOpCode () const { return opCode; }
290 // Information about explicit operands of the instruction
292 unsigned int getNumOperands () const { return operands.size(); }
294 bool operandIsDefined(unsigned i) const;
295 bool operandIsDefinedAndUsed(unsigned i) const;
297 const MachineOperand& getOperand (unsigned i) const;
298 MachineOperand& getOperand (unsigned i);
301 // Information about implicit operands of the instruction
303 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
305 bool implicitRefIsDefined(unsigned i) const;
306 bool implicitRefIsDefinedAndUsed(unsigned i) const;
308 const Value* getImplicitRef (unsigned i) const;
309 Value* getImplicitRef (unsigned i);
312 // Information about registers used in this instruction
314 const hash_set<int>& getRegsUsed () const { return regsUsed; }
315 hash_set<int>& getRegsUsed () { return regsUsed; }
321 friend std::ostream& operator<< (std::ostream& os,
322 const MachineInstr& minstr);
325 // Define iterators to access the Value operands of the Machine Instruction.
326 // begin() and end() are defined to produce these iterators...
328 template<class _MI, class _V> class ValOpIterator;
329 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
330 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
333 // Access to set the operands when building the machine instruction
335 void SetMachineOperandVal(unsigned i,
336 MachineOperand::MachineOperandType
340 bool isDefAndUse=false);
341 void SetMachineOperandConst(unsigned i,
342 MachineOperand::MachineOperandType
345 void SetMachineOperandReg(unsigned i, int regNum,
347 bool isDefAndUse=false,
350 void addImplicitRef (Value* val,
352 bool isDefAndUse=false);
354 void setImplicitRef (unsigned i,
357 bool isDefAndUse=false);
359 void setOperandHi32 (unsigned i);
360 void setOperandLo32 (unsigned i);
361 void setOperandHi64 (unsigned i);
362 void setOperandLo64 (unsigned i);
365 // Replaces the Value for the operand with its allocated
366 // physical register after register allocation is complete.
368 void SetRegForOperand(unsigned i, int regNum);
371 // Iterator to enumerate machine operands.
373 template<class MITy, class VTy>
374 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
378 inline void skipToNextVal() {
379 while (i < MI->getNumOperands() &&
380 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
381 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
382 && MI->getOperand(i).getVRegValue() != 0))
386 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
391 typedef ValOpIterator<MITy, VTy> _Self;
393 inline VTy operator*() const { return MI->getOperand(i).getVRegValue(); }
395 const MachineOperand &getMachineOperand() const {
396 return MI->getOperand(i);
399 inline VTy operator->() const { return operator*(); }
401 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
402 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse(); }
404 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
405 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
407 inline bool operator==(const _Self &y) const {
410 inline bool operator!=(const _Self &y) const {
411 return !operator==(y);
414 static _Self begin(MITy MI) {
417 static _Self end(MITy MI) {
418 return _Self(MI, MI->getNumOperands());
422 // define begin() and end()
423 val_op_iterator begin() { return val_op_iterator::begin(this); }
424 val_op_iterator end() { return val_op_iterator::end(this); }
426 const_val_op_iterator begin() const {
427 return const_val_op_iterator::begin(this);
429 const_val_op_iterator end() const {
430 return const_val_op_iterator::end(this);
435 inline MachineOperand&
436 MachineInstr::getOperand(unsigned int i)
438 assert(i < operands.size() && "getOperand() out of range!");
442 inline const MachineOperand&
443 MachineInstr::getOperand(unsigned int i) const
445 assert(i < operands.size() && "getOperand() out of range!");
450 MachineInstr::operandIsDefined(unsigned int i) const
452 return getOperand(i).opIsDef();
456 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
458 return getOperand(i).opIsDefAndUse();
462 MachineInstr::implicitRefIsDefined(unsigned int i) const
464 assert(i < implicitIsDef.size() && "operand out of range!");
465 return implicitIsDef[i];
469 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
471 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
472 return implicitIsDefAndUse[i];
476 MachineInstr::getImplicitRef(unsigned int i) const
478 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
479 return implicitRefs[i];
483 MachineInstr::getImplicitRef(unsigned int i)
485 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
486 return implicitRefs[i];
490 MachineInstr::addImplicitRef(Value* val,
494 implicitRefs.push_back(val);
495 implicitIsDef.push_back(isDef);
496 implicitIsDefAndUse.push_back(isDefAndUse);
500 MachineInstr::setImplicitRef(unsigned int i,
505 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
506 implicitRefs[i] = val;
507 implicitIsDef[i] = isDef;
508 implicitIsDefAndUse[i] = isDefAndUse;
512 MachineInstr::setOperandHi32(unsigned i)
514 operands[i].markHi32();
518 MachineInstr::setOperandLo32(unsigned i)
520 operands[i].markLo32();
524 MachineInstr::setOperandHi64(unsigned i)
526 operands[i].markHi64();
530 MachineInstr::setOperandLo64(unsigned i)
532 operands[i].markLo64();
536 //---------------------------------------------------------------------------
538 //---------------------------------------------------------------------------
540 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
542 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
544 void PrintMachineInstructions(const Function *F);