1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
25 class TargetInstrDesc;
26 class TargetInstrInfo;
27 class TargetRegisterInfo;
29 template <typename T> struct ilist_traits;
30 template <typename T> struct ilist;
32 //===----------------------------------------------------------------------===//
33 /// MachineInstr - Representation of each machine instruction.
36 const TargetInstrDesc *TID; // Instruction descriptor.
37 unsigned short NumImplicitOps; // Number of implicit operands (which
38 // are determined at construction time).
40 std::vector<MachineOperand> Operands; // the operands
41 std::vector<MachineMemOperand> MemOperands;// information on memory references
42 MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
43 MachineBasicBlock *Parent; // Pointer to the owning basic block.
45 // OperandComplete - Return true if it's illegal to add a new operand
46 bool OperandsComplete() const;
48 MachineInstr(const MachineInstr&);
49 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
51 // Intrusive list support
52 friend struct ilist_traits<MachineInstr>;
53 friend struct ilist_traits<MachineBasicBlock>;
54 void setParent(MachineBasicBlock *P) { Parent = P; }
56 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
57 /// TID NULL and no operands.
60 /// MachineInstr ctor - This constructor create a MachineInstr and add the
61 /// implicit operands. It reserves space for number of operands specified by
63 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
65 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
66 /// the MachineInstr is created and added to the end of the specified basic
69 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
73 const MachineBasicBlock* getParent() const { return Parent; }
74 MachineBasicBlock* getParent() { return Parent; }
76 /// getDesc - Returns the target instruction descriptor of this
78 const TargetInstrDesc &getDesc() const { return *TID; }
80 /// getOpcode - Returns the opcode of this MachineInstr.
82 int getOpcode() const;
84 /// Access to explicit operands of the instruction.
86 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
88 const MachineOperand& getOperand(unsigned i) const {
89 assert(i < getNumOperands() && "getOperand() out of range!");
92 MachineOperand& getOperand(unsigned i) {
93 assert(i < getNumOperands() && "getOperand() out of range!");
97 /// getNumExplicitOperands - Returns the number of non-implicit operands.
99 unsigned getNumExplicitOperands() const;
101 /// Access to memory operands of the instruction
102 unsigned getNumMemOperands() const { return (unsigned)MemOperands.size(); }
104 const MachineMemOperand& getMemOperand(unsigned i) const {
105 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
106 return MemOperands[i];
108 MachineMemOperand& getMemOperand(unsigned i) {
109 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
110 return MemOperands[i];
113 /// isIdenticalTo - Return true if this instruction is identical to (same
114 /// opcode and same operands as) the specified instruction.
115 bool isIdenticalTo(const MachineInstr *Other) const {
116 if (Other->getOpcode() != getOpcode() ||
117 Other->getNumOperands() != getNumOperands())
119 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
120 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
125 /// clone - Create a copy of 'this' instruction that is identical in
126 /// all ways except the the instruction has no parent, prev, or next.
127 MachineInstr* clone() const { return new MachineInstr(*this); }
129 /// removeFromParent - This method unlinks 'this' from the containing basic
130 /// block, and returns it, but does not delete it.
131 MachineInstr *removeFromParent();
133 /// eraseFromParent - This method unlinks 'this' from the containing basic
134 /// block and deletes it.
135 void eraseFromParent() {
136 delete removeFromParent();
139 /// isLabel - Returns true if the MachineInstr represents a label.
141 bool isLabel() const;
143 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
145 bool isDebugLabel() const;
147 /// readsRegister - Return true if the MachineInstr reads the specified
148 /// register. If TargetRegisterInfo is passed, then it also checks if there
149 /// is a read of a super-register.
150 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
151 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
154 /// killsRegister - Return true if the MachineInstr kills the specified
155 /// register. If TargetRegisterInfo is passed, then it also checks if there is
156 /// a kill of a super-register.
157 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
158 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
161 /// modifiesRegister - Return true if the MachineInstr modifies the
162 /// specified register. If TargetRegisterInfo is passed, then it also checks
163 /// if there is a def of a super-register.
164 bool modifiesRegister(unsigned Reg,
165 const TargetRegisterInfo *TRI = NULL) const {
166 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
169 /// registerDefIsDead - Returns true if the register is dead in this machine
170 /// instruction. If TargetRegisterInfo is passed, then it also checks
171 /// if there is a dead def of a super-register.
172 bool registerDefIsDead(unsigned Reg,
173 const TargetRegisterInfo *TRI = NULL) const {
174 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
177 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
178 /// the specific register or -1 if it is not found. It further tightening
179 /// the search criteria to a use that kills the register if isKill is true.
180 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
181 const TargetRegisterInfo *TRI = NULL) const;
183 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
184 /// a pointer to the MachineOperand rather than an index.
185 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
186 const TargetRegisterInfo *TRI = NULL) {
187 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
188 return (Idx == -1) ? NULL : &getOperand(Idx);
191 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
192 /// the specified register or -1 if it is not found. If isDead is true, defs
193 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
194 /// also checks if there is a def of a super-register.
195 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
196 const TargetRegisterInfo *TRI = NULL) const;
198 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
199 /// a pointer to the MachineOperand rather than an index.
200 MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false,
201 const TargetRegisterInfo *TRI = NULL) {
202 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
203 return (Idx == -1) ? NULL : &getOperand(Idx);
206 /// findFirstPredOperandIdx() - Find the index of the first operand in the
207 /// operand list that is used to represent the predicate. It returns -1 if
209 int findFirstPredOperandIdx() const;
211 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
212 /// to two addr elimination.
213 bool isRegReDefinedByTwoAddr(unsigned Reg) const;
215 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
217 void copyKillDeadInfo(const MachineInstr *MI);
219 /// copyPredicates - Copies predicate operand(s) from MI.
220 void copyPredicates(const MachineInstr *MI);
222 /// addRegisterKilled - We have determined MI kills a register. Look for the
223 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
224 /// add a implicit operand if it's not found. Returns true if the operand
225 /// exists / is added.
226 bool addRegisterKilled(unsigned IncomingReg,
227 const TargetRegisterInfo *RegInfo,
228 bool AddIfNotFound = false);
230 /// addRegisterDead - We have determined MI defined a register without a use.
231 /// Look for the operand that defines it and mark it as IsDead. If
232 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
233 /// true if the operand exists / is added.
234 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
235 bool AddIfNotFound = false);
237 /// copyKillDeadInfo - Copies killed/dead information from one instr to another
238 void copyKillDeadInfo(MachineInstr *OldMI,
239 const TargetRegisterInfo *RegInfo);
241 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore
242 /// true, it means there is a store (or call) between the instruction the
243 /// localtion and its intended destination.
244 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
249 void print(std::ostream *OS, const TargetMachine *TM) const {
250 if (OS) print(*OS, TM);
252 void print(std::ostream &OS, const TargetMachine *TM = 0) const;
253 void print(std::ostream *OS) const { if (OS) print(*OS); }
256 //===--------------------------------------------------------------------===//
257 // Accessors used to build up machine instructions.
259 /// addOperand - Add the specified operand to the instruction. If it is an
260 /// implicit operand, it is added to the end of the operand list. If it is
261 /// an explicit operand it is added at the end of the explicit operand list
262 /// (before the first implicit operand).
263 void addOperand(const MachineOperand &Op);
265 /// setDesc - Replace the instruction descriptor (thus opcode) of
266 /// the current instruction with a new one.
268 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
270 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
271 /// fewer operand than it started with.
273 void RemoveOperand(unsigned i);
275 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
276 /// referencing arbitrary storage.
277 void addMemOperand(const MachineMemOperand &MO) {
278 MemOperands.push_back(MO);
282 /// getRegInfo - If this instruction is embedded into a MachineFunction,
283 /// return the MachineRegisterInfo object for the current function, otherwise
285 MachineRegisterInfo *getRegInfo();
287 /// addImplicitDefUseOperands - Add all implicit def and use operands to
288 /// this instruction.
289 void addImplicitDefUseOperands();
291 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
292 /// this instruction from their respective use lists. This requires that the
293 /// operands already be on their use lists.
294 void RemoveRegOperandsFromUseLists();
296 /// AddRegOperandsToUseLists - Add all of the register operands in
297 /// this instruction from their respective use lists. This requires that the
298 /// operands not be on their use lists yet.
299 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
302 //===----------------------------------------------------------------------===//
305 inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
310 } // End llvm namespace