1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
15 #include <ext/hash_set>
20 //---------------------------------------------------------------------------
21 // class MachineOperand
24 // Representation of each machine instruction operand.
25 // This class is designed so that you can allocate a vector of operands
26 // first and initialize each one later.
28 // E.g, for this VM instruction:
29 // ptr = alloca type, numElements
30 // we generate 2 machine instructions on the SPARC:
32 // mul Constant, Numelements -> Reg
33 // add %sp, Reg -> Ptr
35 // Each instruction has 3 operands, listed above. Of those:
36 // - Reg, NumElements, and Ptr are of operand type MO_Register.
37 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
39 // For the register operands, the virtual register type is as follows:
41 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
42 // MachineInstr* minstr will point to the instruction that computes reg.
44 // - %sp will be of virtual register type MO_MachineReg.
45 // The field regNum identifies the machine register.
47 // - NumElements will be of virtual register type MO_VirtualReg.
48 // The field Value* value identifies the value.
50 // - Ptr will also be of virtual register type MO_VirtualReg.
51 // Again, the field Value* value identifies the value.
53 //---------------------------------------------------------------------------
56 class MachineOperand {
58 enum MachineOperandType {
59 MO_VirtualRegister, // virtual register for *value
60 MO_MachineRegister, // pre-assigned machine register `regNum'
68 // Bit fields of the flags variable used for different operand properties
69 static const char DEFFLAG = 0x1; // this is a def of the operand
70 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
71 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
72 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
73 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
74 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
77 MachineOperandType opType;
80 Value* value; // BasicBlockVal for a label operand.
81 // ConstantVal for a non-address immediate.
82 // Virtual register for an SSA operand,
83 // including hidden operands required for
84 // the generated machine code.
85 int64_t immedVal; // constant value for an explicit constant
88 int regNum; // register number for an explicit register
89 // will be set for a value after reg allocation
90 char flags; // see bit field definitions above
93 /*ctor*/ MachineOperand ();
94 /*ctor*/ MachineOperand (MachineOperandType operandType,
96 /*copy ctor*/ MachineOperand (const MachineOperand&);
97 /*dtor*/ ~MachineOperand () {}
99 // Accessor methods. Caller is responsible for checking the
100 // operand type before invoking the corresponding accessor.
102 inline MachineOperandType getOperandType() const {
105 inline Value* getVRegValue () const {
106 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
107 opType == MO_PCRelativeDisp);
110 inline int getMachineRegNum() const {
111 assert(opType == MO_MachineRegister);
114 inline int64_t getImmedValue () const {
115 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
118 inline bool opIsDef () const {
119 return flags & DEFFLAG;
121 inline bool opIsDefAndUse () const {
122 return flags & DEFUSEFLAG;
124 inline bool opHiBits32 () const {
125 return flags & HIFLAG32;
127 inline bool opLoBits32 () const {
128 return flags & LOFLAG32;
130 inline bool opHiBits64 () const {
131 return flags & HIFLAG64;
133 inline bool opLoBits64 () const {
134 return flags & LOFLAG64;
137 // used to get the reg number if when one is allocated (must be
138 // called only after reg alloc)
139 inline int getAllocatedRegNum() const {
140 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
141 opType == MO_MachineRegister);
146 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
149 // These functions are provided so that a vector of operands can be
150 // statically allocated and individual ones can be initialized later.
151 // Give class MachineInstr access to these functions.
153 void Initialize (MachineOperandType operandType,
155 void InitializeConst (MachineOperandType operandType,
157 void InitializeReg (int regNum,
160 // Construction methods needed for fine-grain control.
161 // These must be accessed via coresponding methods in MachineInstr.
162 void markDef() { flags |= DEFFLAG; }
163 void markDefAndUse() { flags |= DEFUSEFLAG; }
164 void markHi32() { flags |= HIFLAG32; }
165 void markLo32() { flags |= LOFLAG32; }
166 void markHi64() { flags |= HIFLAG64; }
167 void markLo64() { flags |= LOFLAG64; }
169 // Replaces the Value with its corresponding physical register after
170 // register allocation is complete
171 void setRegForValue(int reg) {
172 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
173 opType == MO_MachineRegister);
177 friend class MachineInstr;
182 MachineOperand::MachineOperand()
183 : opType(MO_VirtualRegister),
190 MachineOperand::MachineOperand(MachineOperandType operandType,
192 : opType(operandType),
199 MachineOperand::MachineOperand(const MachineOperand& mo)
204 case MO_VirtualRegister:
205 case MO_CCRegister: value = mo.value; break;
206 case MO_MachineRegister: regNum = mo.regNum; break;
207 case MO_SignExtendedImmed:
208 case MO_UnextendedImmed:
209 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
215 MachineOperand::Initialize(MachineOperandType operandType,
218 opType = operandType;
225 MachineOperand::InitializeConst(MachineOperandType operandType,
228 opType = operandType;
236 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
238 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
240 regNum = (int) _regNum;
245 //---------------------------------------------------------------------------
246 // class MachineInstr
249 // Representation of each machine instruction.
251 // MachineOpCode must be an enum, defined separately for each target.
252 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
254 // opCodeMask is used to record variants of an instruction.
255 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
256 // ANNUL: if 1: Annul delay slot instruction.
257 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
258 // Instead of creating 4 different opcodes for BNZ, we create a single
259 // opcode and set bits in opCodeMask for each of these flags.
261 // There are 2 kinds of operands:
263 // (1) Explicit operands of the machine instruction in vector operands[]
265 // (2) "Implicit operands" are values implicitly used or defined by the
266 // machine instruction, such as arguments to a CALL, return value of
267 // a CALL (if any), and return value of a RETURN.
268 //---------------------------------------------------------------------------
270 class MachineInstr : public Annotable, // Values are annotable
271 public NonCopyableV { // Disable copy operations
272 MachineOpCode opCode; // the opcode
273 OpCodeMask opCodeMask; // extra bits for variants of an opcode
274 vector<MachineOperand> operands; // the operands
275 vector<Value*> implicitRefs; // values implicitly referenced by this
276 vector<bool> implicitIsDef; // machine instruction (eg, call args)
277 vector<bool> implicitIsDefAndUse; //
278 hash_set<int> regsUsed; // all machine registers used for this
279 // instruction, including regs used
280 // to save values across the instr.
282 /*ctor*/ MachineInstr (MachineOpCode _opCode,
283 OpCodeMask _opCodeMask = 0x0);
284 /*ctor*/ MachineInstr (MachineOpCode _opCode,
285 unsigned numOperands,
286 OpCodeMask _opCodeMask = 0x0);
287 inline ~MachineInstr () {}
288 const MachineOpCode getOpCode () const { return opCode; }
291 // Information about explicit operands of the instruction
293 unsigned int getNumOperands () const { return operands.size(); }
295 bool operandIsDefined(unsigned i) const;
296 bool operandIsDefinedAndUsed(unsigned i) const;
298 const MachineOperand& getOperand (unsigned i) const;
299 MachineOperand& getOperand (unsigned i);
302 // Information about implicit operands of the instruction
304 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
306 bool implicitRefIsDefined(unsigned i) const;
307 bool implicitRefIsDefinedAndUsed(unsigned i) const;
309 const Value* getImplicitRef (unsigned i) const;
310 Value* getImplicitRef (unsigned i);
313 // Information about registers used in this instruction
315 const hash_set<int>& getRegsUsed () const { return regsUsed; }
316 hash_set<int>& getRegsUsed () { return regsUsed; }
322 friend std::ostream& operator<< (std::ostream& os,
323 const MachineInstr& minstr);
326 // Define iterators to access the Value operands of the Machine Instruction.
327 // begin() and end() are defined to produce these iterators...
329 template<class _MI, class _V> class ValOpIterator;
330 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
331 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
334 // Access to set the operands when building the machine instruction
336 void SetMachineOperandVal(unsigned i,
337 MachineOperand::MachineOperandType
341 bool isDefAndUse=false);
342 void SetMachineOperandConst(unsigned i,
343 MachineOperand::MachineOperandType
346 void SetMachineOperandReg(unsigned i, int regNum,
348 bool isDefAndUse=false,
351 void addImplicitRef (Value* val,
353 bool isDefAndUse=false);
355 void setImplicitRef (unsigned i,
358 bool isDefAndUse=false);
360 void setOperandHi32 (unsigned i);
361 void setOperandLo32 (unsigned i);
362 void setOperandHi64 (unsigned i);
363 void setOperandLo64 (unsigned i);
366 // Replaces the Value for the operand with its allocated
367 // physical register after register allocation is complete.
369 void SetRegForOperand(unsigned i, int regNum);
372 // Iterator to enumerate machine operands.
374 template<class MITy, class VTy>
375 class ValOpIterator : public std::forward_iterator<VTy, ptrdiff_t> {
379 inline void skipToNextVal() {
380 while (i < MI->getNumOperands() &&
381 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
382 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
383 && MI->getOperand(i).getVRegValue() != 0))
387 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
392 typedef ValOpIterator<MITy, VTy> _Self;
394 inline VTy operator*() const { return MI->getOperand(i).getVRegValue(); }
396 const MachineOperand &getMachineOperand() const {
397 return MI->getOperand(i);
400 inline VTy operator->() const { return operator*(); }
402 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
403 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse(); }
405 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
406 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
408 inline bool operator==(const _Self &y) const {
411 inline bool operator!=(const _Self &y) const {
412 return !operator==(y);
415 static _Self begin(MITy MI) {
418 static _Self end(MITy MI) {
419 return _Self(MI, MI->getNumOperands());
423 // define begin() and end()
424 val_op_iterator begin() { return val_op_iterator::begin(this); }
425 val_op_iterator end() { return val_op_iterator::end(this); }
427 const_val_op_iterator begin() const {
428 return const_val_op_iterator::begin(this);
430 const_val_op_iterator end() const {
431 return const_val_op_iterator::end(this);
436 inline MachineOperand&
437 MachineInstr::getOperand(unsigned int i)
439 assert(i < operands.size() && "getOperand() out of range!");
443 inline const MachineOperand&
444 MachineInstr::getOperand(unsigned int i) const
446 assert(i < operands.size() && "getOperand() out of range!");
451 MachineInstr::operandIsDefined(unsigned int i) const
453 return getOperand(i).opIsDef();
457 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
459 return getOperand(i).opIsDefAndUse();
463 MachineInstr::implicitRefIsDefined(unsigned int i) const
465 assert(i < implicitIsDef.size() && "operand out of range!");
466 return implicitIsDef[i];
470 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
472 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
473 return implicitIsDefAndUse[i];
477 MachineInstr::getImplicitRef(unsigned int i) const
479 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
480 return implicitRefs[i];
484 MachineInstr::getImplicitRef(unsigned int i)
486 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
487 return implicitRefs[i];
491 MachineInstr::addImplicitRef(Value* val,
493 bool isDefAndUse=false)
495 implicitRefs.push_back(val);
496 implicitIsDef.push_back(isDef);
497 implicitIsDefAndUse.push_back(isDefAndUse);
501 MachineInstr::setImplicitRef(unsigned int i,
504 bool isDefAndUse=false)
506 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
507 implicitRefs[i] = val;
508 implicitIsDef[i] = isDef;
509 implicitIsDefAndUse[i] = isDefAndUse;
513 MachineInstr::setOperandHi32(unsigned i)
515 operands[i].markHi32();
519 MachineInstr::setOperandLo32(unsigned i)
521 operands[i].markLo32();
525 MachineInstr::setOperandHi64(unsigned i)
527 operands[i].markHi64();
531 MachineInstr::setOperandLo64(unsigned i)
533 operands[i].markLo64();
537 //---------------------------------------------------------------------------
539 //---------------------------------------------------------------------------
541 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
543 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
545 void PrintMachineInstructions(const Function *F);