1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "Support/Annotation.h"
21 #include "Support/iterator"
25 class MachineBasicBlock;
29 typedef int MachineOpCode;
31 //===----------------------------------------------------------------------===//
32 /// Special flags on instructions that modify the opcode.
33 /// These flags are unused for now, but having them enforces that some
34 /// changes will be needed if they are used.
36 enum MachineOpCodeFlags {
37 AnnulFlag, /// 1 if annul bit is set on a branch
38 PredTakenFlag, /// 1 if branch should be predicted taken
39 PredNotTakenFlag /// 1 if branch should be predicted not taken
42 //===----------------------------------------------------------------------===//
43 /// MOTy - MachineOperandType - This namespace contains an enum that describes
44 /// how the machine operand is used by the instruction: is it read, defined, or
45 /// both? Note that the MachineInstr/Operator class currently uses bool
46 /// arguments to represent this information instead of an enum. Eventually this
47 /// should change over to use this _easier to read_ representation instead.
51 Use, /// This machine operand is only read by the instruction
52 Def, /// This machine operand is only written by the instruction
53 UseAndDef /// This machine operand is read AND written
57 //===----------------------------------------------------------------------===//
58 // class MachineOperand
61 // Representation of each machine instruction operand.
62 // This class is designed so that you can allocate a vector of operands
63 // first and initialize each one later.
65 // E.g, for this VM instruction:
66 // ptr = alloca type, numElements
67 // we generate 2 machine instructions on the SPARC:
69 // mul Constant, Numelements -> Reg
70 // add %sp, Reg -> Ptr
72 // Each instruction has 3 operands, listed above. Of those:
73 // - Reg, NumElements, and Ptr are of operand type MO_Register.
74 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
76 // For the register operands, the virtual register type is as follows:
78 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
79 // MachineInstr* minstr will point to the instruction that computes reg.
81 // - %sp will be of virtual register type MO_MachineReg.
82 // The field regNum identifies the machine register.
84 // - NumElements will be of virtual register type MO_VirtualReg.
85 // The field Value* value identifies the value.
87 // - Ptr will also be of virtual register type MO_VirtualReg.
88 // Again, the field Value* value identifies the value.
90 //===----------------------------------------------------------------------===//
92 struct MachineOperand {
93 enum MachineOperandType {
94 MO_VirtualRegister, // virtual register for *value
95 MO_MachineRegister, // pre-assigned machine register `regNum'
100 MO_MachineBasicBlock, // MachineBasicBlock reference
101 MO_FrameIndex, // Abstract Stack Frame Index
102 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
103 MO_ExternalSymbol, // Name of external global symbol
104 MO_GlobalAddress, // Address of a global value
108 // Bit fields of the flags variable used for different operand properties
110 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
111 DEFUSEFLAG = 0x02, // this is both a def and a use
112 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
113 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
114 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
115 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
116 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
123 Value* value; // BasicBlockVal for a label operand.
124 // ConstantVal for a non-address immediate.
125 // Virtual register for an SSA operand,
126 // including hidden operands required for
127 // the generated machine code.
128 // LLVM global for MO_GlobalAddress.
130 int64_t immedVal; // Constant value for an explicit constant
132 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
133 std::string *SymbolName; // For MO_ExternalSymbol type
136 char flags; // see bit field definitions above
137 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
138 int regNum; // register number for an explicit register
139 // will be set for a value after reg allocation
144 opType(MO_VirtualRegister),
147 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
153 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
158 case MOTy::Use: flags = 0; break;
159 case MOTy::Def: flags = DEFONLYFLAG; break;
160 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
161 default: assert(0 && "Invalid value for UseTy!");
165 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
166 bool isPCRelative = false)
167 : value(V), opType(OpTy), regNum(-1) {
169 case MOTy::Use: flags = 0; break;
170 case MOTy::Def: flags = DEFONLYFLAG; break;
171 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
172 default: assert(0 && "Invalid value for UseTy!");
174 if (isPCRelative) flags |= PCRELATIVE;
177 MachineOperand(MachineBasicBlock *mbb)
178 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
180 MachineOperand(const std::string &SymName, bool isPCRelative)
181 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
182 opType(MO_ExternalSymbol), regNum(-1) {}
185 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
189 if (isExternalSymbol())
190 SymbolName = new std::string(M.getSymbolName());
194 if (isExternalSymbol())
198 const MachineOperand &operator=(const MachineOperand &MO) {
199 if (isExternalSymbol()) // if old operand had a symbol name,
200 delete SymbolName; // release old memory
201 immedVal = MO.immedVal;
205 if (isExternalSymbol())
206 SymbolName = new std::string(MO.getSymbolName());
210 // Accessor methods. Caller is responsible for checking the
211 // operand type before invoking the corresponding accessor.
213 MachineOperandType getType() const { return opType; }
215 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
216 /// indicates whether this operand should be emitted as a PC relative value
217 /// instead of a global address. This is used for operands of the forms:
218 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
220 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
223 // This is to finally stop caring whether we have a virtual or machine
224 // register -- an easier interface is to simply call both virtual and machine
225 // registers essentially the same, yet be able to distinguish when
226 // necessary. Thus the instruction selector can just add registers without
227 // abandon, and the register allocator won't be confused.
228 bool isVirtualRegister() const {
229 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
230 && regNum >= MRegisterInfo::FirstVirtualRegister;
232 bool isPhysicalRegister() const {
233 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
234 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
236 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
237 bool isMachineRegister() const { return !isVirtualRegister(); }
238 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
239 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
240 bool isImmediate() const {
241 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
243 bool isFrameIndex() const { return opType == MO_FrameIndex; }
244 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
245 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
246 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
248 Value* getVRegValue() const {
249 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
253 Value* getVRegValueOrNull() const {
254 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
255 isPCRelativeDisp()) ? value : NULL;
257 int getMachineRegNum() const {
258 assert(opType == MO_MachineRegister);
261 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
262 MachineBasicBlock *getMachineBasicBlock() const {
263 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
266 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
267 unsigned getConstantPoolIndex() const {
268 assert(isConstantPoolIndex());
272 GlobalValue *getGlobal() const {
273 assert(isGlobalAddress());
274 return (GlobalValue*)value;
277 const std::string &getSymbolName() const {
278 assert(isExternalSymbol());
282 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
283 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
284 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
285 bool opHiBits32 () const { return flags & HIFLAG32; }
286 bool opLoBits32 () const { return flags & LOFLAG32; }
287 bool opHiBits64 () const { return flags & HIFLAG64; }
288 bool opLoBits64 () const { return flags & LOFLAG64; }
290 // used to check if a machine register has been allocated to this operand
291 bool hasAllocatedReg() const {
292 return (regNum >= 0 &&
293 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
294 opType == MO_MachineRegister));
297 // used to get the reg number if when one is allocated
298 int getAllocatedRegNum() const {
299 assert(hasAllocatedReg());
303 // ********** TODO: get rid of this duplicate code! ***********
304 unsigned getReg() const {
305 return getAllocatedRegNum();
308 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
312 // Construction methods needed for fine-grain control.
313 // These must be accessed via coresponding methods in MachineInstr.
314 void markHi32() { flags |= HIFLAG32; }
315 void markLo32() { flags |= LOFLAG32; }
316 void markHi64() { flags |= HIFLAG64; }
317 void markLo64() { flags |= LOFLAG64; }
319 // Replaces the Value with its corresponding physical register after
320 // register allocation is complete
321 void setRegForValue(int reg) {
322 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
323 opType == MO_MachineRegister);
327 friend class MachineInstr;
331 //===----------------------------------------------------------------------===//
332 // class MachineInstr
335 // Representation of each machine instruction.
337 // MachineOpCode must be an enum, defined separately for each target.
338 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
340 // There are 2 kinds of operands:
342 // (1) Explicit operands of the machine instruction in vector operands[]
344 // (2) "Implicit operands" are values implicitly used or defined by the
345 // machine instruction, such as arguments to a CALL, return value of
346 // a CALL (if any), and return value of a RETURN.
347 //===----------------------------------------------------------------------===//
350 int opCode; // the opcode
351 unsigned opCodeFlags; // flags modifying instrn behavior
352 std::vector<MachineOperand> operands; // the operands
353 unsigned numImplicitRefs; // number of implicit operands
355 // OperandComplete - Return true if it's illegal to add a new operand
356 bool OperandsComplete() const;
358 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
359 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
361 MachineInstr(int Opcode, unsigned numOperands);
363 /// MachineInstr ctor - This constructor only does a _reserve_ of the
364 /// operands, not a resize for them. It is expected that if you use this that
365 /// you call add* methods below to fill up the operands, instead of the Set
366 /// methods. Eventually, the "resizing" ctors will be phased out.
368 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
370 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
371 /// the MachineInstr is created and added to the end of the specified basic
374 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
379 const int getOpcode() const { return opCode; }
380 const int getOpCode() const { return opCode; }
384 unsigned getOpCodeFlags() const { return opCodeFlags; }
387 // Access to explicit operands of the instruction
389 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
391 const MachineOperand& getOperand(unsigned i) const {
392 assert(i < getNumOperands() && "getOperand() out of range!");
395 MachineOperand& getOperand(unsigned i) {
396 assert(i < getNumOperands() && "getOperand() out of range!");
401 // Access to explicit or implicit operands of the instruction
402 // This returns the i'th entry in the operand vector.
403 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
404 // depending on whether i < N or i >= N.
406 const MachineOperand& getExplOrImplOperand(unsigned i) const {
407 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
408 return (i < getNumOperands()? getOperand(i)
409 : getImplicitOp(i - getNumOperands()));
413 // Access to implicit operands of the instruction
415 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
417 MachineOperand& getImplicitOp(unsigned i) {
418 assert(i < numImplicitRefs && "implicit ref# out of range!");
419 return operands[i + operands.size() - numImplicitRefs];
421 const MachineOperand& getImplicitOp(unsigned i) const {
422 assert(i < numImplicitRefs && "implicit ref# out of range!");
423 return operands[i + operands.size() - numImplicitRefs];
426 Value* getImplicitRef(unsigned i) {
427 return getImplicitOp(i).getVRegValue();
429 const Value* getImplicitRef(unsigned i) const {
430 return getImplicitOp(i).getVRegValue();
433 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
435 addRegOperand(V, isDef, isDefAndUse);
437 void setImplicitRef(unsigned i, Value* V) {
438 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
439 SetMachineOperandVal(i + getNumOperands(),
440 MachineOperand::MO_VirtualRegister, V);
446 void print(std::ostream &OS, const TargetMachine &TM) const;
448 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
451 // Define iterators to access the Value operands of the Machine Instruction.
452 // Note that these iterators only enumerate the explicit operands.
453 // begin() and end() are defined to produce these iterators...
455 template<class _MI, class _V> class ValOpIterator;
456 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
457 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
460 //===--------------------------------------------------------------------===//
461 // Accessors to add operands when building up machine instructions
464 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
467 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
468 assert(!OperandsComplete() &&
469 "Trying to add an operand to a machine instr that is already done!");
470 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
471 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
474 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
475 bool isPCRelative = false) {
476 assert(!OperandsComplete() &&
477 "Trying to add an operand to a machine instr that is already done!");
478 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
482 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
483 assert(!OperandsComplete() &&
484 "Trying to add an operand to a machine instr that is already done!");
485 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
490 /// addRegOperand - Add a symbolic virtual register reference...
492 void addRegOperand(int reg, bool isDef) {
493 assert(!OperandsComplete() &&
494 "Trying to add an operand to a machine instr that is already done!");
495 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
496 isDef ? MOTy::Def : MOTy::Use));
499 /// addRegOperand - Add a symbolic virtual register reference...
501 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
502 assert(!OperandsComplete() &&
503 "Trying to add an operand to a machine instr that is already done!");
504 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
508 /// addPCDispOperand - Add a PC relative displacement operand to the MI
510 void addPCDispOperand(Value *V) {
511 assert(!OperandsComplete() &&
512 "Trying to add an operand to a machine instr that is already done!");
513 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
517 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
519 void addMachineRegOperand(int reg, bool isDef) {
520 assert(!OperandsComplete() &&
521 "Trying to add an operand to a machine instr that is already done!");
522 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
523 isDef ? MOTy::Def : MOTy::Use));
526 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
528 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
529 assert(!OperandsComplete() &&
530 "Trying to add an operand to a machine instr that is already done!");
531 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
535 /// addZeroExtImmOperand - Add a zero extended constant argument to the
536 /// machine instruction.
538 void addZeroExtImmOperand(int64_t intValue) {
539 assert(!OperandsComplete() &&
540 "Trying to add an operand to a machine instr that is already done!");
541 operands.push_back(MachineOperand(intValue,
542 MachineOperand::MO_UnextendedImmed));
545 /// addSignExtImmOperand - Add a zero extended constant argument to the
546 /// machine instruction.
548 void addSignExtImmOperand(int64_t intValue) {
549 assert(!OperandsComplete() &&
550 "Trying to add an operand to a machine instr that is already done!");
551 operands.push_back(MachineOperand(intValue,
552 MachineOperand::MO_SignExtendedImmed));
555 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
556 assert(!OperandsComplete() &&
557 "Trying to add an operand to a machine instr that is already done!");
558 operands.push_back(MachineOperand(MBB));
561 /// addFrameIndexOperand - Add an abstract frame index to the instruction
563 void addFrameIndexOperand(unsigned Idx) {
564 assert(!OperandsComplete() &&
565 "Trying to add an operand to a machine instr that is already done!");
566 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
569 /// addConstantPoolndexOperand - Add a constant pool object index to the
572 void addConstantPoolIndexOperand(unsigned I) {
573 assert(!OperandsComplete() &&
574 "Trying to add an operand to a machine instr that is already done!");
575 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
578 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
579 assert(!OperandsComplete() &&
580 "Trying to add an operand to a machine instr that is already done!");
581 operands.push_back(MachineOperand((Value*)GV,
582 MachineOperand::MO_GlobalAddress,
583 MOTy::Use, isPCRelative));
586 /// addExternalSymbolOperand - Add an external symbol operand to this instr
588 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
589 operands.push_back(MachineOperand(SymName, isPCRelative));
592 //===--------------------------------------------------------------------===//
593 // Accessors used to modify instructions in place.
595 // FIXME: Move this stuff to MachineOperand itself!
597 /// replace - Support to rewrite a machine instruction in place: for now,
598 /// simply replace() and then set new operands with Set.*Operand methods
601 void replace(int Opcode, unsigned numOperands);
603 /// setOpcode - Replace the opcode of the current instruction with a new one.
605 void setOpcode(unsigned Op) { opCode = Op; }
607 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
608 /// fewer operand than it started with.
610 void RemoveOperand(unsigned i) {
611 operands.erase(operands.begin()+i);
614 // Access to set the operands when building the machine instruction
616 void SetMachineOperandVal (unsigned i,
617 MachineOperand::MachineOperandType operandType,
620 void SetMachineOperandConst (unsigned i,
621 MachineOperand::MachineOperandType operandType,
624 void SetMachineOperandReg(unsigned i, int regNum);
627 unsigned substituteValue(const Value* oldVal, Value* newVal,
628 bool defsOnly, bool notDefsAndUses,
629 bool& someArgsWereIgnored);
631 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
632 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
633 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
634 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
637 // SetRegForOperand -
638 // SetRegForImplicitRef -
639 // Mark an explicit or implicit operand with its allocated physical register.
641 void SetRegForOperand(unsigned i, int regNum);
642 void SetRegForImplicitRef(unsigned i, int regNum);
645 // Iterator to enumerate machine operands.
647 template<class MITy, class VTy>
648 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
652 void skipToNextVal() {
653 while (i < MI->getNumOperands() &&
654 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
655 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
656 && MI->getOperand(i).getVRegValue() != 0))
660 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
665 typedef ValOpIterator<MITy, VTy> _Self;
667 inline VTy operator*() const {
668 return MI->getOperand(i).getVRegValue();
671 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
672 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
674 inline VTy operator->() const { return operator*(); }
676 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
677 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
678 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
680 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
681 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
683 inline bool operator==(const _Self &y) const {
686 inline bool operator!=(const _Self &y) const {
687 return !operator==(y);
690 static _Self begin(MITy MI) {
693 static _Self end(MITy MI) {
694 return _Self(MI, MI->getNumOperands());
698 // define begin() and end()
699 val_op_iterator begin() { return val_op_iterator::begin(this); }
700 val_op_iterator end() { return val_op_iterator::end(this); }
702 const_val_op_iterator begin() const {
703 return const_val_op_iterator::begin(this);
705 const_val_op_iterator end() const {
706 return const_val_op_iterator::end(this);
711 //===----------------------------------------------------------------------===//
714 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
715 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
716 void PrintMachineInstructions(const Function *F);