1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MRegisterInfo.h"
13 #include "Support/Annotation.h"
14 #include "Support/NonCopyable.h"
15 #include "Support/iterator"
19 class MachineBasicBlock;
23 typedef int MachineOpCode;
25 ///---------------------------------------------------------------------------
26 /// Special flags on instructions that modify the opcode.
27 /// These flags are unused for now, but having them enforces that some
28 /// changes will be needed if they are used.
29 ///---------------------------------------------------------------------------
31 enum MachineOpCodeFlags {
32 AnnulFlag, /// 1 if annul bit is set on a branch
33 PredTakenFlag, /// 1 if branch should be predicted taken
34 PredNotTakenFlag /// 1 if branch should be predicted not taken
37 ///---------------------------------------------------------------------------
38 /// MOTy - MachineOperandType - This namespace contains an enum that describes
39 /// how the machine operand is used by the instruction: is it read, defined, or
40 /// both? Note that the MachineInstr/Operator class currently uses bool
41 /// arguments to represent this information instead of an enum. Eventually this
42 /// should change over to use this _easier to read_ representation instead.
44 ///---------------------------------------------------------------------------
48 Use, /// This machine operand is only read by the instruction
49 Def, /// This machine operand is only written by the instruction
50 UseAndDef /// This machine operand is read AND written
54 //---------------------------------------------------------------------------
55 // class MachineOperand
58 // Representation of each machine instruction operand.
59 // This class is designed so that you can allocate a vector of operands
60 // first and initialize each one later.
62 // E.g, for this VM instruction:
63 // ptr = alloca type, numElements
64 // we generate 2 machine instructions on the SPARC:
66 // mul Constant, Numelements -> Reg
67 // add %sp, Reg -> Ptr
69 // Each instruction has 3 operands, listed above. Of those:
70 // - Reg, NumElements, and Ptr are of operand type MO_Register.
71 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
73 // For the register operands, the virtual register type is as follows:
75 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
76 // MachineInstr* minstr will point to the instruction that computes reg.
78 // - %sp will be of virtual register type MO_MachineReg.
79 // The field regNum identifies the machine register.
81 // - NumElements will be of virtual register type MO_VirtualReg.
82 // The field Value* value identifies the value.
84 // - Ptr will also be of virtual register type MO_VirtualReg.
85 // Again, the field Value* value identifies the value.
87 //---------------------------------------------------------------------------
89 struct MachineOperand {
90 enum MachineOperandType {
91 MO_VirtualRegister, // virtual register for *value
92 MO_MachineRegister, // pre-assigned machine register `regNum'
97 MO_MachineBasicBlock, // MachineBasicBlock reference
98 MO_FrameIndex, // Abstract Stack Frame Index
99 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
100 MO_ExternalSymbol, // Name of external global symbol
101 MO_GlobalAddress, // Address of a global value
105 // Bit fields of the flags variable used for different operand properties
107 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
108 DEFUSEFLAG = 0x02, // this is both a def and a use
109 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
110 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
111 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
112 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
113 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
120 Value* value; // BasicBlockVal for a label operand.
121 // ConstantVal for a non-address immediate.
122 // Virtual register for an SSA operand,
123 // including hidden operands required for
124 // the generated machine code.
125 // LLVM global for MO_GlobalAddress.
127 int64_t immedVal; // Constant value for an explicit constant
129 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
130 std::string *SymbolName; // For MO_ExternalSymbol type
133 char flags; // see bit field definitions above
134 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
135 int regNum; // register number for an explicit register
136 // will be set for a value after reg allocation
141 opType(MO_VirtualRegister),
144 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
150 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
155 case MOTy::Use: flags = 0; break;
156 case MOTy::Def: flags = DEFONLYFLAG; break;
157 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
158 default: assert(0 && "Invalid value for UseTy!");
162 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
163 bool isPCRelative = false)
164 : value(V), opType(OpTy), regNum(-1) {
166 case MOTy::Use: flags = 0; break;
167 case MOTy::Def: flags = DEFONLYFLAG; break;
168 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
169 default: assert(0 && "Invalid value for UseTy!");
171 if (isPCRelative) flags |= PCRELATIVE;
174 MachineOperand(MachineBasicBlock *mbb)
175 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
177 MachineOperand(const std::string &SymName, bool isPCRelative)
178 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
179 opType(MO_ExternalSymbol), regNum(-1) {}
182 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
186 if (isExternalSymbol())
187 SymbolName = new std::string(M.getSymbolName());
191 if (isExternalSymbol())
195 const MachineOperand &operator=(const MachineOperand &MO) {
196 immedVal = MO.immedVal;
200 if (isExternalSymbol())
201 SymbolName = new std::string(MO.getSymbolName());
205 // Accessor methods. Caller is responsible for checking the
206 // operand type before invoking the corresponding accessor.
208 MachineOperandType getType() const { return opType; }
210 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
211 /// indicates whether this operand should be emitted as a PC relative value
212 /// instead of a global address. This is used for operands of the forms:
213 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
215 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
218 // This is to finally stop caring whether we have a virtual or machine
219 // register -- an easier interface is to simply call both virtual and machine
220 // registers essentially the same, yet be able to distinguish when
221 // necessary. Thus the instruction selector can just add registers without
222 // abandon, and the register allocator won't be confused.
223 bool isVirtualRegister() const {
224 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
225 && regNum >= MRegisterInfo::FirstVirtualRegister;
227 bool isPhysicalRegister() const {
228 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
229 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
231 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
232 bool isMachineRegister() const { return !isVirtualRegister(); }
233 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
234 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
235 bool isImmediate() const {
236 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
238 bool isFrameIndex() const { return opType == MO_FrameIndex; }
239 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
240 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
241 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
243 Value* getVRegValue() const {
244 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
248 Value* getVRegValueOrNull() const {
249 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
250 isPCRelativeDisp()) ? value : NULL;
252 int getMachineRegNum() const {
253 assert(opType == MO_MachineRegister);
256 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
257 MachineBasicBlock *getMachineBasicBlock() const {
258 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
261 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
262 unsigned getConstantPoolIndex() const {
263 assert(isConstantPoolIndex());
267 GlobalValue *getGlobal() const {
268 assert(isGlobalAddress());
269 return (GlobalValue*)value;
272 const std::string &getSymbolName() const {
273 assert(isExternalSymbol());
277 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
278 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
279 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
280 bool opHiBits32 () const { return flags & HIFLAG32; }
281 bool opLoBits32 () const { return flags & LOFLAG32; }
282 bool opHiBits64 () const { return flags & HIFLAG64; }
283 bool opLoBits64 () const { return flags & LOFLAG64; }
285 // used to check if a machine register has been allocated to this operand
286 bool hasAllocatedReg() const {
287 return (regNum >= 0 &&
288 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
289 opType == MO_MachineRegister));
292 // used to get the reg number if when one is allocated
293 int getAllocatedRegNum() const {
294 assert(hasAllocatedReg());
298 // ********** TODO: get rid of this duplicate code! ***********
299 unsigned getReg() const {
300 return getAllocatedRegNum();
303 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
307 // Construction methods needed for fine-grain control.
308 // These must be accessed via coresponding methods in MachineInstr.
309 void markHi32() { flags |= HIFLAG32; }
310 void markLo32() { flags |= LOFLAG32; }
311 void markHi64() { flags |= HIFLAG64; }
312 void markLo64() { flags |= LOFLAG64; }
314 // Replaces the Value with its corresponding physical register after
315 // register allocation is complete
316 void setRegForValue(int reg) {
317 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
318 opType == MO_MachineRegister);
322 friend class MachineInstr;
326 //---------------------------------------------------------------------------
327 // class MachineInstr
330 // Representation of each machine instruction.
332 // MachineOpCode must be an enum, defined separately for each target.
333 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
335 // There are 2 kinds of operands:
337 // (1) Explicit operands of the machine instruction in vector operands[]
339 // (2) "Implicit operands" are values implicitly used or defined by the
340 // machine instruction, such as arguments to a CALL, return value of
341 // a CALL (if any), and return value of a RETURN.
342 //---------------------------------------------------------------------------
344 class MachineInstr: public NonCopyable { // Disable copy operations
346 MachineOpCode opCode; // the opcode
347 unsigned opCodeFlags; // flags modifying instrn behavior
348 std::vector<MachineOperand> operands; // the operands
349 unsigned numImplicitRefs; // number of implicit operands
351 // regsUsed - all machine registers used for this instruction, including regs
352 // used to save values across the instruction. This is a bitset of registers.
353 std::set<int> regsUsed;
355 // OperandComplete - Return true if it's illegal to add a new operand
356 bool OperandsComplete() const;
359 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
361 /// MachineInstr ctor - This constructor only does a _reserve_ of the
362 /// operands, not a resize for them. It is expected that if you use this that
363 /// you call add* methods below to fill up the operands, instead of the Set
364 /// methods. Eventually, the "resizing" ctors will be phased out.
366 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
368 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
369 /// the MachineInstr is created and added to the end of the specified basic
372 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
377 const MachineOpCode getOpcode() const { return opCode; }
378 const MachineOpCode getOpCode() const { return opCode; }
382 unsigned getOpCodeFlags() const { return opCodeFlags; }
385 // Access to explicit operands of the instruction
387 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
389 const MachineOperand& getOperand(unsigned i) const {
390 assert(i < getNumOperands() && "getOperand() out of range!");
393 MachineOperand& getOperand(unsigned i) {
394 assert(i < getNumOperands() && "getOperand() out of range!");
399 // Access to explicit or implicit operands of the instruction
400 // This returns the i'th entry in the operand vector.
401 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
402 // depending on whether i < N or i >= N.
404 const MachineOperand& getExplOrImplOperand(unsigned i) const {
405 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
406 return (i < getNumOperands()? getOperand(i)
407 : getImplicitOp(i - getNumOperands()));
411 // Access to implicit operands of the instruction
413 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
415 MachineOperand& getImplicitOp(unsigned i) {
416 assert(i < numImplicitRefs && "implicit ref# out of range!");
417 return operands[i + operands.size() - numImplicitRefs];
419 const MachineOperand& getImplicitOp(unsigned i) const {
420 assert(i < numImplicitRefs && "implicit ref# out of range!");
421 return operands[i + operands.size() - numImplicitRefs];
424 Value* getImplicitRef(unsigned i) {
425 return getImplicitOp(i).getVRegValue();
427 const Value* getImplicitRef(unsigned i) const {
428 return getImplicitOp(i).getVRegValue();
431 inline void addImplicitRef (Value* V,
432 bool isDef=false,bool isDefAndUse=false);
433 inline void setImplicitRef (unsigned i, Value* V,
434 bool isDef=false, bool isDefAndUse=false);
437 // Information about registers used in this instruction.
439 const std::set<int> &getRegsUsed() const {
442 bool isRegUsed(int regNum) const {
443 return regsUsed.find(regNum) != regsUsed.end();
446 // insertusedreg - Add a register to the Used registers set...
447 void insertUsedReg(unsigned Reg) {
448 regsUsed.insert((int) Reg);
454 void print(std::ostream &OS, const TargetMachine &TM) const;
456 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
459 // Define iterators to access the Value operands of the Machine Instruction.
460 // Note that these iterators only enumerate the explicit operands.
461 // begin() and end() are defined to produce these iterators...
463 template<class _MI, class _V> class ValOpIterator;
464 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
465 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
468 //===--------------------------------------------------------------------===//
469 // Accessors to add operands when building up machine instructions
472 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
475 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
476 assert(!OperandsComplete() &&
477 "Trying to add an operand to a machine instr that is already done!");
478 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
479 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
482 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
483 bool isPCRelative = false) {
484 assert(!OperandsComplete() &&
485 "Trying to add an operand to a machine instr that is already done!");
486 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
490 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
491 assert(!OperandsComplete() &&
492 "Trying to add an operand to a machine instr that is already done!");
493 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
498 /// addRegOperand - Add a symbolic virtual register reference...
500 void addRegOperand(int reg, bool isDef) {
501 assert(!OperandsComplete() &&
502 "Trying to add an operand to a machine instr that is already done!");
503 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
504 isDef ? MOTy::Def : MOTy::Use));
507 /// addRegOperand - Add a symbolic virtual register reference...
509 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
510 assert(!OperandsComplete() &&
511 "Trying to add an operand to a machine instr that is already done!");
512 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
516 /// addPCDispOperand - Add a PC relative displacement operand to the MI
518 void addPCDispOperand(Value *V) {
519 assert(!OperandsComplete() &&
520 "Trying to add an operand to a machine instr that is already done!");
521 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
525 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
527 void addMachineRegOperand(int reg, bool isDef) {
528 assert(!OperandsComplete() &&
529 "Trying to add an operand to a machine instr that is already done!");
530 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
531 isDef ? MOTy::Def : MOTy::Use));
535 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
537 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
538 assert(!OperandsComplete() &&
539 "Trying to add an operand to a machine instr that is already done!");
540 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
545 /// addZeroExtImmOperand - Add a zero extended constant argument to the
546 /// machine instruction.
548 void addZeroExtImmOperand(int64_t intValue) {
549 assert(!OperandsComplete() &&
550 "Trying to add an operand to a machine instr that is already done!");
551 operands.push_back(MachineOperand(intValue,
552 MachineOperand::MO_UnextendedImmed));
555 /// addSignExtImmOperand - Add a zero extended constant argument to the
556 /// machine instruction.
558 void addSignExtImmOperand(int64_t intValue) {
559 assert(!OperandsComplete() &&
560 "Trying to add an operand to a machine instr that is already done!");
561 operands.push_back(MachineOperand(intValue,
562 MachineOperand::MO_SignExtendedImmed));
565 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
566 assert(!OperandsComplete() &&
567 "Trying to add an operand to a machine instr that is already done!");
568 operands.push_back(MachineOperand(MBB));
571 /// addFrameIndexOperand - Add an abstract frame index to the instruction
573 void addFrameIndexOperand(unsigned Idx) {
574 assert(!OperandsComplete() &&
575 "Trying to add an operand to a machine instr that is already done!");
576 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
579 /// addConstantPoolndexOperand - Add a constant pool object index to the
582 void addConstantPoolIndexOperand(unsigned I) {
583 assert(!OperandsComplete() &&
584 "Trying to add an operand to a machine instr that is already done!");
585 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
588 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
589 assert(!OperandsComplete() &&
590 "Trying to add an operand to a machine instr that is already done!");
591 operands.push_back(MachineOperand((Value*)GV,
592 MachineOperand::MO_GlobalAddress,
593 MOTy::Use, isPCRelative));
596 /// addExternalSymbolOperand - Add an external symbol operand to this instr
598 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
599 operands.push_back(MachineOperand(SymName, isPCRelative));
602 //===--------------------------------------------------------------------===//
603 // Accessors used to modify instructions in place.
605 // FIXME: Move this stuff to MachineOperand itself!
607 /// replace - Support to rewrite a machine instruction in place: for now,
608 /// simply replace() and then set new operands with Set.*Operand methods
611 void replace(MachineOpCode Opcode, unsigned numOperands);
613 /// setOpcode - Replace the opcode of the current instruction with a new one.
615 void setOpcode(unsigned Op) { opCode = Op; }
617 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
618 /// fewer operand than it started with.
620 void RemoveOperand(unsigned i) {
621 operands.erase(operands.begin()+i);
624 // Access to set the operands when building the machine instruction
626 void SetMachineOperandVal (unsigned i,
627 MachineOperand::MachineOperandType operandType,
630 bool isDefAndUse=false);
632 void SetMachineOperandConst (unsigned i,
633 MachineOperand::MachineOperandType operandType,
636 void SetMachineOperandReg (unsigned i,
641 unsigned substituteValue(const Value* oldVal, Value* newVal,
642 bool defsOnly = true);
644 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
645 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
646 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
647 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
650 // SetRegForOperand -
651 // SetRegForImplicitRef -
652 // Mark an explicit or implicit operand with its allocated physical register.
654 void SetRegForOperand(unsigned i, int regNum);
655 void SetRegForImplicitRef(unsigned i, int regNum);
658 // Iterator to enumerate machine operands.
660 template<class MITy, class VTy>
661 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
665 void skipToNextVal() {
666 while (i < MI->getNumOperands() &&
667 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
668 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
669 && MI->getOperand(i).getVRegValue() != 0))
673 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
678 typedef ValOpIterator<MITy, VTy> _Self;
680 inline VTy operator*() const {
681 return MI->getOperand(i).getVRegValue();
684 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
685 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
687 inline VTy operator->() const { return operator*(); }
689 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
690 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
691 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
693 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
694 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
696 inline bool operator==(const _Self &y) const {
699 inline bool operator!=(const _Self &y) const {
700 return !operator==(y);
703 static _Self begin(MITy MI) {
706 static _Self end(MITy MI) {
707 return _Self(MI, MI->getNumOperands());
711 // define begin() and end()
712 val_op_iterator begin() { return val_op_iterator::begin(this); }
713 val_op_iterator end() { return val_op_iterator::end(this); }
715 const_val_op_iterator begin() const {
716 return const_val_op_iterator::begin(this);
718 const_val_op_iterator end() const {
719 return const_val_op_iterator::end(this);
724 // Define here to enable inlining of the functions used.
726 void MachineInstr::addImplicitRef(Value* V,
731 addRegOperand(V, isDef, isDefAndUse);
734 void MachineInstr::setImplicitRef(unsigned i,
739 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
740 SetMachineOperandVal(i + getNumOperands(),
741 MachineOperand::MO_VirtualRegister,
742 V, isDef, isDefAndUse);
746 //---------------------------------------------------------------------------
748 //---------------------------------------------------------------------------
750 std::ostream& operator<< (std::ostream& os,
751 const MachineInstr& minstr);
753 std::ostream& operator<< (std::ostream& os,
754 const MachineOperand& mop);
756 void PrintMachineInstructions (const Function *F);