1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
15 #include <Support/hash_set>
19 //---------------------------------------------------------------------------
20 // class MachineOperand
23 // Representation of each machine instruction operand.
24 // This class is designed so that you can allocate a vector of operands
25 // first and initialize each one later.
27 // E.g, for this VM instruction:
28 // ptr = alloca type, numElements
29 // we generate 2 machine instructions on the SPARC:
31 // mul Constant, Numelements -> Reg
32 // add %sp, Reg -> Ptr
34 // Each instruction has 3 operands, listed above. Of those:
35 // - Reg, NumElements, and Ptr are of operand type MO_Register.
36 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
38 // For the register operands, the virtual register type is as follows:
40 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
41 // MachineInstr* minstr will point to the instruction that computes reg.
43 // - %sp will be of virtual register type MO_MachineReg.
44 // The field regNum identifies the machine register.
46 // - NumElements will be of virtual register type MO_VirtualReg.
47 // The field Value* value identifies the value.
49 // - Ptr will also be of virtual register type MO_VirtualReg.
50 // Again, the field Value* value identifies the value.
52 //---------------------------------------------------------------------------
55 class MachineOperand {
57 enum MachineOperandType {
58 MO_VirtualRegister, // virtual register for *value
59 MO_MachineRegister, // pre-assigned machine register `regNum'
67 // Bit fields of the flags variable used for different operand properties
68 static const char DEFFLAG = 0x1; // this is a def of the operand
69 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
70 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
71 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
72 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
73 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
76 MachineOperandType opType;
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 int regNum; // register number for an explicit register
88 // will be set for a value after reg allocation
89 char flags; // see bit field definitions above
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType() const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
106 opType == MO_PCRelativeDisp);
109 inline Value* getVRegValueOrNull() const {
110 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
111 opType == MO_PCRelativeDisp)? value : NULL;
113 inline int getMachineRegNum() const {
114 assert(opType == MO_MachineRegister);
117 inline int64_t getImmedValue () const {
118 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
121 inline bool opIsDef () const {
122 return flags & DEFFLAG;
124 inline bool opIsDefAndUse () const {
125 return flags & DEFUSEFLAG;
127 inline bool opHiBits32 () const {
128 return flags & HIFLAG32;
130 inline bool opLoBits32 () const {
131 return flags & LOFLAG32;
133 inline bool opHiBits64 () const {
134 return flags & HIFLAG64;
136 inline bool opLoBits64 () const {
137 return flags & LOFLAG64;
140 // used to get the reg number if when one is allocated (must be
141 // called only after reg alloc)
142 inline int getAllocatedRegNum() const {
143 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
144 opType == MO_MachineRegister);
149 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
152 // These functions are provided so that a vector of operands can be
153 // statically allocated and individual ones can be initialized later.
154 // Give class MachineInstr access to these functions.
156 void Initialize (MachineOperandType operandType,
158 void InitializeConst (MachineOperandType operandType,
160 void InitializeReg (int regNum,
163 // Construction methods needed for fine-grain control.
164 // These must be accessed via coresponding methods in MachineInstr.
165 void markDef() { flags |= DEFFLAG; }
166 void markDefAndUse() { flags |= DEFUSEFLAG; }
167 void markHi32() { flags |= HIFLAG32; }
168 void markLo32() { flags |= LOFLAG32; }
169 void markHi64() { flags |= HIFLAG64; }
170 void markLo64() { flags |= LOFLAG64; }
172 // Replaces the Value with its corresponding physical register after
173 // register allocation is complete
174 void setRegForValue(int reg) {
175 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
176 opType == MO_MachineRegister);
180 friend class MachineInstr;
185 MachineOperand::MachineOperand()
186 : opType(MO_VirtualRegister),
193 MachineOperand::MachineOperand(MachineOperandType operandType,
195 : opType(operandType),
202 MachineOperand::MachineOperand(const MachineOperand& mo)
207 case MO_VirtualRegister:
208 case MO_CCRegister: value = mo.value; break;
209 case MO_MachineRegister: regNum = mo.regNum; break;
210 case MO_SignExtendedImmed:
211 case MO_UnextendedImmed:
212 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
218 MachineOperand::Initialize(MachineOperandType operandType,
221 opType = operandType;
228 MachineOperand::InitializeConst(MachineOperandType operandType,
231 opType = operandType;
239 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
241 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
243 regNum = (int) _regNum;
248 //---------------------------------------------------------------------------
249 // class MachineInstr
252 // Representation of each machine instruction.
254 // MachineOpCode must be an enum, defined separately for each target.
255 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
257 // opCodeMask is used to record variants of an instruction.
258 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
259 // ANNUL: if 1: Annul delay slot instruction.
260 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
261 // Instead of creating 4 different opcodes for BNZ, we create a single
262 // opcode and set bits in opCodeMask for each of these flags.
264 // There are 2 kinds of operands:
266 // (1) Explicit operands of the machine instruction in vector operands[]
268 // (2) "Implicit operands" are values implicitly used or defined by the
269 // machine instruction, such as arguments to a CALL, return value of
270 // a CALL (if any), and return value of a RETURN.
271 //---------------------------------------------------------------------------
273 class MachineInstr : public Annotable, // Values are annotable
274 public NonCopyable { // Disable copy operations
275 MachineOpCode opCode; // the opcode
276 OpCodeMask opCodeMask; // extra bits for variants of an opcode
277 vector<MachineOperand> operands; // the operands
278 vector<Value*> implicitRefs; // values implicitly referenced by this
279 vector<bool> implicitIsDef; // machine instruction (eg, call args)
280 vector<bool> implicitIsDefAndUse; //
281 hash_set<int> regsUsed; // all machine registers used for this
282 // instruction, including regs used
283 // to save values across the instr.
285 /*ctor*/ MachineInstr (MachineOpCode _opCode,
286 OpCodeMask _opCodeMask = 0x0);
287 /*ctor*/ MachineInstr (MachineOpCode _opCode,
288 unsigned numOperands,
289 OpCodeMask _opCodeMask = 0x0);
290 inline ~MachineInstr () {}
291 const MachineOpCode getOpCode () const { return opCode; }
294 // Information about explicit operands of the instruction
296 unsigned int getNumOperands () const { return operands.size(); }
298 bool operandIsDefined(unsigned i) const;
299 bool operandIsDefinedAndUsed(unsigned i) const;
301 const MachineOperand& getOperand (unsigned i) const;
302 MachineOperand& getOperand (unsigned i);
305 // Information about implicit operands of the instruction
307 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
309 bool implicitRefIsDefined(unsigned i) const;
310 bool implicitRefIsDefinedAndUsed(unsigned i) const;
312 const Value* getImplicitRef (unsigned i) const;
313 Value* getImplicitRef (unsigned i);
316 // Information about registers used in this instruction
318 const hash_set<int>& getRegsUsed () const { return regsUsed; }
319 hash_set<int>& getRegsUsed () { return regsUsed; }
325 friend std::ostream& operator<< (std::ostream& os,
326 const MachineInstr& minstr);
329 // Define iterators to access the Value operands of the Machine Instruction.
330 // begin() and end() are defined to produce these iterators...
332 template<class _MI, class _V> class ValOpIterator;
333 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
334 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
337 // Access to set the operands when building the machine instruction
339 void SetMachineOperandVal(unsigned i,
340 MachineOperand::MachineOperandType
344 bool isDefAndUse=false);
345 void SetMachineOperandConst(unsigned i,
346 MachineOperand::MachineOperandType
349 void SetMachineOperandReg(unsigned i, int regNum,
351 bool isDefAndUse=false,
354 void addImplicitRef (Value* val,
356 bool isDefAndUse=false);
358 void setImplicitRef (unsigned i,
361 bool isDefAndUse=false);
363 unsigned substituteValue (const Value* oldVal,
365 bool defsOnly = true);
367 void setOperandHi32 (unsigned i);
368 void setOperandLo32 (unsigned i);
369 void setOperandHi64 (unsigned i);
370 void setOperandLo64 (unsigned i);
373 // Replaces the Value for the operand with its allocated
374 // physical register after register allocation is complete.
376 void SetRegForOperand(unsigned i, int regNum);
379 // Iterator to enumerate machine operands.
381 template<class MITy, class VTy>
382 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
386 inline void skipToNextVal() {
387 while (i < MI->getNumOperands() &&
388 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
389 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
390 && MI->getOperand(i).getVRegValue() != 0))
394 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
399 typedef ValOpIterator<MITy, VTy> _Self;
401 inline VTy operator*() const {
402 return MI->getOperand(i).getVRegValue();
405 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
406 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
408 inline VTy operator->() const { return operator*(); }
410 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
411 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
413 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
414 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
416 inline bool operator==(const _Self &y) const {
419 inline bool operator!=(const _Self &y) const {
420 return !operator==(y);
423 static _Self begin(MITy MI) {
426 static _Self end(MITy MI) {
427 return _Self(MI, MI->getNumOperands());
431 // define begin() and end()
432 val_op_iterator begin() { return val_op_iterator::begin(this); }
433 val_op_iterator end() { return val_op_iterator::end(this); }
435 const_val_op_iterator begin() const {
436 return const_val_op_iterator::begin(this);
438 const_val_op_iterator end() const {
439 return const_val_op_iterator::end(this);
444 inline MachineOperand&
445 MachineInstr::getOperand(unsigned int i)
447 assert(i < operands.size() && "getOperand() out of range!");
451 inline const MachineOperand&
452 MachineInstr::getOperand(unsigned int i) const
454 assert(i < operands.size() && "getOperand() out of range!");
459 MachineInstr::operandIsDefined(unsigned int i) const
461 return getOperand(i).opIsDef();
465 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
467 return getOperand(i).opIsDefAndUse();
471 MachineInstr::implicitRefIsDefined(unsigned int i) const
473 assert(i < implicitIsDef.size() && "operand out of range!");
474 return implicitIsDef[i];
478 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
480 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
481 return implicitIsDefAndUse[i];
485 MachineInstr::getImplicitRef(unsigned int i) const
487 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
488 return implicitRefs[i];
492 MachineInstr::getImplicitRef(unsigned int i)
494 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
495 return implicitRefs[i];
499 MachineInstr::addImplicitRef(Value* val,
503 implicitRefs.push_back(val);
504 implicitIsDef.push_back(isDef);
505 implicitIsDefAndUse.push_back(isDefAndUse);
509 MachineInstr::setImplicitRef(unsigned int i,
514 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
515 implicitRefs[i] = val;
516 implicitIsDef[i] = isDef;
517 implicitIsDefAndUse[i] = isDefAndUse;
521 MachineInstr::setOperandHi32(unsigned i)
523 operands[i].markHi32();
527 MachineInstr::setOperandLo32(unsigned i)
529 operands[i].markLo32();
533 MachineInstr::setOperandHi64(unsigned i)
535 operands[i].markHi64();
539 MachineInstr::setOperandLo64(unsigned i)
541 operands[i].markLo64();
545 //---------------------------------------------------------------------------
547 //---------------------------------------------------------------------------
549 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
551 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
553 void PrintMachineInstructions(const Function *F);