1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MRegisterInfo.h"
13 #include "Support/Annotation.h"
14 #include "Support/NonCopyable.h"
15 #include "Support/iterator"
18 class MachineBasicBlock;
22 typedef int MachineOpCode;
24 /// MOTy - MachineOperandType - This namespace contains an enum that describes
25 /// how the machine operand is used by the instruction: is it read, defined, or
26 /// both? Note that the MachineInstr/Operator class currently uses bool
27 /// arguments to represent this information instead of an enum. Eventually this
28 /// should change over to use this _easier to read_ representation instead.
32 Use, /// This machine operand is only read by the instruction
33 Def, /// This machine operand is only written by the instruction
34 UseAndDef /// This machine operand is read AND written
38 //---------------------------------------------------------------------------
39 // class MachineOperand
42 // Representation of each machine instruction operand.
43 // This class is designed so that you can allocate a vector of operands
44 // first and initialize each one later.
46 // E.g, for this VM instruction:
47 // ptr = alloca type, numElements
48 // we generate 2 machine instructions on the SPARC:
50 // mul Constant, Numelements -> Reg
51 // add %sp, Reg -> Ptr
53 // Each instruction has 3 operands, listed above. Of those:
54 // - Reg, NumElements, and Ptr are of operand type MO_Register.
55 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
57 // For the register operands, the virtual register type is as follows:
59 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
60 // MachineInstr* minstr will point to the instruction that computes reg.
62 // - %sp will be of virtual register type MO_MachineReg.
63 // The field regNum identifies the machine register.
65 // - NumElements will be of virtual register type MO_VirtualReg.
66 // The field Value* value identifies the value.
68 // - Ptr will also be of virtual register type MO_VirtualReg.
69 // Again, the field Value* value identifies the value.
71 //---------------------------------------------------------------------------
73 struct MachineOperand {
74 enum MachineOperandType {
75 MO_VirtualRegister, // virtual register for *value
76 MO_MachineRegister, // pre-assigned machine register `regNum'
81 MO_MachineBasicBlock, // MachineBasicBlock reference
82 MO_FrameIndex, // Abstract Stack Frame Index
83 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
84 MO_ExternalSymbol, // Name of external global symbol
85 MO_GlobalAddress, // Address of a global value
89 // Bit fields of the flags variable used for different operand properties
91 DEFFLAG = 0x01, // this is a def of the operand
92 DEFUSEFLAG = 0x02, // this is both a def and a use
93 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
94 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
95 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
96 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
97 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
104 Value* value; // BasicBlockVal for a label operand.
105 // ConstantVal for a non-address immediate.
106 // Virtual register for an SSA operand,
107 // including hidden operands required for
108 // the generated machine code.
109 // LLVM global for MO_GlobalAddress.
111 int64_t immedVal; // Constant value for an explicit constant
113 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
114 std::string *SymbolName; // For MO_ExternalSymbol type
117 char flags; // see bit field definitions above
118 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
119 int regNum; // register number for an explicit register
120 // will be set for a value after reg allocation
125 opType(MO_VirtualRegister),
128 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
134 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
139 case MOTy::Use: flags = 0; break;
140 case MOTy::Def: flags = DEFFLAG; break;
141 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
142 default: assert(0 && "Invalid value for UseTy!");
146 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
147 bool isPCRelative = false)
148 : value(V), opType(OpTy), regNum(-1) {
150 case MOTy::Use: flags = 0; break;
151 case MOTy::Def: flags = DEFFLAG; break;
152 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
153 default: assert(0 && "Invalid value for UseTy!");
155 if (isPCRelative) flags |= PCRELATIVE;
158 MachineOperand(MachineBasicBlock *mbb)
159 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
161 MachineOperand(const std::string &SymName, bool isPCRelative)
162 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
163 opType(MO_ExternalSymbol), regNum(-1) {}
166 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
170 if (isExternalSymbol())
171 SymbolName = new std::string(M.getSymbolName());
175 if (isExternalSymbol())
179 const MachineOperand &operator=(const MachineOperand &MO) {
180 immedVal = MO.immedVal;
184 if (isExternalSymbol())
185 SymbolName = new std::string(MO.getSymbolName());
189 // Accessor methods. Caller is responsible for checking the
190 // operand type before invoking the corresponding accessor.
192 MachineOperandType getType() const { return opType; }
194 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
195 /// indicates whether this operand should be emitted as a PC relative value
196 /// instead of a global address. This is used for operands of the forms:
197 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
199 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
202 // This is to finally stop caring whether we have a virtual or machine
203 // register -- an easier interface is to simply call both virtual and machine
204 // registers essentially the same, yet be able to distinguish when
205 // necessary. Thus the instruction selector can just add registers without
206 // abandon, and the register allocator won't be confused.
207 bool isVirtualRegister() const {
208 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
209 && regNum >= MRegisterInfo::FirstVirtualRegister;
211 bool isPhysicalRegister() const {
212 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
213 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
215 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
216 bool isMachineRegister() const { return !isVirtualRegister(); }
217 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
218 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
219 bool isImmediate() const {
220 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
222 bool isFrameIndex() const { return opType == MO_FrameIndex; }
223 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
224 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
225 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
227 Value* getVRegValue() const {
228 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
232 Value* getVRegValueOrNull() const {
233 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
234 isPCRelativeDisp()) ? value : NULL;
236 int getMachineRegNum() const {
237 assert(opType == MO_MachineRegister);
240 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
241 MachineBasicBlock *getMachineBasicBlock() const {
242 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
245 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
246 unsigned getConstantPoolIndex() const {
247 assert(isConstantPoolIndex());
251 GlobalValue *getGlobal() const {
252 assert(isGlobalAddress());
253 return (GlobalValue*)value;
256 const std::string &getSymbolName() const {
257 assert(isExternalSymbol());
261 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
262 bool opIsDef () const { return flags & DEFFLAG; }
263 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
264 bool opHiBits32 () const { return flags & HIFLAG32; }
265 bool opLoBits32 () const { return flags & LOFLAG32; }
266 bool opHiBits64 () const { return flags & HIFLAG64; }
267 bool opLoBits64 () const { return flags & LOFLAG64; }
269 // used to check if a machine register has been allocated to this operand
270 bool hasAllocatedReg() const {
271 return (regNum >= 0 &&
272 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
273 opType == MO_MachineRegister));
276 // used to get the reg number if when one is allocated
277 int getAllocatedRegNum() const {
278 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
279 opType == MO_MachineRegister);
283 unsigned getReg() const {
284 assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
288 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
292 // Construction methods needed for fine-grain control.
293 // These must be accessed via coresponding methods in MachineInstr.
294 void markHi32() { flags |= HIFLAG32; }
295 void markLo32() { flags |= LOFLAG32; }
296 void markHi64() { flags |= HIFLAG64; }
297 void markLo64() { flags |= LOFLAG64; }
299 // Replaces the Value with its corresponding physical register after
300 // register allocation is complete
301 void setRegForValue(int reg) {
302 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
303 opType == MO_MachineRegister);
307 friend class MachineInstr;
311 //---------------------------------------------------------------------------
312 // class MachineInstr
315 // Representation of each machine instruction.
317 // MachineOpCode must be an enum, defined separately for each target.
318 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
320 // There are 2 kinds of operands:
322 // (1) Explicit operands of the machine instruction in vector operands[]
324 // (2) "Implicit operands" are values implicitly used or defined by the
325 // machine instruction, such as arguments to a CALL, return value of
326 // a CALL (if any), and return value of a RETURN.
327 //---------------------------------------------------------------------------
329 class MachineInstr: public NonCopyable { // Disable copy operations
331 MachineOpCode opCode; // the opcode
332 std::vector<MachineOperand> operands; // the operands
333 unsigned numImplicitRefs; // number of implicit operands
335 MachineOperand& getImplicitOp(unsigned i) {
336 assert(i < numImplicitRefs && "implicit ref# out of range!");
337 return operands[i + operands.size() - numImplicitRefs];
339 const MachineOperand& getImplicitOp(unsigned i) const {
340 assert(i < numImplicitRefs && "implicit ref# out of range!");
341 return operands[i + operands.size() - numImplicitRefs];
344 // regsUsed - all machine registers used for this instruction, including regs
345 // used to save values across the instruction. This is a bitset of registers.
346 std::vector<bool> regsUsed;
348 // OperandComplete - Return true if it's illegal to add a new operand
349 bool OperandsComplete() const;
352 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
354 /// MachineInstr ctor - This constructor only does a _reserve_ of the
355 /// operands, not a resize for them. It is expected that if you use this that
356 /// you call add* methods below to fill up the operands, instead of the Set
357 /// methods. Eventually, the "resizing" ctors will be phased out.
359 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
361 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
362 /// the MachineInstr is created and added to the end of the specified basic
365 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
370 const MachineOpCode getOpcode() const { return opCode; }
371 const MachineOpCode getOpCode() const { return opCode; }
374 // Information about explicit operands of the instruction
376 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
378 const MachineOperand& getOperand(unsigned i) const {
379 assert(i < getNumOperands() && "getOperand() out of range!");
382 MachineOperand& getOperand(unsigned i) {
383 assert(i < getNumOperands() && "getOperand() out of range!");
388 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
389 return getOperand(i).getType();
392 // FIXME: ELIMINATE: Misleading name: Definition not defined.
393 bool operandIsDefined(unsigned i) const {
394 return getOperand(i).opIsDef();
397 bool operandIsDefinedAndUsed(unsigned i) const {
398 return getOperand(i).opIsDefAndUse();
402 // Information about implicit operands of the instruction
404 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
406 const Value* getImplicitRef(unsigned i) const {
407 return getImplicitOp(i).getVRegValue();
409 Value* getImplicitRef(unsigned i) {
410 return getImplicitOp(i).getVRegValue();
413 bool implicitRefIsDefined(unsigned i) const {
414 return getImplicitOp(i).opIsDef();
416 bool implicitRefIsDefinedAndUsed(unsigned i) const {
417 return getImplicitOp(i).opIsDefAndUse();
419 inline void addImplicitRef (Value* V,
420 bool isDef=false,bool isDefAndUse=false);
421 inline void setImplicitRef (unsigned i, Value* V,
422 bool isDef=false, bool isDefAndUse=false);
425 // Information about registers used in this instruction
427 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
429 // insertUsedReg - Add a register to the Used registers set...
430 void insertUsedReg(unsigned Reg) {
431 if (Reg >= regsUsed.size())
432 regsUsed.resize(Reg+1);
433 regsUsed[Reg] = true;
439 void print(std::ostream &OS, const TargetMachine &TM) const;
441 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
444 // Define iterators to access the Value operands of the Machine Instruction.
445 // Note that these iterators only enumerate the explicit operands.
446 // begin() and end() are defined to produce these iterators...
448 template<class _MI, class _V> class ValOpIterator;
449 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
450 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
453 //===--------------------------------------------------------------------===//
454 // Accessors to add operands when building up machine instructions
457 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
460 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
461 assert(!OperandsComplete() &&
462 "Trying to add an operand to a machine instr that is already done!");
463 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
464 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
467 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
468 bool isPCRelative = false) {
469 assert(!OperandsComplete() &&
470 "Trying to add an operand to a machine instr that is already done!");
471 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
475 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
476 assert(!OperandsComplete() &&
477 "Trying to add an operand to a machine instr that is already done!");
478 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
483 /// addRegOperand - Add a symbolic virtual register reference...
485 void addRegOperand(int reg, bool isDef) {
486 assert(!OperandsComplete() &&
487 "Trying to add an operand to a machine instr that is already done!");
488 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
489 isDef ? MOTy::Def : MOTy::Use));
492 /// addRegOperand - Add a symbolic virtual register reference...
494 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
495 assert(!OperandsComplete() &&
496 "Trying to add an operand to a machine instr that is already done!");
497 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
501 /// addPCDispOperand - Add a PC relative displacement operand to the MI
503 void addPCDispOperand(Value *V) {
504 assert(!OperandsComplete() &&
505 "Trying to add an operand to a machine instr that is already done!");
506 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
510 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
512 void addMachineRegOperand(int reg, bool isDef) {
513 assert(!OperandsComplete() &&
514 "Trying to add an operand to a machine instr that is already done!");
515 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
516 isDef ? MOTy::Def : MOTy::Use));
520 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
522 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
523 assert(!OperandsComplete() &&
524 "Trying to add an operand to a machine instr that is already done!");
525 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
530 /// addZeroExtImmOperand - Add a zero extended constant argument to the
531 /// machine instruction.
533 void addZeroExtImmOperand(int64_t intValue) {
534 assert(!OperandsComplete() &&
535 "Trying to add an operand to a machine instr that is already done!");
536 operands.push_back(MachineOperand(intValue,
537 MachineOperand::MO_UnextendedImmed));
540 /// addSignExtImmOperand - Add a zero extended constant argument to the
541 /// machine instruction.
543 void addSignExtImmOperand(int64_t intValue) {
544 assert(!OperandsComplete() &&
545 "Trying to add an operand to a machine instr that is already done!");
546 operands.push_back(MachineOperand(intValue,
547 MachineOperand::MO_SignExtendedImmed));
550 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
551 assert(!OperandsComplete() &&
552 "Trying to add an operand to a machine instr that is already done!");
553 operands.push_back(MachineOperand(MBB));
556 /// addFrameIndexOperand - Add an abstract frame index to the instruction
558 void addFrameIndexOperand(unsigned Idx) {
559 assert(!OperandsComplete() &&
560 "Trying to add an operand to a machine instr that is already done!");
561 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
564 /// addConstantPoolndexOperand - Add a constant pool object index to the
567 void addConstantPoolIndexOperand(unsigned I) {
568 assert(!OperandsComplete() &&
569 "Trying to add an operand to a machine instr that is already done!");
570 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
573 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
574 assert(!OperandsComplete() &&
575 "Trying to add an operand to a machine instr that is already done!");
576 operands.push_back(MachineOperand((Value*)GV,
577 MachineOperand::MO_GlobalAddress,
578 MOTy::Use, isPCRelative));
581 /// addExternalSymbolOperand - Add an external symbol operand to this instr
583 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
584 operands.push_back(MachineOperand(SymName, isPCRelative));
587 //===--------------------------------------------------------------------===//
588 // Accessors used to modify instructions in place.
590 // FIXME: Move this stuff to MachineOperand itself!
592 /// replace - Support to rewrite a machine instruction in place: for now,
593 /// simply replace() and then set new operands with Set.*Operand methods
596 void replace(MachineOpCode Opcode, unsigned numOperands);
598 /// setOpcode - Replace the opcode of the current instruction with a new one.
600 void setOpcode(unsigned Op) { opCode = Op; }
602 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
603 /// fewer operand than it started with.
605 void RemoveOperand(unsigned i) {
606 operands.erase(operands.begin()+i);
609 // Access to set the operands when building the machine instruction
611 void SetMachineOperandVal (unsigned i,
612 MachineOperand::MachineOperandType operandType,
615 bool isDefAndUse=false);
617 void SetMachineOperandConst (unsigned i,
618 MachineOperand::MachineOperandType operandType,
621 void SetMachineOperandReg (unsigned i,
626 unsigned substituteValue(const Value* oldVal, Value* newVal,
627 bool defsOnly = true);
629 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
630 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
631 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
632 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
635 // SetRegForOperand - Replaces the Value for the operand with its allocated
636 // physical register after register allocation is complete.
638 void SetRegForOperand(unsigned i, int regNum);
641 // Iterator to enumerate machine operands.
643 template<class MITy, class VTy>
644 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
648 void skipToNextVal() {
649 while (i < MI->getNumOperands() &&
650 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
651 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
652 && MI->getOperand(i).getVRegValue() != 0))
656 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
661 typedef ValOpIterator<MITy, VTy> _Self;
663 inline VTy operator*() const {
664 return MI->getOperand(i).getVRegValue();
667 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
668 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
670 inline VTy operator->() const { return operator*(); }
672 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
673 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
675 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
676 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
678 inline bool operator==(const _Self &y) const {
681 inline bool operator!=(const _Self &y) const {
682 return !operator==(y);
685 static _Self begin(MITy MI) {
688 static _Self end(MITy MI) {
689 return _Self(MI, MI->getNumOperands());
693 // define begin() and end()
694 val_op_iterator begin() { return val_op_iterator::begin(this); }
695 val_op_iterator end() { return val_op_iterator::end(this); }
697 const_val_op_iterator begin() const {
698 return const_val_op_iterator::begin(this);
700 const_val_op_iterator end() const {
701 return const_val_op_iterator::end(this);
706 // Define here to enable inlining of the functions used.
708 void MachineInstr::addImplicitRef(Value* V,
713 addRegOperand(V, isDef, isDefAndUse);
716 void MachineInstr::setImplicitRef(unsigned i,
721 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
722 SetMachineOperandVal(i + getNumOperands(),
723 MachineOperand::MO_VirtualRegister,
724 V, isDef, isDefAndUse);
728 //---------------------------------------------------------------------------
730 //---------------------------------------------------------------------------
732 std::ostream& operator<< (std::ostream& os,
733 const MachineInstr& minstr);
735 std::ostream& operator<< (std::ostream& os,
736 const MachineOperand& mop);
738 void PrintMachineInstructions (const Function *F);