1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "Support/Annotation.h"
20 #include "Support/iterator"
27 class MachineBasicBlock;
31 typedef int MachineOpCode;
33 //===----------------------------------------------------------------------===//
34 /// Special flags on instructions that modify the opcode.
35 /// These flags are unused for now, but having them enforces that some
36 /// changes will be needed if they are used.
38 enum MachineOpCodeFlags {
39 AnnulFlag, /// 1 if annul bit is set on a branch
40 PredTakenFlag, /// 1 if branch should be predicted taken
41 PredNotTakenFlag /// 1 if branch should be predicted not taken
44 //===----------------------------------------------------------------------===//
45 /// MOTy - MachineOperandType - This namespace contains an enum that describes
46 /// how the machine operand is used by the instruction: is it read, defined, or
47 /// both? Note that the MachineInstr/Operator class currently uses bool
48 /// arguments to represent this information instead of an enum. Eventually this
49 /// should change over to use this _easier to read_ representation instead.
53 Use, /// This machine operand is only read by the instruction
54 Def, /// This machine operand is only written by the instruction
55 UseAndDef /// This machine operand is read AND written
59 //===----------------------------------------------------------------------===//
60 // class MachineOperand
63 // Representation of each machine instruction operand.
64 // This class is designed so that you can allocate a vector of operands
65 // first and initialize each one later.
67 // E.g, for this VM instruction:
68 // ptr = alloca type, numElements
69 // we generate 2 machine instructions on the SPARC:
71 // mul Constant, Numelements -> Reg
72 // add %sp, Reg -> Ptr
74 // Each instruction has 3 operands, listed above. Of those:
75 // - Reg, NumElements, and Ptr are of operand type MO_Register.
76 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
78 // For the register operands, the virtual register type is as follows:
80 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
81 // MachineInstr* minstr will point to the instruction that computes reg.
83 // - %sp will be of virtual register type MO_MachineReg.
84 // The field regNum identifies the machine register.
86 // - NumElements will be of virtual register type MO_VirtualReg.
87 // The field Value* value identifies the value.
89 // - Ptr will also be of virtual register type MO_VirtualReg.
90 // Again, the field Value* value identifies the value.
92 //===----------------------------------------------------------------------===//
94 struct MachineOperand {
95 enum MachineOperandType {
96 MO_VirtualRegister, // virtual register for *value
97 MO_MachineRegister, // pre-assigned machine register `regNum'
102 MO_MachineBasicBlock, // MachineBasicBlock reference
103 MO_FrameIndex, // Abstract Stack Frame Index
104 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
105 MO_ExternalSymbol, // Name of external global symbol
106 MO_GlobalAddress, // Address of a global value
110 // Bit fields of the flags variable used for different operand properties
112 DEFFLAG = 0x01, // this is a def of the operand
113 USEFLAG = 0x02, // this is a use of the operand
114 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
115 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
116 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
117 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
118 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
123 Value* value; // BasicBlockVal for a label operand.
124 // ConstantVal for a non-address immediate.
125 // Virtual register for an SSA operand,
126 // including hidden operands required for
127 // the generated machine code.
128 // LLVM global for MO_GlobalAddress.
130 int64_t immedVal; // Constant value for an explicit constant
132 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
133 std::string *SymbolName; // For MO_ExternalSymbol type
136 char flags; // see bit field definitions above
137 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
138 int regNum; // register number for an explicit register
139 // will be set for a value after reg allocation
144 opType(MO_VirtualRegister),
147 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
153 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
158 case MOTy::Use: flags = USEFLAG; break;
159 case MOTy::Def: flags = DEFFLAG; break;
160 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
161 default: assert(0 && "Invalid value for UseTy!");
165 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
166 bool isPCRelative = false)
167 : value(V), opType(OpTy), regNum(-1) {
169 case MOTy::Use: flags = USEFLAG; break;
170 case MOTy::Def: flags = DEFFLAG; break;
171 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
172 default: assert(0 && "Invalid value for UseTy!");
174 if (isPCRelative) flags |= PCRELATIVE;
177 MachineOperand(MachineBasicBlock *mbb)
178 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
180 MachineOperand(const std::string &SymName, bool isPCRelative)
181 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
182 opType(MO_ExternalSymbol), regNum(-1) {}
185 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
189 if (isExternalSymbol())
190 SymbolName = new std::string(M.getSymbolName());
194 if (isExternalSymbol())
198 const MachineOperand &operator=(const MachineOperand &MO) {
199 if (isExternalSymbol()) // if old operand had a symbol name,
200 delete SymbolName; // release old memory
201 immedVal = MO.immedVal;
205 if (isExternalSymbol())
206 SymbolName = new std::string(MO.getSymbolName());
210 // Accessor methods. Caller is responsible for checking the
211 // operand type before invoking the corresponding accessor.
213 MachineOperandType getType() const { return opType; }
215 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
216 /// indicates whether this operand should be emitted as a PC relative value
217 /// instead of a global address. This is used for operands of the forms:
218 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
220 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
223 /// isRegister - Return true if this operand is a register operand. The X86
224 /// backend currently can't decide whether to use MO_MR or MO_VR to represent
225 /// them, so we accept both.
227 /// Note: The sparc backend should not use this method.
229 bool isRegister() const {
230 return opType == MO_MachineRegister || opType == MO_VirtualRegister;
233 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
234 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
235 bool isImmediate() const {
236 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
238 bool isFrameIndex() const { return opType == MO_FrameIndex; }
239 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
240 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
241 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
243 Value* getVRegValue() const {
244 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
248 Value* getVRegValueOrNull() const {
249 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
250 isPCRelativeDisp()) ? value : NULL;
252 int getMachineRegNum() const {
253 assert(opType == MO_MachineRegister);
256 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
257 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
259 MachineBasicBlock *getMachineBasicBlock() const {
260 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
263 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
264 unsigned getConstantPoolIndex() const {
265 assert(isConstantPoolIndex());
269 GlobalValue *getGlobal() const {
270 assert(isGlobalAddress());
271 return (GlobalValue*)value;
274 const std::string &getSymbolName() const {
275 assert(isExternalSymbol());
279 bool isUse () const { return flags & USEFLAG; }
280 MachineOperand& setUse () { flags |= USEFLAG; return *this; }
281 bool isDef () const { return flags & DEFFLAG; }
282 MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
283 bool isHiBits32 () const { return flags & HIFLAG32; }
284 bool isLoBits32 () const { return flags & LOFLAG32; }
285 bool isHiBits64 () const { return flags & HIFLAG64; }
286 bool isLoBits64 () const { return flags & LOFLAG64; }
288 // used to check if a machine register has been allocated to this operand
289 bool hasAllocatedReg() const {
290 return (regNum >= 0 &&
291 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
292 opType == MO_MachineRegister));
295 // used to get the reg number if when one is allocated
296 int getAllocatedRegNum() const {
297 assert(hasAllocatedReg());
301 // ********** TODO: get rid of this duplicate code! ***********
302 unsigned getReg() const {
303 return getAllocatedRegNum();
305 void setReg(unsigned Reg) {
306 assert(hasAllocatedReg() && "This operand cannot have a register number!");
310 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
314 // Construction methods needed for fine-grain control.
315 // These must be accessed via coresponding methods in MachineInstr.
316 void markHi32() { flags |= HIFLAG32; }
317 void markLo32() { flags |= LOFLAG32; }
318 void markHi64() { flags |= HIFLAG64; }
319 void markLo64() { flags |= LOFLAG64; }
321 // Replaces the Value with its corresponding physical register after
322 // register allocation is complete
323 void setRegForValue(int reg) {
324 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
325 opType == MO_MachineRegister);
329 friend class MachineInstr;
333 //===----------------------------------------------------------------------===//
334 // class MachineInstr
337 // Representation of each machine instruction.
339 // MachineOpCode must be an enum, defined separately for each target.
340 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
342 // There are 2 kinds of operands:
344 // (1) Explicit operands of the machine instruction in vector operands[]
346 // (2) "Implicit operands" are values implicitly used or defined by the
347 // machine instruction, such as arguments to a CALL, return value of
348 // a CALL (if any), and return value of a RETURN.
349 //===----------------------------------------------------------------------===//
352 int opCode; // the opcode
353 unsigned opCodeFlags; // flags modifying instrn behavior
354 std::vector<MachineOperand> operands; // the operands
355 unsigned numImplicitRefs; // number of implicit operands
357 // OperandComplete - Return true if it's illegal to add a new operand
358 bool OperandsComplete() const;
360 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
361 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
363 MachineInstr(int Opcode, unsigned numOperands);
365 /// MachineInstr ctor - This constructor only does a _reserve_ of the
366 /// operands, not a resize for them. It is expected that if you use this that
367 /// you call add* methods below to fill up the operands, instead of the Set
368 /// methods. Eventually, the "resizing" ctors will be phased out.
370 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
372 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
373 /// the MachineInstr is created and added to the end of the specified basic
376 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
381 const int getOpcode() const { return opCode; }
382 const int getOpCode() const { return opCode; }
386 unsigned getOpCodeFlags() const { return opCodeFlags; }
389 // Access to explicit operands of the instruction
391 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
393 const MachineOperand& getOperand(unsigned i) const {
394 assert(i < getNumOperands() && "getOperand() out of range!");
397 MachineOperand& getOperand(unsigned i) {
398 assert(i < getNumOperands() && "getOperand() out of range!");
403 // Access to explicit or implicit operands of the instruction
404 // This returns the i'th entry in the operand vector.
405 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
406 // depending on whether i < N or i >= N.
408 const MachineOperand& getExplOrImplOperand(unsigned i) const {
409 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
410 return (i < getNumOperands()? getOperand(i)
411 : getImplicitOp(i - getNumOperands()));
415 // Access to implicit operands of the instruction
417 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
419 MachineOperand& getImplicitOp(unsigned i) {
420 assert(i < numImplicitRefs && "implicit ref# out of range!");
421 return operands[i + operands.size() - numImplicitRefs];
423 const MachineOperand& getImplicitOp(unsigned i) const {
424 assert(i < numImplicitRefs && "implicit ref# out of range!");
425 return operands[i + operands.size() - numImplicitRefs];
428 Value* getImplicitRef(unsigned i) {
429 return getImplicitOp(i).getVRegValue();
431 const Value* getImplicitRef(unsigned i) const {
432 return getImplicitOp(i).getVRegValue();
435 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
437 addRegOperand(V, isDef, isDefAndUse);
439 void setImplicitRef(unsigned i, Value* V) {
440 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
441 SetMachineOperandVal(i + getNumOperands(),
442 MachineOperand::MO_VirtualRegister, V);
448 void print(std::ostream &OS, const TargetMachine &TM) const;
450 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
453 // Define iterators to access the Value operands of the Machine Instruction.
454 // Note that these iterators only enumerate the explicit operands.
455 // begin() and end() are defined to produce these iterators...
457 template<class _MI, class _V> class ValOpIterator;
458 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
459 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
462 //===--------------------------------------------------------------------===//
463 // Accessors to add operands when building up machine instructions
466 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
469 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
470 assert(!OperandsComplete() &&
471 "Trying to add an operand to a machine instr that is already done!");
472 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
473 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
476 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
477 bool isPCRelative = false) {
478 assert(!OperandsComplete() &&
479 "Trying to add an operand to a machine instr that is already done!");
480 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
484 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
485 assert(!OperandsComplete() &&
486 "Trying to add an operand to a machine instr that is already done!");
487 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
492 /// addRegOperand - Add a symbolic virtual register reference...
494 void addRegOperand(int reg, bool isDef) {
495 assert(!OperandsComplete() &&
496 "Trying to add an operand to a machine instr that is already done!");
497 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
498 isDef ? MOTy::Def : MOTy::Use));
501 /// addRegOperand - Add a symbolic virtual register reference...
503 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
504 assert(!OperandsComplete() &&
505 "Trying to add an operand to a machine instr that is already done!");
506 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
510 /// addPCDispOperand - Add a PC relative displacement operand to the MI
512 void addPCDispOperand(Value *V) {
513 assert(!OperandsComplete() &&
514 "Trying to add an operand to a machine instr that is already done!");
515 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
519 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
521 void addMachineRegOperand(int reg, bool isDef) {
522 assert(!OperandsComplete() &&
523 "Trying to add an operand to a machine instr that is already done!");
524 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
525 isDef ? MOTy::Def : MOTy::Use));
528 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
530 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
531 assert(!OperandsComplete() &&
532 "Trying to add an operand to a machine instr that is already done!");
533 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
537 /// addZeroExtImmOperand - Add a zero extended constant argument to the
538 /// machine instruction.
540 void addZeroExtImmOperand(int64_t intValue) {
541 assert(!OperandsComplete() &&
542 "Trying to add an operand to a machine instr that is already done!");
543 operands.push_back(MachineOperand(intValue,
544 MachineOperand::MO_UnextendedImmed));
547 /// addSignExtImmOperand - Add a zero extended constant argument to the
548 /// machine instruction.
550 void addSignExtImmOperand(int64_t intValue) {
551 assert(!OperandsComplete() &&
552 "Trying to add an operand to a machine instr that is already done!");
553 operands.push_back(MachineOperand(intValue,
554 MachineOperand::MO_SignExtendedImmed));
557 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
558 assert(!OperandsComplete() &&
559 "Trying to add an operand to a machine instr that is already done!");
560 operands.push_back(MachineOperand(MBB));
563 /// addFrameIndexOperand - Add an abstract frame index to the instruction
565 void addFrameIndexOperand(unsigned Idx) {
566 assert(!OperandsComplete() &&
567 "Trying to add an operand to a machine instr that is already done!");
568 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
571 /// addConstantPoolndexOperand - Add a constant pool object index to the
574 void addConstantPoolIndexOperand(unsigned I) {
575 assert(!OperandsComplete() &&
576 "Trying to add an operand to a machine instr that is already done!");
577 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
580 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
581 assert(!OperandsComplete() &&
582 "Trying to add an operand to a machine instr that is already done!");
583 operands.push_back(MachineOperand((Value*)GV,
584 MachineOperand::MO_GlobalAddress,
585 MOTy::Use, isPCRelative));
588 /// addExternalSymbolOperand - Add an external symbol operand to this instr
590 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
591 operands.push_back(MachineOperand(SymName, isPCRelative));
594 //===--------------------------------------------------------------------===//
595 // Accessors used to modify instructions in place.
597 // FIXME: Move this stuff to MachineOperand itself!
599 /// replace - Support to rewrite a machine instruction in place: for now,
600 /// simply replace() and then set new operands with Set.*Operand methods
603 void replace(int Opcode, unsigned numOperands);
605 /// setOpcode - Replace the opcode of the current instruction with a new one.
607 void setOpcode(unsigned Op) { opCode = Op; }
609 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
610 /// fewer operand than it started with.
612 void RemoveOperand(unsigned i) {
613 operands.erase(operands.begin()+i);
616 // Access to set the operands when building the machine instruction
618 void SetMachineOperandVal (unsigned i,
619 MachineOperand::MachineOperandType operandType,
622 void SetMachineOperandConst (unsigned i,
623 MachineOperand::MachineOperandType operandType,
626 void SetMachineOperandReg(unsigned i, int regNum);
629 unsigned substituteValue(const Value* oldVal, Value* newVal,
630 bool defsOnly, bool notDefsAndUses,
631 bool& someArgsWereIgnored);
633 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
634 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
635 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
636 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
639 // SetRegForOperand -
640 // SetRegForImplicitRef -
641 // Mark an explicit or implicit operand with its allocated physical register.
643 void SetRegForOperand(unsigned i, int regNum);
644 void SetRegForImplicitRef(unsigned i, int regNum);
647 // Iterator to enumerate machine operands.
649 template<class MITy, class VTy>
650 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
654 void skipToNextVal() {
655 while (i < MI->getNumOperands() &&
656 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
657 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
658 && MI->getOperand(i).getVRegValue() != 0))
662 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
667 typedef ValOpIterator<MITy, VTy> _Self;
669 inline VTy operator*() const {
670 return MI->getOperand(i).getVRegValue();
673 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
674 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
676 inline VTy operator->() const { return operator*(); }
678 inline bool isUse() const { return MI->getOperand(i).isUse(); }
679 inline bool isDef() const { return MI->getOperand(i).isDef(); }
681 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
682 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
684 inline bool operator==(const _Self &y) const {
687 inline bool operator!=(const _Self &y) const {
688 return !operator==(y);
691 static _Self begin(MITy MI) {
694 static _Self end(MITy MI) {
695 return _Self(MI, MI->getNumOperands());
699 // define begin() and end()
700 val_op_iterator begin() { return val_op_iterator::begin(this); }
701 val_op_iterator end() { return val_op_iterator::end(this); }
703 const_val_op_iterator begin() const {
704 return const_val_op_iterator::begin(this);
706 const_val_op_iterator end() const {
707 return const_val_op_iterator::end(this);
712 //===----------------------------------------------------------------------===//
715 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
716 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
717 void PrintMachineInstructions(const Function *F);
719 } // End llvm namespace