1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MRegisterInfo.h"
13 #include "Support/Annotation.h"
14 #include "Support/iterator"
19 class MachineBasicBlock;
23 typedef int MachineOpCode;
25 //===----------------------------------------------------------------------===//
26 /// Special flags on instructions that modify the opcode.
27 /// These flags are unused for now, but having them enforces that some
28 /// changes will be needed if they are used.
30 enum MachineOpCodeFlags {
31 AnnulFlag, /// 1 if annul bit is set on a branch
32 PredTakenFlag, /// 1 if branch should be predicted taken
33 PredNotTakenFlag /// 1 if branch should be predicted not taken
36 //===----------------------------------------------------------------------===//
37 /// MOTy - MachineOperandType - This namespace contains an enum that describes
38 /// how the machine operand is used by the instruction: is it read, defined, or
39 /// both? Note that the MachineInstr/Operator class currently uses bool
40 /// arguments to represent this information instead of an enum. Eventually this
41 /// should change over to use this _easier to read_ representation instead.
45 Use, /// This machine operand is only read by the instruction
46 Def, /// This machine operand is only written by the instruction
47 UseAndDef /// This machine operand is read AND written
51 //===----------------------------------------------------------------------===//
52 // class MachineOperand
55 // Representation of each machine instruction operand.
56 // This class is designed so that you can allocate a vector of operands
57 // first and initialize each one later.
59 // E.g, for this VM instruction:
60 // ptr = alloca type, numElements
61 // we generate 2 machine instructions on the SPARC:
63 // mul Constant, Numelements -> Reg
64 // add %sp, Reg -> Ptr
66 // Each instruction has 3 operands, listed above. Of those:
67 // - Reg, NumElements, and Ptr are of operand type MO_Register.
68 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
70 // For the register operands, the virtual register type is as follows:
72 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
73 // MachineInstr* minstr will point to the instruction that computes reg.
75 // - %sp will be of virtual register type MO_MachineReg.
76 // The field regNum identifies the machine register.
78 // - NumElements will be of virtual register type MO_VirtualReg.
79 // The field Value* value identifies the value.
81 // - Ptr will also be of virtual register type MO_VirtualReg.
82 // Again, the field Value* value identifies the value.
84 //===----------------------------------------------------------------------===//
86 struct MachineOperand {
87 enum MachineOperandType {
88 MO_VirtualRegister, // virtual register for *value
89 MO_MachineRegister, // pre-assigned machine register `regNum'
94 MO_MachineBasicBlock, // MachineBasicBlock reference
95 MO_FrameIndex, // Abstract Stack Frame Index
96 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
97 MO_ExternalSymbol, // Name of external global symbol
98 MO_GlobalAddress, // Address of a global value
102 // Bit fields of the flags variable used for different operand properties
104 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
105 DEFUSEFLAG = 0x02, // this is both a def and a use
106 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
107 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
108 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
109 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
110 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
117 Value* value; // BasicBlockVal for a label operand.
118 // ConstantVal for a non-address immediate.
119 // Virtual register for an SSA operand,
120 // including hidden operands required for
121 // the generated machine code.
122 // LLVM global for MO_GlobalAddress.
124 int64_t immedVal; // Constant value for an explicit constant
126 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
127 std::string *SymbolName; // For MO_ExternalSymbol type
130 char flags; // see bit field definitions above
131 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
132 int regNum; // register number for an explicit register
133 // will be set for a value after reg allocation
138 opType(MO_VirtualRegister),
141 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
147 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
152 case MOTy::Use: flags = 0; break;
153 case MOTy::Def: flags = DEFONLYFLAG; break;
154 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
155 default: assert(0 && "Invalid value for UseTy!");
159 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
160 bool isPCRelative = false)
161 : value(V), opType(OpTy), regNum(-1) {
163 case MOTy::Use: flags = 0; break;
164 case MOTy::Def: flags = DEFONLYFLAG; break;
165 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
166 default: assert(0 && "Invalid value for UseTy!");
168 if (isPCRelative) flags |= PCRELATIVE;
171 MachineOperand(MachineBasicBlock *mbb)
172 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
174 MachineOperand(const std::string &SymName, bool isPCRelative)
175 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
176 opType(MO_ExternalSymbol), regNum(-1) {}
179 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
183 if (isExternalSymbol())
184 SymbolName = new std::string(M.getSymbolName());
188 if (isExternalSymbol())
192 const MachineOperand &operator=(const MachineOperand &MO) {
193 if (isExternalSymbol()) // if old operand had a symbol name,
194 delete SymbolName; // release old memory
195 immedVal = MO.immedVal;
199 if (isExternalSymbol())
200 SymbolName = new std::string(MO.getSymbolName());
204 // Accessor methods. Caller is responsible for checking the
205 // operand type before invoking the corresponding accessor.
207 MachineOperandType getType() const { return opType; }
209 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
210 /// indicates whether this operand should be emitted as a PC relative value
211 /// instead of a global address. This is used for operands of the forms:
212 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
214 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
217 // This is to finally stop caring whether we have a virtual or machine
218 // register -- an easier interface is to simply call both virtual and machine
219 // registers essentially the same, yet be able to distinguish when
220 // necessary. Thus the instruction selector can just add registers without
221 // abandon, and the register allocator won't be confused.
222 bool isVirtualRegister() const {
223 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
224 && regNum >= MRegisterInfo::FirstVirtualRegister;
226 bool isPhysicalRegister() const {
227 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
228 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
230 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
231 bool isMachineRegister() const { return !isVirtualRegister(); }
232 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
233 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
234 bool isImmediate() const {
235 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
237 bool isFrameIndex() const { return opType == MO_FrameIndex; }
238 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
239 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
240 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
242 Value* getVRegValue() const {
243 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
247 Value* getVRegValueOrNull() const {
248 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
249 isPCRelativeDisp()) ? value : NULL;
251 int getMachineRegNum() const {
252 assert(opType == MO_MachineRegister);
255 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
256 MachineBasicBlock *getMachineBasicBlock() const {
257 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
260 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
261 unsigned getConstantPoolIndex() const {
262 assert(isConstantPoolIndex());
266 GlobalValue *getGlobal() const {
267 assert(isGlobalAddress());
268 return (GlobalValue*)value;
271 const std::string &getSymbolName() const {
272 assert(isExternalSymbol());
276 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
277 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
278 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
279 bool opHiBits32 () const { return flags & HIFLAG32; }
280 bool opLoBits32 () const { return flags & LOFLAG32; }
281 bool opHiBits64 () const { return flags & HIFLAG64; }
282 bool opLoBits64 () const { return flags & LOFLAG64; }
284 // used to check if a machine register has been allocated to this operand
285 bool hasAllocatedReg() const {
286 return (regNum >= 0 &&
287 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
288 opType == MO_MachineRegister));
291 // used to get the reg number if when one is allocated
292 int getAllocatedRegNum() const {
293 assert(hasAllocatedReg());
297 // ********** TODO: get rid of this duplicate code! ***********
298 unsigned getReg() const {
299 return getAllocatedRegNum();
302 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
306 // Construction methods needed for fine-grain control.
307 // These must be accessed via coresponding methods in MachineInstr.
308 void markHi32() { flags |= HIFLAG32; }
309 void markLo32() { flags |= LOFLAG32; }
310 void markHi64() { flags |= HIFLAG64; }
311 void markLo64() { flags |= LOFLAG64; }
313 // Replaces the Value with its corresponding physical register after
314 // register allocation is complete
315 void setRegForValue(int reg) {
316 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
317 opType == MO_MachineRegister);
321 friend class MachineInstr;
325 //===----------------------------------------------------------------------===//
326 // class MachineInstr
329 // Representation of each machine instruction.
331 // MachineOpCode must be an enum, defined separately for each target.
332 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
334 // There are 2 kinds of operands:
336 // (1) Explicit operands of the machine instruction in vector operands[]
338 // (2) "Implicit operands" are values implicitly used or defined by the
339 // machine instruction, such as arguments to a CALL, return value of
340 // a CALL (if any), and return value of a RETURN.
341 //===----------------------------------------------------------------------===//
344 int opCode; // the opcode
345 unsigned opCodeFlags; // flags modifying instrn behavior
346 std::vector<MachineOperand> operands; // the operands
347 unsigned numImplicitRefs; // number of implicit operands
349 // regsUsed - all machine registers used for this instruction, including regs
350 // used to save values across the instruction. This is a bitset of registers.
351 std::set<int> regsUsed;
353 // OperandComplete - Return true if it's illegal to add a new operand
354 bool OperandsComplete() const;
356 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
357 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
359 MachineInstr(int Opcode, unsigned numOperands);
361 /// MachineInstr ctor - This constructor only does a _reserve_ of the
362 /// operands, not a resize for them. It is expected that if you use this that
363 /// you call add* methods below to fill up the operands, instead of the Set
364 /// methods. Eventually, the "resizing" ctors will be phased out.
366 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
368 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
369 /// the MachineInstr is created and added to the end of the specified basic
372 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
377 const int getOpcode() const { return opCode; }
378 const int getOpCode() const { return opCode; }
382 unsigned getOpCodeFlags() const { return opCodeFlags; }
385 // Access to explicit operands of the instruction
387 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
389 const MachineOperand& getOperand(unsigned i) const {
390 assert(i < getNumOperands() && "getOperand() out of range!");
393 MachineOperand& getOperand(unsigned i) {
394 assert(i < getNumOperands() && "getOperand() out of range!");
399 // Access to explicit or implicit operands of the instruction
400 // This returns the i'th entry in the operand vector.
401 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
402 // depending on whether i < N or i >= N.
404 const MachineOperand& getExplOrImplOperand(unsigned i) const {
405 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
406 return (i < getNumOperands()? getOperand(i)
407 : getImplicitOp(i - getNumOperands()));
411 // Access to implicit operands of the instruction
413 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
415 MachineOperand& getImplicitOp(unsigned i) {
416 assert(i < numImplicitRefs && "implicit ref# out of range!");
417 return operands[i + operands.size() - numImplicitRefs];
419 const MachineOperand& getImplicitOp(unsigned i) const {
420 assert(i < numImplicitRefs && "implicit ref# out of range!");
421 return operands[i + operands.size() - numImplicitRefs];
424 Value* getImplicitRef(unsigned i) {
425 return getImplicitOp(i).getVRegValue();
427 const Value* getImplicitRef(unsigned i) const {
428 return getImplicitOp(i).getVRegValue();
431 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
433 addRegOperand(V, isDef, isDefAndUse);
435 void setImplicitRef(unsigned i, Value* V) {
436 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
437 SetMachineOperandVal(i + getNumOperands(),
438 MachineOperand::MO_VirtualRegister, V);
442 // Information about registers used in this instruction.
444 const std::set<int> &getRegsUsed() const {
447 void insertUsedReg(unsigned Reg) {
448 assert(((int) Reg) >= 0 && "Invalid register being marked as used");
449 regsUsed.insert((int) Reg);
455 void print(std::ostream &OS, const TargetMachine &TM) const;
457 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
460 // Define iterators to access the Value operands of the Machine Instruction.
461 // Note that these iterators only enumerate the explicit operands.
462 // begin() and end() are defined to produce these iterators...
464 template<class _MI, class _V> class ValOpIterator;
465 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
466 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
469 //===--------------------------------------------------------------------===//
470 // Accessors to add operands when building up machine instructions
473 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
476 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
477 assert(!OperandsComplete() &&
478 "Trying to add an operand to a machine instr that is already done!");
479 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
480 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
483 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
484 bool isPCRelative = false) {
485 assert(!OperandsComplete() &&
486 "Trying to add an operand to a machine instr that is already done!");
487 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
491 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
492 assert(!OperandsComplete() &&
493 "Trying to add an operand to a machine instr that is already done!");
494 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
499 /// addRegOperand - Add a symbolic virtual register reference...
501 void addRegOperand(int reg, bool isDef) {
502 assert(!OperandsComplete() &&
503 "Trying to add an operand to a machine instr that is already done!");
504 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
505 isDef ? MOTy::Def : MOTy::Use));
508 /// addRegOperand - Add a symbolic virtual register reference...
510 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
511 assert(!OperandsComplete() &&
512 "Trying to add an operand to a machine instr that is already done!");
513 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
517 /// addPCDispOperand - Add a PC relative displacement operand to the MI
519 void addPCDispOperand(Value *V) {
520 assert(!OperandsComplete() &&
521 "Trying to add an operand to a machine instr that is already done!");
522 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
526 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
528 void addMachineRegOperand(int reg, bool isDef) {
529 assert(!OperandsComplete() &&
530 "Trying to add an operand to a machine instr that is already done!");
531 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
532 isDef ? MOTy::Def : MOTy::Use));
536 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
538 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
539 assert(!OperandsComplete() &&
540 "Trying to add an operand to a machine instr that is already done!");
541 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
546 /// addZeroExtImmOperand - Add a zero extended constant argument to the
547 /// machine instruction.
549 void addZeroExtImmOperand(int64_t intValue) {
550 assert(!OperandsComplete() &&
551 "Trying to add an operand to a machine instr that is already done!");
552 operands.push_back(MachineOperand(intValue,
553 MachineOperand::MO_UnextendedImmed));
556 /// addSignExtImmOperand - Add a zero extended constant argument to the
557 /// machine instruction.
559 void addSignExtImmOperand(int64_t intValue) {
560 assert(!OperandsComplete() &&
561 "Trying to add an operand to a machine instr that is already done!");
562 operands.push_back(MachineOperand(intValue,
563 MachineOperand::MO_SignExtendedImmed));
566 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
567 assert(!OperandsComplete() &&
568 "Trying to add an operand to a machine instr that is already done!");
569 operands.push_back(MachineOperand(MBB));
572 /// addFrameIndexOperand - Add an abstract frame index to the instruction
574 void addFrameIndexOperand(unsigned Idx) {
575 assert(!OperandsComplete() &&
576 "Trying to add an operand to a machine instr that is already done!");
577 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
580 /// addConstantPoolndexOperand - Add a constant pool object index to the
583 void addConstantPoolIndexOperand(unsigned I) {
584 assert(!OperandsComplete() &&
585 "Trying to add an operand to a machine instr that is already done!");
586 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
589 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
590 assert(!OperandsComplete() &&
591 "Trying to add an operand to a machine instr that is already done!");
592 operands.push_back(MachineOperand((Value*)GV,
593 MachineOperand::MO_GlobalAddress,
594 MOTy::Use, isPCRelative));
597 /// addExternalSymbolOperand - Add an external symbol operand to this instr
599 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
600 operands.push_back(MachineOperand(SymName, isPCRelative));
603 //===--------------------------------------------------------------------===//
604 // Accessors used to modify instructions in place.
606 // FIXME: Move this stuff to MachineOperand itself!
608 /// replace - Support to rewrite a machine instruction in place: for now,
609 /// simply replace() and then set new operands with Set.*Operand methods
612 void replace(int Opcode, unsigned numOperands);
614 /// setOpcode - Replace the opcode of the current instruction with a new one.
616 void setOpcode(unsigned Op) { opCode = Op; }
618 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
619 /// fewer operand than it started with.
621 void RemoveOperand(unsigned i) {
622 operands.erase(operands.begin()+i);
625 // Access to set the operands when building the machine instruction
627 void SetMachineOperandVal (unsigned i,
628 MachineOperand::MachineOperandType operandType,
631 void SetMachineOperandConst (unsigned i,
632 MachineOperand::MachineOperandType operandType,
635 void SetMachineOperandReg(unsigned i, int regNum);
638 unsigned substituteValue(const Value* oldVal, Value* newVal,
639 bool defsOnly, bool notDefsAndUses,
640 bool& someArgsWereIgnored);
642 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
643 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
644 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
645 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
648 // SetRegForOperand -
649 // SetRegForImplicitRef -
650 // Mark an explicit or implicit operand with its allocated physical register.
652 void SetRegForOperand(unsigned i, int regNum);
653 void SetRegForImplicitRef(unsigned i, int regNum);
656 // Iterator to enumerate machine operands.
658 template<class MITy, class VTy>
659 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
663 void skipToNextVal() {
664 while (i < MI->getNumOperands() &&
665 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
666 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
667 && MI->getOperand(i).getVRegValue() != 0))
671 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
676 typedef ValOpIterator<MITy, VTy> _Self;
678 inline VTy operator*() const {
679 return MI->getOperand(i).getVRegValue();
682 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
683 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
685 inline VTy operator->() const { return operator*(); }
687 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
688 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
689 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
691 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
692 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
694 inline bool operator==(const _Self &y) const {
697 inline bool operator!=(const _Self &y) const {
698 return !operator==(y);
701 static _Self begin(MITy MI) {
704 static _Self end(MITy MI) {
705 return _Self(MI, MI->getNumOperands());
709 // define begin() and end()
710 val_op_iterator begin() { return val_op_iterator::begin(this); }
711 val_op_iterator end() { return val_op_iterator::end(this); }
713 const_val_op_iterator begin() const {
714 return const_val_op_iterator::begin(this);
716 const_val_op_iterator end() const {
717 return const_val_op_iterator::end(this);
722 //===----------------------------------------------------------------------===//
725 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
726 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
727 void PrintMachineInstructions(const Function *F);