1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MachineInstrInfo.h"
13 #include "llvm/Annotation.h"
14 #include <Support/iterator>
15 #include <Support/hash_set>
19 //---------------------------------------------------------------------------
20 // class MachineOperand
23 // Representation of each machine instruction operand.
24 // This class is designed so that you can allocate a vector of operands
25 // first and initialize each one later.
27 // E.g, for this VM instruction:
28 // ptr = alloca type, numElements
29 // we generate 2 machine instructions on the SPARC:
31 // mul Constant, Numelements -> Reg
32 // add %sp, Reg -> Ptr
34 // Each instruction has 3 operands, listed above. Of those:
35 // - Reg, NumElements, and Ptr are of operand type MO_Register.
36 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
38 // For the register operands, the virtual register type is as follows:
40 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
41 // MachineInstr* minstr will point to the instruction that computes reg.
43 // - %sp will be of virtual register type MO_MachineReg.
44 // The field regNum identifies the machine register.
46 // - NumElements will be of virtual register type MO_VirtualReg.
47 // The field Value* value identifies the value.
49 // - Ptr will also be of virtual register type MO_VirtualReg.
50 // Again, the field Value* value identifies the value.
52 //---------------------------------------------------------------------------
55 class MachineOperand {
57 enum MachineOperandType {
58 MO_VirtualRegister, // virtual register for *value
59 MO_MachineRegister, // pre-assigned machine register `regNum'
67 // Bit fields of the flags variable used for different operand properties
68 static const char DEFFLAG = 0x1; // this is a def of the operand
69 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
70 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
71 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
72 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
73 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
76 MachineOperandType opType;
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 int regNum; // register number for an explicit register
88 // will be set for a value after reg allocation
89 char flags; // see bit field definitions above
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType() const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
106 opType == MO_PCRelativeDisp);
109 inline Value* getVRegValueOrNull() const {
110 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
111 opType == MO_PCRelativeDisp)? value : NULL;
113 inline int getMachineRegNum() const {
114 assert(opType == MO_MachineRegister);
117 inline int64_t getImmedValue () const {
118 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
121 inline bool opIsDef () const {
122 return flags & DEFFLAG;
124 inline bool opIsDefAndUse () const {
125 return flags & DEFUSEFLAG;
127 inline bool opHiBits32 () const {
128 return flags & HIFLAG32;
130 inline bool opLoBits32 () const {
131 return flags & LOFLAG32;
133 inline bool opHiBits64 () const {
134 return flags & HIFLAG64;
136 inline bool opLoBits64 () const {
137 return flags & LOFLAG64;
140 // used to check if a machine register has been allocated to this operand
141 inline bool hasAllocatedReg() const {
142 return (regNum >= 0 &&
143 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
144 opType == MO_MachineRegister));
147 // used to get the reg number if when one is allocated
148 inline int getAllocatedRegNum() const {
149 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
150 opType == MO_MachineRegister);
156 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
159 // These functions are provided so that a vector of operands can be
160 // statically allocated and individual ones can be initialized later.
161 // Give class MachineInstr access to these functions.
163 void Initialize (MachineOperandType operandType,
165 void InitializeConst (MachineOperandType operandType,
167 void InitializeReg (int regNum,
170 // Construction methods needed for fine-grain control.
171 // These must be accessed via coresponding methods in MachineInstr.
172 void markDef() { flags |= DEFFLAG; }
173 void markDefAndUse() { flags |= DEFUSEFLAG; }
174 void markHi32() { flags |= HIFLAG32; }
175 void markLo32() { flags |= LOFLAG32; }
176 void markHi64() { flags |= HIFLAG64; }
177 void markLo64() { flags |= LOFLAG64; }
179 // Replaces the Value with its corresponding physical register after
180 // register allocation is complete
181 void setRegForValue(int reg) {
182 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
183 opType == MO_MachineRegister);
187 friend class MachineInstr;
192 MachineOperand::MachineOperand()
193 : opType(MO_VirtualRegister),
200 MachineOperand::MachineOperand(MachineOperandType operandType,
202 : opType(operandType),
209 MachineOperand::MachineOperand(const MachineOperand& mo)
214 case MO_VirtualRegister:
215 case MO_CCRegister: value = mo.value; break;
216 case MO_MachineRegister: regNum = mo.regNum; break;
217 case MO_SignExtendedImmed:
218 case MO_UnextendedImmed:
219 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
225 MachineOperand::Initialize(MachineOperandType operandType,
228 opType = operandType;
235 MachineOperand::InitializeConst(MachineOperandType operandType,
238 opType = operandType;
246 MachineOperand::InitializeReg(int _regNum, bool isCCReg)
248 opType = isCCReg? MO_CCRegister : MO_MachineRegister;
250 regNum = (int) _regNum;
255 //---------------------------------------------------------------------------
256 // class MachineInstr
259 // Representation of each machine instruction.
261 // MachineOpCode must be an enum, defined separately for each target.
262 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
264 // opCodeMask is used to record variants of an instruction.
265 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
266 // ANNUL: if 1: Annul delay slot instruction.
267 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
268 // Instead of creating 4 different opcodes for BNZ, we create a single
269 // opcode and set bits in opCodeMask for each of these flags.
271 // There are 2 kinds of operands:
273 // (1) Explicit operands of the machine instruction in vector operands[]
275 // (2) "Implicit operands" are values implicitly used or defined by the
276 // machine instruction, such as arguments to a CALL, return value of
277 // a CALL (if any), and return value of a RETURN.
278 //---------------------------------------------------------------------------
280 class MachineInstr : public Annotable, // Values are annotable
281 public NonCopyable { // Disable copy operations
282 MachineOpCode opCode; // the opcode
283 OpCodeMask opCodeMask; // extra bits for variants of an opcode
284 vector<MachineOperand> operands; // the operands
285 vector<Value*> implicitRefs; // values implicitly referenced by this
286 vector<bool> implicitIsDef; // machine instruction (eg, call args)
287 vector<bool> implicitIsDefAndUse; //
288 hash_set<int> regsUsed; // all machine registers used for this
289 // instruction, including regs used
290 // to save values across the instr.
292 /*ctor*/ MachineInstr (MachineOpCode _opCode,
293 OpCodeMask _opCodeMask = 0x0);
294 /*ctor*/ MachineInstr (MachineOpCode _opCode,
295 unsigned numOperands,
296 OpCodeMask _opCodeMask = 0x0);
297 inline ~MachineInstr () {}
300 // Support to rewrite a machine instruction in place: for now, simply
301 // replace() and then set new operands with Set.*Operand methods below.
303 void replace (MachineOpCode _opCode,
304 unsigned numOperands,
305 OpCodeMask _opCodeMask = 0x0);
308 // The op code. Note that MachineOpCode is a target-specific type.
310 const MachineOpCode getOpCode () const { return opCode; }
313 // Information about explicit operands of the instruction
315 unsigned int getNumOperands () const { return operands.size(); }
317 bool operandIsDefined(unsigned i) const;
318 bool operandIsDefinedAndUsed(unsigned i) const;
320 const MachineOperand& getOperand (unsigned i) const;
321 MachineOperand& getOperand (unsigned i);
324 // Information about implicit operands of the instruction
326 unsigned getNumImplicitRefs() const{return implicitRefs.size();}
328 bool implicitRefIsDefined(unsigned i) const;
329 bool implicitRefIsDefinedAndUsed(unsigned i) const;
331 const Value* getImplicitRef (unsigned i) const;
332 Value* getImplicitRef (unsigned i);
335 // Information about registers used in this instruction
337 const hash_set<int>& getRegsUsed () const { return regsUsed; }
338 hash_set<int>& getRegsUsed () { return regsUsed; }
344 friend std::ostream& operator<< (std::ostream& os,
345 const MachineInstr& minstr);
348 // Define iterators to access the Value operands of the Machine Instruction.
349 // begin() and end() are defined to produce these iterators...
351 template<class _MI, class _V> class ValOpIterator;
352 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
353 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
356 // Access to set the operands when building the machine instruction
358 void SetMachineOperandVal(unsigned i,
359 MachineOperand::MachineOperandType
363 bool isDefAndUse=false);
364 void SetMachineOperandConst(unsigned i,
365 MachineOperand::MachineOperandType
368 void SetMachineOperandReg(unsigned i, int regNum,
370 bool isDefAndUse=false,
373 void addImplicitRef (Value* val,
375 bool isDefAndUse=false);
377 void setImplicitRef (unsigned i,
380 bool isDefAndUse=false);
382 unsigned substituteValue (const Value* oldVal,
384 bool defsOnly = true);
386 void setOperandHi32 (unsigned i);
387 void setOperandLo32 (unsigned i);
388 void setOperandHi64 (unsigned i);
389 void setOperandLo64 (unsigned i);
392 // Replaces the Value for the operand with its allocated
393 // physical register after register allocation is complete.
395 void SetRegForOperand(unsigned i, int regNum);
398 // Iterator to enumerate machine operands.
400 template<class MITy, class VTy>
401 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
405 inline void skipToNextVal() {
406 while (i < MI->getNumOperands() &&
407 !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
408 MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
409 && MI->getOperand(i).getVRegValue() != 0))
413 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
418 typedef ValOpIterator<MITy, VTy> _Self;
420 inline VTy operator*() const {
421 return MI->getOperand(i).getVRegValue();
424 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
425 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
427 inline VTy operator->() const { return operator*(); }
429 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
430 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
432 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
433 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
435 inline bool operator==(const _Self &y) const {
438 inline bool operator!=(const _Self &y) const {
439 return !operator==(y);
442 static _Self begin(MITy MI) {
445 static _Self end(MITy MI) {
446 return _Self(MI, MI->getNumOperands());
450 // define begin() and end()
451 val_op_iterator begin() { return val_op_iterator::begin(this); }
452 val_op_iterator end() { return val_op_iterator::end(this); }
454 const_val_op_iterator begin() const {
455 return const_val_op_iterator::begin(this);
457 const_val_op_iterator end() const {
458 return const_val_op_iterator::end(this);
463 inline MachineOperand&
464 MachineInstr::getOperand(unsigned int i)
466 assert(i < operands.size() && "getOperand() out of range!");
470 inline const MachineOperand&
471 MachineInstr::getOperand(unsigned int i) const
473 assert(i < operands.size() && "getOperand() out of range!");
478 MachineInstr::operandIsDefined(unsigned int i) const
480 return getOperand(i).opIsDef();
484 MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
486 return getOperand(i).opIsDefAndUse();
490 MachineInstr::implicitRefIsDefined(unsigned int i) const
492 assert(i < implicitIsDef.size() && "operand out of range!");
493 return implicitIsDef[i];
497 MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
499 assert(i < implicitIsDefAndUse.size() && "operand out of range!");
500 return implicitIsDefAndUse[i];
504 MachineInstr::getImplicitRef(unsigned int i) const
506 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
507 return implicitRefs[i];
511 MachineInstr::getImplicitRef(unsigned int i)
513 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
514 return implicitRefs[i];
518 MachineInstr::addImplicitRef(Value* val,
522 implicitRefs.push_back(val);
523 implicitIsDef.push_back(isDef);
524 implicitIsDefAndUse.push_back(isDefAndUse);
528 MachineInstr::setImplicitRef(unsigned int i,
533 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
534 implicitRefs[i] = val;
535 implicitIsDef[i] = isDef;
536 implicitIsDefAndUse[i] = isDefAndUse;
540 MachineInstr::setOperandHi32(unsigned i)
542 operands[i].markHi32();
546 MachineInstr::setOperandLo32(unsigned i)
548 operands[i].markLo32();
552 MachineInstr::setOperandHi64(unsigned i)
554 operands[i].markHi64();
558 MachineInstr::setOperandLo64(unsigned i)
560 operands[i].markLo64();
564 //---------------------------------------------------------------------------
566 //---------------------------------------------------------------------------
568 std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
570 std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
572 void PrintMachineInstructions(const Function *F);