2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/Target/MachineInstrInfo.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
63 class MachineOperand {
65 enum MachineOperandType {
66 MO_VirtualRegister, // virtual register for *value
67 MO_MachineRegister, // pre-assigned machine register `regNum'
75 MachineOperandType opType;
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
83 int64_t immedVal; // constant value for an explicit constant
86 unsigned regNum; // register number for an explicit register
87 // will be set for a value after reg allocation
88 bool isDef; // is this a defition for the value
91 /*ctor*/ MachineOperand ();
92 /*ctor*/ MachineOperand (MachineOperandType operandType,
94 /*copy ctor*/ MachineOperand (const MachineOperand&);
95 /*dtor*/ ~MachineOperand () {}
97 // Accessor methods. Caller is responsible for checking the
98 // operand type before invoking the corresponding accessor.
100 inline MachineOperandType getOperandType () const {
103 inline Value* getVRegValue () const {
104 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
105 opType == MO_PCRelativeDisp);
108 inline unsigned int getMachineRegNum() const {
109 assert(opType == MO_MachineRegister);
112 inline int64_t getImmedValue () const {
113 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
116 inline bool opIsDef () const {
121 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
125 // These functions are provided so that a vector of operands can be
126 // statically allocated and individual ones can be initialized later.
127 // Give class MachineInstr gets access to these functions.
129 void Initialize (MachineOperandType operandType,
131 void InitializeConst (MachineOperandType operandType,
133 void InitializeReg (unsigned int regNum);
135 friend class MachineInstr;
136 friend class ValOpIterator<const MachineInstr, const Value>;
137 friend class ValOpIterator< MachineInstr, Value>;
142 // replaces the Value with its corresponding physical register afeter
143 // register allocation is complete
144 void setRegForValue(int reg) {
145 assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
149 // used to get the reg number if when one is allocted (must be
150 // called only after reg alloc)
151 inline unsigned getAllocatedRegNum() const {
152 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
153 opType == MO_MachineRegister);
162 MachineOperand::MachineOperand()
163 : opType(MO_VirtualRegister),
171 MachineOperand::MachineOperand(MachineOperandType operandType,
173 : opType(operandType),
181 MachineOperand::MachineOperand(const MachineOperand& mo)
186 case MO_VirtualRegister:
187 case MO_CCRegister: value = mo.value; break;
188 case MO_MachineRegister: regNum = mo.regNum; break;
189 case MO_SignExtendedImmed:
190 case MO_UnextendedImmed:
191 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
197 MachineOperand::Initialize(MachineOperandType operandType,
200 opType = operandType;
205 MachineOperand::InitializeConst(MachineOperandType operandType,
208 opType = operandType;
214 MachineOperand::InitializeReg(unsigned int _regNum)
216 opType = MO_MachineRegister;
222 //---------------------------------------------------------------------------
223 // class MachineInstr
226 // Representation of each machine instruction.
228 // MachineOpCode must be an enum, defined separately for each target.
229 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
231 // opCodeMask is used to record variants of an instruction.
232 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
233 // ANNUL: if 1: Annul delay slot instruction.
234 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
235 // Instead of creating 4 different opcodes for BNZ, we create a single
236 // opcode and set bits in opCodeMask for each of these flags.
237 //---------------------------------------------------------------------------
239 class MachineInstr : public NonCopyable {
241 MachineOpCode opCode;
242 OpCodeMask opCodeMask; // extra bits for variants of an opcode
243 vector<MachineOperand> operands;
246 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
247 typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
250 /*ctor*/ MachineInstr (MachineOpCode _opCode,
251 OpCodeMask _opCodeMask = 0x0);
252 /*ctor*/ MachineInstr (MachineOpCode _opCode,
253 unsigned numOperands,
254 OpCodeMask _opCodeMask = 0x0);
255 inline ~MachineInstr () {}
257 const MachineOpCode getOpCode () const;
259 unsigned int getNumOperands () const;
261 const MachineOperand& getOperand (unsigned int i) const;
262 MachineOperand& getOperand (unsigned int i);
264 bool operandIsDefined(unsigned int i) const;
266 void dump (unsigned int indent = 0) const;
273 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
274 friend val_op_const_iterator;
275 friend val_op_iterator;
278 // Access to set the operands when building the machine instruction
279 void SetMachineOperand(unsigned int i,
280 MachineOperand::MachineOperandType operandType,
281 Value* _val, bool isDef=false);
282 void SetMachineOperand(unsigned int i,
283 MachineOperand::MachineOperandType operandType,
284 int64_t intValue, bool isDef=false);
285 void SetMachineOperand(unsigned int i,
290 inline const MachineOpCode
291 MachineInstr::getOpCode() const
297 MachineInstr::getNumOperands() const
299 return operands.size();
302 inline MachineOperand&
303 MachineInstr::getOperand(unsigned int i)
305 assert(i < operands.size() && "getOperand() out of range!");
309 inline const MachineOperand&
310 MachineInstr::getOperand(unsigned int i) const
312 assert(i < operands.size() && "getOperand() out of range!");
317 MachineInstr::operandIsDefined(unsigned int i) const
319 return getOperand(i).opIsDef();
323 template<class _MI, class _V>
324 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
330 inline void skipToNextVal() {
331 while (i < minstr->getNumOperands() &&
332 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
333 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
334 && minstr->operands[i].value != NULL))
339 typedef ValOpIterator<_MI, _V> _Self;
341 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
342 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
346 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
348 const MachineOperand & getMachineOperand() const { return minstr->getOperand(i); }
350 inline _V* operator->() const { return operator*(); }
351 // inline bool isDef () const { return (((int) i) == resultPos); }
353 inline bool isDef () const { return minstr->getOperand(i).isDef; }
354 inline bool done () const { return (i == minstr->getNumOperands()); }
356 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
357 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
361 //---------------------------------------------------------------------------
362 // class MachineCodeForVMInstr
365 // Representation of the sequence of machine instructions created
366 // for a single VM instruction. Additionally records any temporary
367 // "values" used as intermediate values in this sequence.
368 // Note that such values should be treated as pure SSA values with
369 // no interpretation of their operands (i.e., as a TmpInstruction object
370 // which actually represents such a value).
372 //---------------------------------------------------------------------------
374 class MachineCodeForVMInstr: public vector<MachineInstr*>
377 vector<Value*> tempVec;
380 /*ctor*/ MachineCodeForVMInstr () {}
381 /*ctor*/ ~MachineCodeForVMInstr ();
383 const vector<Value*>&
384 getTempValues () const { return tempVec; }
386 void addTempValue (Value* val)
387 { tempVec.push_back(val); }
389 // dropAllReferences() - This function drops all references within
390 // temporary (hidden) instructions created in implementing the original
391 // VM intruction. This ensures there are no remaining "uses" within
392 // these hidden instructions, before the values of a method are freed.
394 // Make this inline because it has to be called from class Instruction
395 // and inlining it avoids a serious circurality in link order.
396 inline void dropAllReferences() {
397 for (unsigned i=0, N=tempVec.size(); i < N; i++)
398 if (Instruction *I = tempVec[i]->castInstruction())
399 I->dropAllReferences();
404 MachineCodeForVMInstr::~MachineCodeForVMInstr()
406 // Free the Value objects created to hold intermediate values
407 for (unsigned i=0, N=tempVec.size(); i < N; i++)
410 // Free the MachineInstr objects allocated, if any.
411 for (unsigned i=0, N=this->size(); i < N; i++)
416 //---------------------------------------------------------------------------
417 // class MachineCodeForBasicBlock
420 // Representation of the sequence of machine instructions created
421 // for a basic block.
422 //---------------------------------------------------------------------------
425 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
427 typedef vector<MachineInstr*>::iterator iterator;
428 typedef vector<const MachineInstr*>::const_iterator const_iterator;
432 //---------------------------------------------------------------------------
433 // Target-independent utility routines for creating machine instructions
434 //---------------------------------------------------------------------------
437 //------------------------------------------------------------------------
438 // Function Set2OperandsFromInstr
439 // Function Set3OperandsFromInstr
441 // For the common case of 2- and 3-operand arithmetic/logical instructions,
442 // set the m/c instr. operands directly from the VM instruction's operands.
443 // Check whether the first or second operand is 0 and can use a dedicated
445 // Check whether the second operand should use an immediate field or register.
446 // (First and third operands are never immediates for such instructions.)
449 // canDiscardResult: Specifies that the result operand can be discarded
450 // by using the dedicated "0"
452 // op1position, op2position and resultPosition: Specify in which position
453 // in the machine instruction the 3 operands (arg1, arg2
454 // and result) should go.
456 // RETURN VALUE: unsigned int flags, where
457 // flags & 0x01 => operand 1 is constant and needs a register
458 // flags & 0x02 => operand 2 is constant and needs a register
459 //------------------------------------------------------------------------
461 void Set2OperandsFromInstr (MachineInstr* minstr,
462 InstructionNode* vmInstrNode,
463 const TargetMachine& targetMachine,
464 bool canDiscardResult = false,
466 int resultPosition = 1);
468 void Set3OperandsFromInstr (MachineInstr* minstr,
469 InstructionNode* vmInstrNode,
470 const TargetMachine& targetMachine,
471 bool canDiscardResult = false,
474 int resultPosition = 2);
476 MachineOperand::MachineOperandType
477 ChooseRegOrImmed(Value* val,
478 MachineOpCode opCode,
479 const TargetMachine& targetMachine,
481 unsigned int& getMachineRegNum,
482 int64_t& getImmedValue);
485 ostream& operator<<(ostream& os, const MachineInstr& minstr);
488 ostream& operator<<(ostream& os, const MachineOperand& mop);
491 void PrintMachineInstructions (const Method *method);
494 //**************************************************************************/