1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineOperand class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
15 #define LLVM_CODEGEN_MACHINEOPERAND_H
17 #include "llvm/Support/DataTypes.h"
26 class MachineBasicBlock;
28 class MachineRegisterInfo;
31 class TargetRegisterInfo;
36 /// MachineOperand class - Representation of each machine instruction operand.
38 class MachineOperand {
40 enum MachineOperandType {
41 MO_Register, ///< Register operand.
42 MO_Immediate, ///< Immediate operand
43 MO_CImmediate, ///< Immediate >64bit operand
44 MO_FPImmediate, ///< Floating-point immediate operand
45 MO_MachineBasicBlock, ///< MachineBasicBlock reference
46 MO_FrameIndex, ///< Abstract Stack Frame Index
47 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
48 MO_TargetIndex, ///< Target-dependent index+offset operand.
49 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
50 MO_ExternalSymbol, ///< Name of external global symbol
51 MO_GlobalAddress, ///< Address of a global value
52 MO_BlockAddress, ///< Address of a basic block
53 MO_RegisterMask, ///< Mask of preserved registers.
54 MO_Metadata, ///< Metadata reference (for debug info)
55 MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
59 /// OpKind - Specify what kind of operand this is. This discriminates the
61 unsigned char OpKind; // MachineOperandType
63 // This union is discriminated by OpKind.
65 /// SubReg - Subregister number, only valid for MO_Register. A value of 0
66 /// indicates the MO_Register has no subReg.
69 /// TargetFlags - This is a set of target-specific operand flags.
70 unsigned char TargetFlags;
73 /// TiedTo - Non-zero when this register operand is tied to another register
74 /// operand. The encoding of this field is described in the block comment
75 /// before MachineInstr::tieOperands().
76 unsigned char TiedTo : 4;
78 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
81 /// IsDef - True if this is a def, false if this is a use of the register.
85 /// IsImp - True if this is an implicit def or use, false if it is explicit.
89 /// IsKill - True if this instruction is the last use of the register on this
90 /// path through the function. This is only valid on uses of registers.
93 /// IsDead - True if this register is never used by a subsequent instruction.
94 /// This is only valid on definitions of registers.
97 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
98 /// read value doesn't matter. This flag can be set on both use and def
99 /// operands. On a sub-register def operand, it refers to the part of the
100 /// register that isn't written. On a full-register def operand, it is a
101 /// noop. See readsReg().
103 /// This is only valid on registers.
105 /// Note that an instruction may have multiple <undef> operands referring to
106 /// the same register. In that case, the instruction may depend on those
107 /// operands reading the same dont-care value. For example:
109 /// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
111 /// Any register can be used for %vreg2, and its value doesn't matter, but
112 /// the two operands must be the same register.
116 /// IsInternalRead - True if this operand reads a value that was defined
117 /// inside the same instruction or bundle. This flag can be set on both use
118 /// and def operands. On a sub-register def operand, it refers to the part
119 /// of the register that isn't written. On a full-register def operand, it
122 /// When this flag is set, the instruction bundle must contain at least one
123 /// other def of the register. If multiple instructions in the bundle define
124 /// the register, the meaning is target-defined.
125 bool IsInternalRead : 1;
127 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
128 /// by the MachineInstr before all input registers are read. This is used to
129 /// model the GCC inline asm '&' constraint modifier.
130 bool IsEarlyClobber : 1;
132 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
133 /// not a real instruction. Such uses should be ignored during codegen.
136 /// SmallContents - This really should be part of the Contents union, but
137 /// lives out here so we can get a better packed struct.
138 /// MO_Register: Register number.
139 /// OffsetedInfo: Low bits of offset.
141 unsigned RegNo; // For MO_Register.
142 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
145 /// ParentMI - This is the instruction that this operand is embedded into.
146 /// This is valid for all operand types, when the operand is in an instr.
147 MachineInstr *ParentMI;
149 /// Contents union - This contains the payload for the various operand types.
151 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
152 const ConstantFP *CFP; // For MO_FPImmediate.
153 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
154 int64_t ImmVal; // For MO_Immediate.
155 const uint32_t *RegMask; // For MO_RegisterMask.
156 const MDNode *MD; // For MO_Metadata.
157 MCSymbol *Sym; // For MO_MCSymbol
159 struct { // For MO_Register.
160 // Register number is in SmallContents.RegNo.
161 MachineOperand *Prev; // Access list for register. See MRI.
162 MachineOperand *Next;
165 /// OffsetedInfo - This struct contains the offset and an object identifier.
166 /// this represent the object as with an optional offset from it.
169 int Index; // For MO_*Index - The index itself.
170 const char *SymbolName; // For MO_ExternalSymbol.
171 const GlobalValue *GV; // For MO_GlobalAddress.
172 const BlockAddress *BA; // For MO_BlockAddress.
174 // Low bits of offset are in SmallContents.OffsetLo.
175 int OffsetHi; // An offset from the object, high 32 bits.
179 explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
183 /// getType - Returns the MachineOperandType for this operand.
185 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
187 unsigned char getTargetFlags() const {
188 return isReg() ? 0 : TargetFlags;
190 void setTargetFlags(unsigned char F) {
191 assert(!isReg() && "Register operands can't have target flags");
194 void addTargetFlag(unsigned char F) {
195 assert(!isReg() && "Register operands can't have target flags");
200 /// getParent - Return the instruction that this operand belongs to.
202 MachineInstr *getParent() { return ParentMI; }
203 const MachineInstr *getParent() const { return ParentMI; }
205 /// clearParent - Reset the parent pointer.
207 /// The MachineOperand copy constructor also copies ParentMI, expecting the
208 /// original to be deleted. If a MachineOperand is ever stored outside a
209 /// MachineInstr, the parent pointer must be cleared.
211 /// Never call clearParent() on an operand in a MachineInstr.
213 void clearParent() { ParentMI = 0; }
215 void print(raw_ostream &os, const TargetMachine *TM = 0) const;
217 //===--------------------------------------------------------------------===//
218 // Accessors that tell you what kind of MachineOperand you're looking at.
219 //===--------------------------------------------------------------------===//
221 /// isReg - Tests if this is a MO_Register operand.
222 bool isReg() const { return OpKind == MO_Register; }
223 /// isImm - Tests if this is a MO_Immediate operand.
224 bool isImm() const { return OpKind == MO_Immediate; }
225 /// isCImm - Test if t his is a MO_CImmediate operand.
226 bool isCImm() const { return OpKind == MO_CImmediate; }
227 /// isFPImm - Tests if this is a MO_FPImmediate operand.
228 bool isFPImm() const { return OpKind == MO_FPImmediate; }
229 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
230 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
231 /// isFI - Tests if this is a MO_FrameIndex operand.
232 bool isFI() const { return OpKind == MO_FrameIndex; }
233 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
234 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
235 /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
236 bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
237 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
238 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
239 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
240 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
241 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
242 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
243 /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
244 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
245 /// isRegMask - Tests if this is a MO_RegisterMask operand.
246 bool isRegMask() const { return OpKind == MO_RegisterMask; }
247 /// isMetadata - Tests if this is a MO_Metadata operand.
248 bool isMetadata() const { return OpKind == MO_Metadata; }
249 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
252 //===--------------------------------------------------------------------===//
253 // Accessors for Register Operands
254 //===--------------------------------------------------------------------===//
256 /// getReg - Returns the register number.
257 unsigned getReg() const {
258 assert(isReg() && "This is not a register operand!");
259 return SmallContents.RegNo;
262 unsigned getSubReg() const {
263 assert(isReg() && "Wrong MachineOperand accessor");
264 return (unsigned)SubReg;
268 assert(isReg() && "Wrong MachineOperand accessor");
273 assert(isReg() && "Wrong MachineOperand accessor");
277 bool isImplicit() const {
278 assert(isReg() && "Wrong MachineOperand accessor");
282 bool isDead() const {
283 assert(isReg() && "Wrong MachineOperand accessor");
287 bool isKill() const {
288 assert(isReg() && "Wrong MachineOperand accessor");
292 bool isUndef() const {
293 assert(isReg() && "Wrong MachineOperand accessor");
297 bool isInternalRead() const {
298 assert(isReg() && "Wrong MachineOperand accessor");
299 return IsInternalRead;
302 bool isEarlyClobber() const {
303 assert(isReg() && "Wrong MachineOperand accessor");
304 return IsEarlyClobber;
307 bool isTied() const {
308 assert(isReg() && "Wrong MachineOperand accessor");
312 bool isDebug() const {
313 assert(isReg() && "Wrong MachineOperand accessor");
317 /// readsReg - Returns true if this operand reads the previous value of its
318 /// register. A use operand with the <undef> flag set doesn't read its
319 /// register. A sub-register def implicitly reads the other parts of the
320 /// register being redefined unless the <undef> flag is set.
322 /// This refers to reading the register value from before the current
323 /// instruction or bundle. Internal bundle reads are not included.
324 bool readsReg() const {
325 assert(isReg() && "Wrong MachineOperand accessor");
326 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
329 //===--------------------------------------------------------------------===//
330 // Mutators for Register Operands
331 //===--------------------------------------------------------------------===//
333 /// Change the register this operand corresponds to.
335 void setReg(unsigned Reg);
337 void setSubReg(unsigned subReg) {
338 assert(isReg() && "Wrong MachineOperand accessor");
339 SubReg = (unsigned char)subReg;
342 /// substVirtReg - Substitute the current register with the virtual
343 /// subregister Reg:SubReg. Take any existing SubReg index into account,
344 /// using TargetRegisterInfo to compose the subreg indices if necessary.
345 /// Reg must be a virtual register, SubIdx can be 0.
347 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
349 /// substPhysReg - Substitute the current register with the physical register
350 /// Reg, taking any existing SubReg into account. For instance,
351 /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
353 void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
355 void setIsUse(bool Val = true) { setIsDef(!Val); }
357 void setIsDef(bool Val = true);
359 void setImplicit(bool Val = true) {
360 assert(isReg() && "Wrong MachineOperand accessor");
364 void setIsKill(bool Val = true) {
365 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
366 assert((!Val || !isDebug()) && "Marking a debug operation as kill");
370 void setIsDead(bool Val = true) {
371 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
375 void setIsUndef(bool Val = true) {
376 assert(isReg() && "Wrong MachineOperand accessor");
380 void setIsInternalRead(bool Val = true) {
381 assert(isReg() && "Wrong MachineOperand accessor");
382 IsInternalRead = Val;
385 void setIsEarlyClobber(bool Val = true) {
386 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
387 IsEarlyClobber = Val;
390 void setIsDebug(bool Val = true) {
391 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
395 //===--------------------------------------------------------------------===//
396 // Accessors for various operand types.
397 //===--------------------------------------------------------------------===//
399 int64_t getImm() const {
400 assert(isImm() && "Wrong MachineOperand accessor");
401 return Contents.ImmVal;
404 const ConstantInt *getCImm() const {
405 assert(isCImm() && "Wrong MachineOperand accessor");
409 const ConstantFP *getFPImm() const {
410 assert(isFPImm() && "Wrong MachineOperand accessor");
414 MachineBasicBlock *getMBB() const {
415 assert(isMBB() && "Wrong MachineOperand accessor");
419 int getIndex() const {
420 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
421 "Wrong MachineOperand accessor");
422 return Contents.OffsetedInfo.Val.Index;
425 const GlobalValue *getGlobal() const {
426 assert(isGlobal() && "Wrong MachineOperand accessor");
427 return Contents.OffsetedInfo.Val.GV;
430 const BlockAddress *getBlockAddress() const {
431 assert(isBlockAddress() && "Wrong MachineOperand accessor");
432 return Contents.OffsetedInfo.Val.BA;
435 MCSymbol *getMCSymbol() const {
436 assert(isMCSymbol() && "Wrong MachineOperand accessor");
440 /// getOffset - Return the offset from the symbol in this operand. This always
441 /// returns 0 for ExternalSymbol operands.
442 int64_t getOffset() const {
443 assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
444 isBlockAddress()) && "Wrong MachineOperand accessor");
445 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
446 SmallContents.OffsetLo;
449 const char *getSymbolName() const {
450 assert(isSymbol() && "Wrong MachineOperand accessor");
451 return Contents.OffsetedInfo.Val.SymbolName;
454 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
455 /// It is sometimes necessary to detach the register mask pointer from its
456 /// machine operand. This static method can be used for such detached bit
458 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
459 // See TargetRegisterInfo.h.
460 assert(PhysReg < (1u << 30) && "Not a physical register");
461 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
464 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
465 bool clobbersPhysReg(unsigned PhysReg) const {
466 return clobbersPhysReg(getRegMask(), PhysReg);
469 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
471 const uint32_t *getRegMask() const {
472 assert(isRegMask() && "Wrong MachineOperand accessor");
473 return Contents.RegMask;
476 const MDNode *getMetadata() const {
477 assert(isMetadata() && "Wrong MachineOperand accessor");
481 //===--------------------------------------------------------------------===//
482 // Mutators for various operand types.
483 //===--------------------------------------------------------------------===//
485 void setImm(int64_t immVal) {
486 assert(isImm() && "Wrong MachineOperand mutator");
487 Contents.ImmVal = immVal;
490 void setOffset(int64_t Offset) {
491 assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
492 isBlockAddress()) && "Wrong MachineOperand accessor");
493 SmallContents.OffsetLo = unsigned(Offset);
494 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
497 void setIndex(int Idx) {
498 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
499 "Wrong MachineOperand accessor");
500 Contents.OffsetedInfo.Val.Index = Idx;
503 void setMBB(MachineBasicBlock *MBB) {
504 assert(isMBB() && "Wrong MachineOperand accessor");
508 //===--------------------------------------------------------------------===//
510 //===--------------------------------------------------------------------===//
512 /// isIdenticalTo - Return true if this operand is identical to the specified
513 /// operand. Note: This method ignores isKill and isDead properties.
514 bool isIdenticalTo(const MachineOperand &Other) const;
516 /// \brief MachineOperand hash_value overload.
518 /// Note that this includes the same information in the hash that
519 /// isIdenticalTo uses for comparison. It is thus suited for use in hash
520 /// tables which use that function for equality comparisons only.
521 friend hash_code hash_value(const MachineOperand &MO);
523 /// ChangeToImmediate - Replace this operand with a new immediate operand of
524 /// the specified value. If an operand is known to be an immediate already,
525 /// the setImm method should be used.
526 void ChangeToImmediate(int64_t ImmVal);
528 /// ChangeToRegister - Replace this operand with a new register operand of
529 /// the specified value. If an operand is known to be an register already,
530 /// the setReg method should be used.
531 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
532 bool isKill = false, bool isDead = false,
533 bool isUndef = false, bool isDebug = false);
535 //===--------------------------------------------------------------------===//
536 // Construction methods.
537 //===--------------------------------------------------------------------===//
539 static MachineOperand CreateImm(int64_t Val) {
540 MachineOperand Op(MachineOperand::MO_Immediate);
545 static MachineOperand CreateCImm(const ConstantInt *CI) {
546 MachineOperand Op(MachineOperand::MO_CImmediate);
551 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
552 MachineOperand Op(MachineOperand::MO_FPImmediate);
553 Op.Contents.CFP = CFP;
557 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
558 bool isKill = false, bool isDead = false,
559 bool isUndef = false,
560 bool isEarlyClobber = false,
562 bool isDebug = false,
563 bool isInternalRead = false) {
564 MachineOperand Op(MachineOperand::MO_Register);
569 Op.IsUndef = isUndef;
570 Op.IsInternalRead = isInternalRead;
571 Op.IsEarlyClobber = isEarlyClobber;
573 Op.IsDebug = isDebug;
574 Op.SmallContents.RegNo = Reg;
575 Op.Contents.Reg.Prev = 0;
576 Op.Contents.Reg.Next = 0;
580 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
581 unsigned char TargetFlags = 0) {
582 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
584 Op.setTargetFlags(TargetFlags);
587 static MachineOperand CreateFI(int Idx) {
588 MachineOperand Op(MachineOperand::MO_FrameIndex);
592 static MachineOperand CreateCPI(unsigned Idx, int Offset,
593 unsigned char TargetFlags = 0) {
594 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
596 Op.setOffset(Offset);
597 Op.setTargetFlags(TargetFlags);
600 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
601 unsigned char TargetFlags = 0) {
602 MachineOperand Op(MachineOperand::MO_TargetIndex);
604 Op.setOffset(Offset);
605 Op.setTargetFlags(TargetFlags);
608 static MachineOperand CreateJTI(unsigned Idx,
609 unsigned char TargetFlags = 0) {
610 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
612 Op.setTargetFlags(TargetFlags);
615 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
616 unsigned char TargetFlags = 0) {
617 MachineOperand Op(MachineOperand::MO_GlobalAddress);
618 Op.Contents.OffsetedInfo.Val.GV = GV;
619 Op.setOffset(Offset);
620 Op.setTargetFlags(TargetFlags);
623 static MachineOperand CreateES(const char *SymName,
624 unsigned char TargetFlags = 0) {
625 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
626 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
627 Op.setOffset(0); // Offset is always 0.
628 Op.setTargetFlags(TargetFlags);
631 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
632 unsigned char TargetFlags = 0) {
633 MachineOperand Op(MachineOperand::MO_BlockAddress);
634 Op.Contents.OffsetedInfo.Val.BA = BA;
635 Op.setOffset(Offset);
636 Op.setTargetFlags(TargetFlags);
639 /// CreateRegMask - Creates a register mask operand referencing Mask. The
640 /// operand does not take ownership of the memory referenced by Mask, it must
641 /// remain valid for the lifetime of the operand.
643 /// A RegMask operand represents a set of non-clobbered physical registers on
644 /// an instruction that clobbers many registers, typically a call. The bit
645 /// mask has a bit set for each physreg that is preserved by this
646 /// instruction, as described in the documentation for
647 /// TargetRegisterInfo::getCallPreservedMask().
649 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
651 static MachineOperand CreateRegMask(const uint32_t *Mask) {
652 assert(Mask && "Missing register mask");
653 MachineOperand Op(MachineOperand::MO_RegisterMask);
654 Op.Contents.RegMask = Mask;
657 static MachineOperand CreateMetadata(const MDNode *Meta) {
658 MachineOperand Op(MachineOperand::MO_Metadata);
659 Op.Contents.MD = Meta;
663 static MachineOperand CreateMCSymbol(MCSymbol *Sym) {
664 MachineOperand Op(MachineOperand::MO_MCSymbol);
665 Op.Contents.Sym = Sym;
669 friend class MachineInstr;
670 friend class MachineRegisterInfo;
672 //===--------------------------------------------------------------------===//
673 // Methods for handling register use/def lists.
674 //===--------------------------------------------------------------------===//
676 /// isOnRegUseList - Return true if this operand is on a register use/def list
677 /// or false if not. This can only be called for register operands that are
678 /// part of a machine instruction.
679 bool isOnRegUseList() const {
680 assert(isReg() && "Can only add reg operand to use lists");
681 return Contents.Reg.Prev != 0;
685 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
690 } // End llvm namespace