1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator.h"
24 /// MachineRegisterInfo - Keep track of information for virtual and physical
25 /// registers, including vreg register classes, use/def chains for registers,
27 class MachineRegisterInfo {
28 /// VRegInfo - Information we keep for each virtual register. The entries in
29 /// this vector are actually converted to vreg numbers by adding the
30 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
32 /// Each element in this list contains the register class of the vreg and the
33 /// start of the use/def list for the register.
34 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
36 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
37 /// virtual registers. For each target register class, it keeps a list of
38 /// virtual registers belonging to the class.
39 std::vector<std::vector<unsigned> > RegClass2VRegMap;
41 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
42 /// physical registers.
43 MachineOperand **PhysRegUseDefLists;
45 /// UsedPhysRegs - This is a bit vector that is computed and set by the
46 /// register allocator, and must be kept up to date by passes that run after
47 /// register allocation (though most don't modify this). This is used
48 /// so that the code generator knows which callee save registers to save and
49 /// for other target specific uses.
50 BitVector UsedPhysRegs;
52 /// LiveIns/LiveOuts - Keep track of the physical registers that are
53 /// livein/liveout of the function. Live in values are typically arguments in
54 /// registers, live out values are typically return values in registers.
55 /// LiveIn values are allowed to have virtual registers associated with them,
56 /// stored in the second element.
57 std::vector<std::pair<unsigned, unsigned> > LiveIns;
58 std::vector<unsigned> LiveOuts;
60 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
61 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
63 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
64 ~MachineRegisterInfo();
66 //===--------------------------------------------------------------------===//
68 //===--------------------------------------------------------------------===//
70 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
71 /// and uses of a register within the MachineFunction that corresponds to this
72 /// MachineRegisterInfo object.
73 template<bool Uses, bool Defs>
74 class defusechain_iterator;
76 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
78 typedef defusechain_iterator<true,true> reg_iterator;
79 reg_iterator reg_begin(unsigned RegNo) const {
80 return reg_iterator(getRegUseDefListHead(RegNo));
82 static reg_iterator reg_end() { return reg_iterator(0); }
84 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
85 typedef defusechain_iterator<false,true> def_iterator;
86 def_iterator def_begin(unsigned RegNo) const {
87 return def_iterator(getRegUseDefListHead(RegNo));
89 static def_iterator def_end() { return def_iterator(0); }
91 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
92 typedef defusechain_iterator<true,false> use_iterator;
93 use_iterator use_begin(unsigned RegNo) const {
94 return use_iterator(getRegUseDefListHead(RegNo));
96 static use_iterator use_end() { return use_iterator(0); }
98 /// use_empty - Return true if there are no instructions using the specified
100 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
103 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
104 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
105 /// except that it also changes any definitions of the register as well.
106 void replaceRegWith(unsigned FromReg, unsigned ToReg);
108 /// getRegUseDefListHead - Return the head pointer for the register use/def
109 /// list for the specified virtual or physical register.
110 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
111 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
112 return PhysRegUseDefLists[RegNo];
113 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
114 return VRegInfo[RegNo].second;
117 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
118 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
119 return PhysRegUseDefLists[RegNo];
120 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
121 return VRegInfo[RegNo].second;
124 /// getVRegDef - Return the machine instr that defines the specified virtual
125 /// register or null if none is found. This assumes that the code is in SSA
126 /// form, so there should only be one definition.
127 MachineInstr *getVRegDef(unsigned Reg) const;
130 void dumpUses(unsigned RegNo) const;
133 //===--------------------------------------------------------------------===//
134 // Virtual Register Info
135 //===--------------------------------------------------------------------===//
137 /// getRegClass - Return the register class of the specified virtual register.
139 const TargetRegisterClass *getRegClass(unsigned Reg) const {
140 Reg -= TargetRegisterInfo::FirstVirtualRegister;
141 assert(Reg < VRegInfo.size() && "Invalid vreg!");
142 return VRegInfo[Reg].first;
145 /// setRegClass - Set the register class of the specified virtual register.
147 void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
149 Reg -= TargetRegisterInfo::FirstVirtualRegister;
150 assert(Reg < VRegInfo.size() && "Invalid vreg!");
151 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
152 VRegInfo[Reg].first = RC;
154 // Remove from old register class's vregs list. This may be slow but
155 // fortunately this operation is rarely needed.
156 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
157 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
160 // Add to new register class's vregs list.
161 RegClass2VRegMap[RC->getID()].push_back(VR);
164 /// createVirtualRegister - Create and return a new virtual register in the
165 /// function with the specified register class.
167 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
168 assert(RegClass && "Cannot create register without RegClass!");
169 // Add a reg, but keep track of whether the vector reallocated or not.
170 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
171 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
173 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
174 // The vector reallocated, handle this now.
175 HandleVRegListReallocation();
176 unsigned VR = getLastVirtReg();
177 RegClass2VRegMap[RegClass->getID()].push_back(VR);
181 /// getLastVirtReg - Return the highest currently assigned virtual register.
183 unsigned getLastVirtReg() const {
184 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
187 /// getRegClassVirtRegs - Return the list of virtual registers of the given
188 /// target register class.
189 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
190 return RegClass2VRegMap[RC->getID()];
193 //===--------------------------------------------------------------------===//
194 // Physical Register Use Info
195 //===--------------------------------------------------------------------===//
197 /// isPhysRegUsed - Return true if the specified register is used in this
198 /// function. This only works after register allocation.
199 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
201 /// setPhysRegUsed - Mark the specified register used in this function.
202 /// This should only be called during and after register allocation.
203 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
205 /// setPhysRegUnused - Mark the specified register unused in this function.
206 /// This should only be called during and after register allocation.
207 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
210 //===--------------------------------------------------------------------===//
211 // LiveIn/LiveOut Management
212 //===--------------------------------------------------------------------===//
214 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
215 /// is an error to add the same register to the same set more than once.
216 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
217 LiveIns.push_back(std::make_pair(Reg, vreg));
219 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
221 // Iteration support for live in/out sets. These sets are kept in sorted
222 // order by their register number.
223 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
225 typedef std::vector<unsigned>::const_iterator liveout_iterator;
226 livein_iterator livein_begin() const { return LiveIns.begin(); }
227 livein_iterator livein_end() const { return LiveIns.end(); }
228 bool livein_empty() const { return LiveIns.empty(); }
229 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
230 liveout_iterator liveout_end() const { return LiveOuts.end(); }
231 bool liveout_empty() const { return LiveOuts.empty(); }
233 bool isLiveIn(unsigned Reg) const {
234 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
235 if (I->first == Reg || I->second == Reg)
241 void HandleVRegListReallocation();
244 /// defusechain_iterator - This class provides iterator support for machine
245 /// operands in the function that use or define a specific register. If
246 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
247 /// returns defs. If neither are true then you are silly and it always
249 template<bool ReturnUses, bool ReturnDefs>
250 class defusechain_iterator
251 : public forward_iterator<MachineInstr, ptrdiff_t> {
253 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
254 // If the first node isn't one we're interested in, advance to one that
255 // we are interested in.
257 if ((!ReturnUses && op->isUse()) ||
258 (!ReturnDefs && op->isDef()))
262 friend class MachineRegisterInfo;
264 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
265 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
267 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
268 defusechain_iterator() : Op(0) {}
270 bool operator==(const defusechain_iterator &x) const {
273 bool operator!=(const defusechain_iterator &x) const {
274 return !operator==(x);
277 /// atEnd - return true if this iterator is equal to reg_end() on the value.
278 bool atEnd() const { return Op == 0; }
280 // Iterator traversal: forward iteration only
281 defusechain_iterator &operator++() { // Preincrement
282 assert(Op && "Cannot increment end iterator!");
283 Op = Op->getNextOperandForReg();
285 // If this is an operand we don't care about, skip it.
286 while (Op && ((!ReturnUses && Op->isUse()) ||
287 (!ReturnDefs && Op->isDef())))
288 Op = Op->getNextOperandForReg();
292 defusechain_iterator operator++(int) { // Postincrement
293 defusechain_iterator tmp = *this; ++*this; return tmp;
296 MachineOperand &getOperand() const {
297 assert(Op && "Cannot dereference end iterator!");
301 /// getOperandNo - Return the operand # of this MachineOperand in its
303 unsigned getOperandNo() const {
304 assert(Op && "Cannot dereference end iterator!");
305 return Op - &Op->getParent()->getOperand(0);
308 // Retrieve a reference to the current operand.
309 MachineInstr &operator*() const {
310 assert(Op && "Cannot dereference end iterator!");
311 return *Op->getParent();
314 MachineInstr *operator->() const {
315 assert(Op && "Cannot dereference end iterator!");
316 return Op->getParent();
322 } // End llvm namespace