1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBundle.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
29 /// MachineRegisterInfo - Keep track of information for virtual and physical
30 /// registers, including vreg register classes, use/def chains for registers,
32 class MachineRegisterInfo {
35 virtual void anchor();
37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
39 virtual ~Delegate() {}
43 const MachineFunction *MF;
44 Delegate *TheDelegate;
46 /// IsSSA - True when the machine function is in SSA form and virtual
47 /// registers have a single def.
50 /// TracksLiveness - True while register liveness is being tracked accurately.
51 /// Basic block live-in lists, kill flags, and implicit defs may not be
52 /// accurate when after this flag is cleared.
55 /// VRegInfo - Information we keep for each virtual register.
57 /// Each element in this list contains the register class of the vreg and the
58 /// start of the use/def list for the register.
59 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
60 VirtReg2IndexFunctor> VRegInfo;
62 /// RegAllocHints - This vector records register allocation hints for virtual
63 /// registers. For each virtual register, it keeps a register and hint type
64 /// pair making up the allocation hint. Hint type is target specific except
65 /// for the value 0 which means the second value of the pair is the preferred
66 /// register for allocation. For example, if the hint is <0, 1024>, it means
67 /// the allocator should prefer the physical register allocated to the virtual
68 /// register of the hint.
69 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
71 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
72 /// physical registers.
73 MachineOperand **PhysRegUseDefLists;
75 /// getRegUseDefListHead - Return the head pointer for the register use/def
76 /// list for the specified virtual or physical register.
77 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
78 if (TargetRegisterInfo::isVirtualRegister(RegNo))
79 return VRegInfo[RegNo].second;
80 return PhysRegUseDefLists[RegNo];
83 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
84 if (TargetRegisterInfo::isVirtualRegister(RegNo))
85 return VRegInfo[RegNo].second;
86 return PhysRegUseDefLists[RegNo];
89 /// Get the next element in the use-def chain.
90 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
91 assert(MO && MO->isReg() && "This is not a register operand!");
92 return MO->Contents.Reg.Next;
95 /// UsedRegUnits - This is a bit vector that is computed and set by the
96 /// register allocator, and must be kept up to date by passes that run after
97 /// register allocation (though most don't modify this). This is used
98 /// so that the code generator knows which callee save registers to save and
99 /// for other target specific uses.
100 /// This vector has bits set for register units that are modified in the
101 /// current function. It doesn't include registers clobbered by function
102 /// calls with register mask operands.
103 BitVector UsedRegUnits;
105 /// UsedPhysRegMask - Additional used physregs including aliases.
106 /// This bit vector represents all the registers clobbered by function calls.
107 /// It can model things that UsedRegUnits can't, such as function calls that
108 /// clobber ymm7 but preserve the low half in xmm7.
109 BitVector UsedPhysRegMask;
111 /// ReservedRegs - This is a bit vector of reserved registers. The target
112 /// may change its mind about which registers should be reserved. This
113 /// vector is the frozen set of reserved registers when register allocation
115 BitVector ReservedRegs;
117 /// Keep track of the physical registers that are live in to the function.
118 /// Live in values are typically arguments in registers. LiveIn values are
119 /// allowed to have virtual registers associated with them, stored in the
121 std::vector<std::pair<unsigned, unsigned> > LiveIns;
123 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
124 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
126 explicit MachineRegisterInfo(const MachineFunction *MF);
127 ~MachineRegisterInfo();
129 const TargetRegisterInfo *getTargetRegisterInfo() const {
130 return MF->getSubtarget().getRegisterInfo();
133 void resetDelegate(Delegate *delegate) {
134 // Ensure another delegate does not take over unless the current
135 // delegate first unattaches itself. If we ever need to multicast
136 // notifications, we will need to change to using a list.
137 assert(TheDelegate == delegate &&
138 "Only the current delegate can perform reset!");
139 TheDelegate = nullptr;
142 void setDelegate(Delegate *delegate) {
143 assert(delegate && !TheDelegate &&
144 "Attempted to set delegate to null, or to change it without "
145 "first resetting it!");
147 TheDelegate = delegate;
150 //===--------------------------------------------------------------------===//
152 //===--------------------------------------------------------------------===//
154 // isSSA - Returns true when the machine function is in SSA form. Early
155 // passes require the machine function to be in SSA form where every virtual
156 // register has a single defining instruction.
158 // The TwoAddressInstructionPass and PHIElimination passes take the machine
159 // function out of SSA form when they introduce multiple defs per virtual
161 bool isSSA() const { return IsSSA; }
163 // leaveSSA - Indicates that the machine function is no longer in SSA form.
164 void leaveSSA() { IsSSA = false; }
166 /// tracksLiveness - Returns true when tracking register liveness accurately.
168 /// While this flag is true, register liveness information in basic block
169 /// live-in lists and machine instruction operands is accurate. This means it
170 /// can be used to change the code in ways that affect the values in
171 /// registers, for example by the register scavenger.
173 /// When this flag is false, liveness is no longer reliable.
174 bool tracksLiveness() const { return TracksLiveness; }
176 /// invalidateLiveness - Indicates that register liveness is no longer being
177 /// tracked accurately.
179 /// This should be called by late passes that invalidate the liveness
181 void invalidateLiveness() { TracksLiveness = false; }
183 //===--------------------------------------------------------------------===//
185 //===--------------------------------------------------------------------===//
187 // Strictly for use by MachineInstr.cpp.
188 void addRegOperandToUseList(MachineOperand *MO);
190 // Strictly for use by MachineInstr.cpp.
191 void removeRegOperandFromUseList(MachineOperand *MO);
193 // Strictly for use by MachineInstr.cpp.
194 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
196 /// Verify the sanity of the use list for Reg.
197 void verifyUseList(unsigned Reg) const;
199 /// Verify the use list of all registers.
200 void verifyUseLists() const;
202 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
203 /// and uses of a register within the MachineFunction that corresponds to this
204 /// MachineRegisterInfo object.
205 template<bool Uses, bool Defs, bool SkipDebug,
206 bool ByOperand, bool ByInstr, bool ByBundle>
207 class defusechain_iterator;
208 template<bool Uses, bool Defs, bool SkipDebug,
209 bool ByOperand, bool ByInstr, bool ByBundle>
210 class defusechain_instr_iterator;
212 // Make it a friend so it can access getNextOperandForReg().
213 template<bool, bool, bool, bool, bool, bool>
214 friend class defusechain_iterator;
215 template<bool, bool, bool, bool, bool, bool>
216 friend class defusechain_instr_iterator;
220 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
222 typedef defusechain_iterator<true,true,false,true,false,false>
224 reg_iterator reg_begin(unsigned RegNo) const {
225 return reg_iterator(getRegUseDefListHead(RegNo));
227 static reg_iterator reg_end() { return reg_iterator(nullptr); }
229 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
230 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
233 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
234 /// of the specified register, stepping by MachineInstr.
235 typedef defusechain_instr_iterator<true,true,false,false,true,false>
237 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
238 return reg_instr_iterator(getRegUseDefListHead(RegNo));
240 static reg_instr_iterator reg_instr_end() {
241 return reg_instr_iterator(nullptr);
244 inline iterator_range<reg_instr_iterator>
245 reg_instructions(unsigned Reg) const {
246 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
250 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
251 /// of the specified register, stepping by bundle.
252 typedef defusechain_instr_iterator<true,true,false,false,false,true>
254 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
255 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
257 static reg_bundle_iterator reg_bundle_end() {
258 return reg_bundle_iterator(nullptr);
261 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
262 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
266 /// reg_empty - Return true if there are no instructions using or defining the
267 /// specified register (it may be live-in).
268 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
270 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
271 /// of the specified register, skipping those marked as Debug.
272 typedef defusechain_iterator<true,true,true,true,false,false>
274 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
275 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
277 static reg_nodbg_iterator reg_nodbg_end() {
278 return reg_nodbg_iterator(nullptr);
281 inline iterator_range<reg_nodbg_iterator>
282 reg_nodbg_operands(unsigned Reg) const {
283 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
287 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
288 /// all defs and uses of the specified register, stepping by MachineInstr,
289 /// skipping those marked as Debug.
290 typedef defusechain_instr_iterator<true,true,true,false,true,false>
291 reg_instr_nodbg_iterator;
292 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
293 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
295 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
296 return reg_instr_nodbg_iterator(nullptr);
299 inline iterator_range<reg_instr_nodbg_iterator>
300 reg_nodbg_instructions(unsigned Reg) const {
301 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
302 reg_instr_nodbg_end());
305 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
306 /// all defs and uses of the specified register, stepping by bundle,
307 /// skipping those marked as Debug.
308 typedef defusechain_instr_iterator<true,true,true,false,false,true>
309 reg_bundle_nodbg_iterator;
310 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
311 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
313 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
314 return reg_bundle_nodbg_iterator(nullptr);
317 inline iterator_range<reg_bundle_nodbg_iterator>
318 reg_nodbg_bundles(unsigned Reg) const {
319 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
320 reg_bundle_nodbg_end());
323 /// reg_nodbg_empty - Return true if the only instructions using or defining
324 /// Reg are Debug instructions.
325 bool reg_nodbg_empty(unsigned RegNo) const {
326 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
329 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
330 typedef defusechain_iterator<false,true,false,true,false,false>
332 def_iterator def_begin(unsigned RegNo) const {
333 return def_iterator(getRegUseDefListHead(RegNo));
335 static def_iterator def_end() { return def_iterator(nullptr); }
337 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
338 return iterator_range<def_iterator>(def_begin(Reg), def_end());
341 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
342 /// specified register, stepping by MachineInst.
343 typedef defusechain_instr_iterator<false,true,false,false,true,false>
345 def_instr_iterator def_instr_begin(unsigned RegNo) const {
346 return def_instr_iterator(getRegUseDefListHead(RegNo));
348 static def_instr_iterator def_instr_end() {
349 return def_instr_iterator(nullptr);
352 inline iterator_range<def_instr_iterator>
353 def_instructions(unsigned Reg) const {
354 return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
358 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
359 /// specified register, stepping by bundle.
360 typedef defusechain_instr_iterator<false,true,false,false,false,true>
362 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
363 return def_bundle_iterator(getRegUseDefListHead(RegNo));
365 static def_bundle_iterator def_bundle_end() {
366 return def_bundle_iterator(nullptr);
369 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
370 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
374 /// def_empty - Return true if there are no instructions defining the
375 /// specified register (it may be live-in).
376 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
378 /// hasOneDef - Return true if there is exactly one instruction defining the
379 /// specified register.
380 bool hasOneDef(unsigned RegNo) const {
381 def_iterator DI = def_begin(RegNo);
384 return ++DI == def_end();
387 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
388 typedef defusechain_iterator<true,false,false,true,false,false>
390 use_iterator use_begin(unsigned RegNo) const {
391 return use_iterator(getRegUseDefListHead(RegNo));
393 static use_iterator use_end() { return use_iterator(nullptr); }
395 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
396 return iterator_range<use_iterator>(use_begin(Reg), use_end());
399 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
400 /// specified register, stepping by MachineInstr.
401 typedef defusechain_instr_iterator<true,false,false,false,true,false>
403 use_instr_iterator use_instr_begin(unsigned RegNo) const {
404 return use_instr_iterator(getRegUseDefListHead(RegNo));
406 static use_instr_iterator use_instr_end() {
407 return use_instr_iterator(nullptr);
410 inline iterator_range<use_instr_iterator>
411 use_instructions(unsigned Reg) const {
412 return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
416 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
417 /// specified register, stepping by bundle.
418 typedef defusechain_instr_iterator<true,false,false,false,false,true>
420 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
421 return use_bundle_iterator(getRegUseDefListHead(RegNo));
423 static use_bundle_iterator use_bundle_end() {
424 return use_bundle_iterator(nullptr);
427 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
428 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
432 /// use_empty - Return true if there are no instructions using the specified
434 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
436 /// hasOneUse - Return true if there is exactly one instruction using the
437 /// specified register.
438 bool hasOneUse(unsigned RegNo) const {
439 use_iterator UI = use_begin(RegNo);
442 return ++UI == use_end();
445 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
446 /// specified register, skipping those marked as Debug.
447 typedef defusechain_iterator<true,false,true,true,false,false>
449 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
450 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
452 static use_nodbg_iterator use_nodbg_end() {
453 return use_nodbg_iterator(nullptr);
456 inline iterator_range<use_nodbg_iterator>
457 use_nodbg_operands(unsigned Reg) const {
458 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
462 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
463 /// all uses of the specified register, stepping by MachineInstr, skipping
464 /// those marked as Debug.
465 typedef defusechain_instr_iterator<true,false,true,false,true,false>
466 use_instr_nodbg_iterator;
467 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
468 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
470 static use_instr_nodbg_iterator use_instr_nodbg_end() {
471 return use_instr_nodbg_iterator(nullptr);
474 inline iterator_range<use_instr_nodbg_iterator>
475 use_nodbg_instructions(unsigned Reg) const {
476 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
477 use_instr_nodbg_end());
480 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
481 /// all uses of the specified register, stepping by bundle, skipping
482 /// those marked as Debug.
483 typedef defusechain_instr_iterator<true,false,true,false,false,true>
484 use_bundle_nodbg_iterator;
485 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
486 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
488 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
489 return use_bundle_nodbg_iterator(nullptr);
492 inline iterator_range<use_bundle_nodbg_iterator>
493 use_nodbg_bundles(unsigned Reg) const {
494 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
495 use_bundle_nodbg_end());
498 /// use_nodbg_empty - Return true if there are no non-Debug instructions
499 /// using the specified register.
500 bool use_nodbg_empty(unsigned RegNo) const {
501 return use_nodbg_begin(RegNo) == use_nodbg_end();
504 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
505 /// instruction using the specified register.
506 bool hasOneNonDBGUse(unsigned RegNo) const;
508 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
509 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
510 /// except that it also changes any definitions of the register as well.
512 /// Note that it is usually necessary to first constrain ToReg's register
513 /// class to match the FromReg constraints using:
515 /// constrainRegClass(ToReg, getRegClass(FromReg))
517 /// That function will return NULL if the virtual registers have incompatible
520 /// Note that if ToReg is a physical register the function will replace and
521 /// apply sub registers to ToReg in order to obtain a final/proper physical
523 void replaceRegWith(unsigned FromReg, unsigned ToReg);
525 /// getVRegDef - Return the machine instr that defines the specified virtual
526 /// register or null if none is found. This assumes that the code is in SSA
527 /// form, so there should only be one definition.
528 MachineInstr *getVRegDef(unsigned Reg) const;
530 /// getUniqueVRegDef - Return the unique machine instr that defines the
531 /// specified virtual register or null if none is found. If there are
532 /// multiple definitions or no definition, return null.
533 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
535 /// clearKillFlags - Iterate over all the uses of the given register and
536 /// clear the kill flag from the MachineOperand. This function is used by
537 /// optimization passes which extend register lifetimes and need only
538 /// preserve conservative kill flag information.
539 void clearKillFlags(unsigned Reg) const;
542 void dumpUses(unsigned RegNo) const;
545 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
546 /// throughout the function. It is safe to move instructions that read such
548 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
550 /// Get an iterator over the pressure sets affected by the given physical or
551 /// virtual register. If RegUnit is physical, it must be a register unit (from
552 /// MCRegUnitIterator).
553 PSetIterator getPressureSets(unsigned RegUnit) const;
555 //===--------------------------------------------------------------------===//
556 // Virtual Register Info
557 //===--------------------------------------------------------------------===//
559 /// getRegClass - Return the register class of the specified virtual register.
561 const TargetRegisterClass *getRegClass(unsigned Reg) const {
562 return VRegInfo[Reg].first;
565 /// setRegClass - Set the register class of the specified virtual register.
567 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
569 /// constrainRegClass - Constrain the register class of the specified virtual
570 /// register to be a common subclass of RC and the current register class,
571 /// but only if the new class has at least MinNumRegs registers. Return the
572 /// new register class, or NULL if no such class exists.
573 /// This should only be used when the constraint is known to be trivial, like
574 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
576 const TargetRegisterClass *constrainRegClass(unsigned Reg,
577 const TargetRegisterClass *RC,
578 unsigned MinNumRegs = 0);
580 /// recomputeRegClass - Try to find a legal super-class of Reg's register
581 /// class that still satisfies the constraints from the instructions using
582 /// Reg. Returns true if Reg was upgraded.
584 /// This method can be used after constraints have been removed from a
585 /// virtual register, for example after removing instructions or splitting
588 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
590 /// createVirtualRegister - Create and return a new virtual register in the
591 /// function with the specified register class.
593 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
595 /// getNumVirtRegs - Return the number of virtual registers created.
597 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
599 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
600 void clearVirtRegs();
602 /// setRegAllocationHint - Specify a register allocation hint for the
603 /// specified virtual register.
604 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
605 RegAllocHints[Reg].first = Type;
606 RegAllocHints[Reg].second = PrefReg;
609 /// getRegAllocationHint - Return the register allocation hint for the
610 /// specified virtual register.
611 std::pair<unsigned, unsigned>
612 getRegAllocationHint(unsigned Reg) const {
613 return RegAllocHints[Reg];
616 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
617 /// standard simple hint (Type == 0) is not set.
618 unsigned getSimpleHint(unsigned Reg) const {
619 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
620 return Hint.first ? 0 : Hint.second;
623 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
624 /// specified register as undefined which causes the DBG_VALUE to be
625 /// deleted during LiveDebugVariables analysis.
626 void markUsesInDebugValueAsUndef(unsigned Reg) const;
628 //===--------------------------------------------------------------------===//
629 // Physical Register Use Info
630 //===--------------------------------------------------------------------===//
632 /// isPhysRegUsed - Return true if the specified register is used in this
633 /// function. Also check for clobbered aliases and registers clobbered by
634 /// function calls with register mask operands.
636 /// This only works after register allocation. It is primarily used by
637 /// PrologEpilogInserter to determine which callee-saved registers need
639 bool isPhysRegUsed(unsigned Reg) const {
640 if (UsedPhysRegMask.test(Reg))
642 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
643 Units.isValid(); ++Units)
644 if (UsedRegUnits.test(*Units))
649 /// Mark the specified register unit as used in this function.
650 /// This should only be called during and after register allocation.
651 void setRegUnitUsed(unsigned RegUnit) {
652 UsedRegUnits.set(RegUnit);
655 /// setPhysRegUsed - Mark the specified register used in this function.
656 /// This should only be called during and after register allocation.
657 void setPhysRegUsed(unsigned Reg) {
658 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
659 Units.isValid(); ++Units)
660 UsedRegUnits.set(*Units);
663 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
664 /// This corresponds to the bit mask attached to register mask operands.
665 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
666 UsedPhysRegMask.setBitsNotInMask(RegMask);
669 /// setPhysRegUnused - Mark the specified register unused in this function.
670 /// This should only be called during and after register allocation.
671 void setPhysRegUnused(unsigned Reg) {
672 UsedPhysRegMask.reset(Reg);
673 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
674 Units.isValid(); ++Units)
675 UsedRegUnits.reset(*Units);
679 //===--------------------------------------------------------------------===//
680 // Reserved Register Info
681 //===--------------------------------------------------------------------===//
683 // The set of reserved registers must be invariant during register
684 // allocation. For example, the target cannot suddenly decide it needs a
685 // frame pointer when the register allocator has already used the frame
686 // pointer register for something else.
688 // These methods can be used by target hooks like hasFP() to avoid changing
689 // the reserved register set during register allocation.
691 /// freezeReservedRegs - Called by the register allocator to freeze the set
692 /// of reserved registers before allocation begins.
693 void freezeReservedRegs(const MachineFunction&);
695 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
696 /// to ensure the set of reserved registers stays constant.
697 bool reservedRegsFrozen() const {
698 return !ReservedRegs.empty();
701 /// canReserveReg - Returns true if PhysReg can be used as a reserved
702 /// register. Any register can be reserved before freezeReservedRegs() is
704 bool canReserveReg(unsigned PhysReg) const {
705 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
708 /// getReservedRegs - Returns a reference to the frozen set of reserved
709 /// registers. This method should always be preferred to calling
710 /// TRI::getReservedRegs() when possible.
711 const BitVector &getReservedRegs() const {
712 assert(reservedRegsFrozen() &&
713 "Reserved registers haven't been frozen yet. "
714 "Use TRI::getReservedRegs().");
718 /// isReserved - Returns true when PhysReg is a reserved register.
720 /// Reserved registers may belong to an allocatable register class, but the
721 /// target has explicitly requested that they are not used.
723 bool isReserved(unsigned PhysReg) const {
724 return getReservedRegs().test(PhysReg);
727 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
728 /// register class and it hasn't been reserved.
730 /// Allocatable registers may show up in the allocation order of some virtual
731 /// register, so a register allocator needs to track its liveness and
733 bool isAllocatable(unsigned PhysReg) const {
734 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
735 !isReserved(PhysReg);
738 //===--------------------------------------------------------------------===//
740 //===--------------------------------------------------------------------===//
742 /// addLiveIn - Add the specified register as a live-in. Note that it
743 /// is an error to add the same register to the same set more than once.
744 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
745 LiveIns.push_back(std::make_pair(Reg, vreg));
748 // Iteration support for the live-ins set. It's kept in sorted order
749 // by register number.
750 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
752 livein_iterator livein_begin() const { return LiveIns.begin(); }
753 livein_iterator livein_end() const { return LiveIns.end(); }
754 bool livein_empty() const { return LiveIns.empty(); }
756 bool isLiveIn(unsigned Reg) const;
758 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
759 /// corresponding live-in physical register.
760 unsigned getLiveInPhysReg(unsigned VReg) const;
762 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
763 /// corresponding live-in physical register.
764 unsigned getLiveInVirtReg(unsigned PReg) const;
766 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
767 /// into the given entry block.
768 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
769 const TargetRegisterInfo &TRI,
770 const TargetInstrInfo &TII);
772 /// defusechain_iterator - This class provides iterator support for machine
773 /// operands in the function that use or define a specific register. If
774 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
775 /// returns defs. If neither are true then you are silly and it always
776 /// returns end(). If SkipDebug is true it skips uses marked Debug
777 /// when incrementing.
778 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
779 bool ByOperand, bool ByInstr, bool ByBundle>
780 class defusechain_iterator
781 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
783 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
784 // If the first node isn't one we're interested in, advance to one that
785 // we are interested in.
787 if ((!ReturnUses && op->isUse()) ||
788 (!ReturnDefs && op->isDef()) ||
789 (SkipDebug && op->isDebug()))
793 friend class MachineRegisterInfo;
796 assert(Op && "Cannot increment end iterator!");
797 Op = getNextOperandForReg(Op);
799 // All defs come before the uses, so stop def_iterator early.
805 assert(!Op->isDebug() && "Can't have debug defs");
808 // If this is an operand we don't care about, skip it.
809 while (Op && ((!ReturnDefs && Op->isDef()) ||
810 (SkipDebug && Op->isDebug())))
811 Op = getNextOperandForReg(Op);
815 typedef std::iterator<std::forward_iterator_tag,
816 MachineInstr, ptrdiff_t>::reference reference;
817 typedef std::iterator<std::forward_iterator_tag,
818 MachineInstr, ptrdiff_t>::pointer pointer;
820 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
821 defusechain_iterator() : Op(nullptr) {}
823 bool operator==(const defusechain_iterator &x) const {
826 bool operator!=(const defusechain_iterator &x) const {
827 return !operator==(x);
830 /// atEnd - return true if this iterator is equal to reg_end() on the value.
831 bool atEnd() const { return Op == nullptr; }
833 // Iterator traversal: forward iteration only
834 defusechain_iterator &operator++() { // Preincrement
835 assert(Op && "Cannot increment end iterator!");
839 MachineInstr *P = Op->getParent();
842 } while (Op && Op->getParent() == P);
843 } else if (ByBundle) {
844 MachineInstr *P = getBundleStart(Op->getParent());
847 } while (Op && getBundleStart(Op->getParent()) == P);
852 defusechain_iterator operator++(int) { // Postincrement
853 defusechain_iterator tmp = *this; ++*this; return tmp;
856 /// getOperandNo - Return the operand # of this MachineOperand in its
858 unsigned getOperandNo() const {
859 assert(Op && "Cannot dereference end iterator!");
860 return Op - &Op->getParent()->getOperand(0);
863 // Retrieve a reference to the current operand.
864 MachineOperand &operator*() const {
865 assert(Op && "Cannot dereference end iterator!");
869 MachineOperand *operator->() const {
870 assert(Op && "Cannot dereference end iterator!");
875 /// defusechain_iterator - This class provides iterator support for machine
876 /// operands in the function that use or define a specific register. If
877 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
878 /// returns defs. If neither are true then you are silly and it always
879 /// returns end(). If SkipDebug is true it skips uses marked Debug
880 /// when incrementing.
881 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
882 bool ByOperand, bool ByInstr, bool ByBundle>
883 class defusechain_instr_iterator
884 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
886 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
887 // If the first node isn't one we're interested in, advance to one that
888 // we are interested in.
890 if ((!ReturnUses && op->isUse()) ||
891 (!ReturnDefs && op->isDef()) ||
892 (SkipDebug && op->isDebug()))
896 friend class MachineRegisterInfo;
899 assert(Op && "Cannot increment end iterator!");
900 Op = getNextOperandForReg(Op);
902 // All defs come before the uses, so stop def_iterator early.
908 assert(!Op->isDebug() && "Can't have debug defs");
911 // If this is an operand we don't care about, skip it.
912 while (Op && ((!ReturnDefs && Op->isDef()) ||
913 (SkipDebug && Op->isDebug())))
914 Op = getNextOperandForReg(Op);
918 typedef std::iterator<std::forward_iterator_tag,
919 MachineInstr, ptrdiff_t>::reference reference;
920 typedef std::iterator<std::forward_iterator_tag,
921 MachineInstr, ptrdiff_t>::pointer pointer;
923 defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
924 defusechain_instr_iterator() : Op(nullptr) {}
926 bool operator==(const defusechain_instr_iterator &x) const {
929 bool operator!=(const defusechain_instr_iterator &x) const {
930 return !operator==(x);
933 /// atEnd - return true if this iterator is equal to reg_end() on the value.
934 bool atEnd() const { return Op == nullptr; }
936 // Iterator traversal: forward iteration only
937 defusechain_instr_iterator &operator++() { // Preincrement
938 assert(Op && "Cannot increment end iterator!");
942 MachineInstr *P = Op->getParent();
945 } while (Op && Op->getParent() == P);
946 } else if (ByBundle) {
947 MachineInstr *P = getBundleStart(Op->getParent());
950 } while (Op && getBundleStart(Op->getParent()) == P);
955 defusechain_instr_iterator operator++(int) { // Postincrement
956 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
959 // Retrieve a reference to the current operand.
960 MachineInstr &operator*() const {
961 assert(Op && "Cannot dereference end iterator!");
962 if (ByBundle) return *(getBundleStart(Op->getParent()));
963 return *Op->getParent();
966 MachineInstr *operator->() const {
967 assert(Op && "Cannot dereference end iterator!");
968 if (ByBundle) return getBundleStart(Op->getParent());
969 return Op->getParent();
974 /// Iterate over the pressure sets affected by the given physical or virtual
975 /// register. If Reg is physical, it must be a register unit (from
976 /// MCRegUnitIterator).
981 PSetIterator(): PSet(nullptr), Weight(0) {}
982 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
983 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
984 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
985 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
986 PSet = TRI->getRegClassPressureSets(RC);
987 Weight = TRI->getRegClassWeight(RC).RegWeight;
990 PSet = TRI->getRegUnitPressureSets(RegUnit);
991 Weight = TRI->getRegUnitWeight(RegUnit);
996 bool isValid() const { return PSet; }
998 unsigned getWeight() const { return Weight; }
1000 unsigned operator*() const { return *PSet; }
1003 assert(isValid() && "Invalid PSetIterator.");
1010 inline PSetIterator MachineRegisterInfo::
1011 getPressureSets(unsigned RegUnit) const {
1012 return PSetIterator(RegUnit, this);
1015 } // End llvm namespace