1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator"
24 /// MachineRegisterInfo - Keep track of information for each virtual register,
25 /// including its register class.
26 class MachineRegisterInfo {
27 /// VRegInfo - Information we keep for each virtual register. The entries in
28 /// this vector are actually converted to vreg numbers by adding the
29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
31 /// Each element in this list contains the register class of the vreg and the
32 /// start of the use/def list for the register.
33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
35 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
36 /// physical registers.
37 MachineOperand **PhysRegUseDefLists;
39 /// UsedPhysRegs - This is a bit vector that is computed and set by the
40 /// register allocator, and must be kept up to date by passes that run after
41 /// register allocation (though most don't modify this). This is used
42 /// so that the code generator knows which callee save registers to save and
43 /// for other target specific uses.
44 BitVector UsedPhysRegs;
46 /// LiveIns/LiveOuts - Keep track of the physical registers that are
47 /// livein/liveout of the function. Live in values are typically arguments in
48 /// registers, live out values are typically return values in registers.
49 /// LiveIn values are allowed to have virtual registers associated with them,
50 /// stored in the second element.
51 std::vector<std::pair<unsigned, unsigned> > LiveIns;
52 std::vector<unsigned> LiveOuts;
54 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
55 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
57 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
58 ~MachineRegisterInfo();
60 //===--------------------------------------------------------------------===//
62 //===--------------------------------------------------------------------===//
64 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
65 /// and uses of a register within the MachineFunction that corresponds to this
66 /// MachineRegisterInfo object.
67 template<bool Uses, bool Defs>
68 class defusechain_iterator;
70 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
72 typedef defusechain_iterator<true,true> reg_iterator;
73 reg_iterator reg_begin(unsigned RegNo) const {
74 return reg_iterator(getRegUseDefListHead(RegNo));
76 static reg_iterator reg_end() { return reg_iterator(0); }
78 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
79 typedef defusechain_iterator<false,true> def_iterator;
80 def_iterator def_begin(unsigned RegNo) const {
81 return def_iterator(getRegUseDefListHead(RegNo));
83 static def_iterator def_end() { return def_iterator(0); }
85 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
86 typedef defusechain_iterator<true,false> use_iterator;
87 use_iterator use_begin(unsigned RegNo) const {
88 return use_iterator(getRegUseDefListHead(RegNo));
90 static use_iterator use_end() { return use_iterator(0); }
93 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
94 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
95 /// except that it also changes any definitions of the register as well.
96 void replaceRegWith(unsigned FromReg, unsigned ToReg);
98 /// getRegUseDefListHead - Return the head pointer for the register use/def
99 /// list for the specified virtual or physical register.
100 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
101 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
102 return PhysRegUseDefLists[RegNo];
103 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
104 return VRegInfo[RegNo].second;
107 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
108 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
109 return PhysRegUseDefLists[RegNo];
110 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
111 return VRegInfo[RegNo].second;
114 /// getVRegDef - Return the machine instr that defines the specified virtual
115 /// register or null if none is found. This assumes that the code is in SSA
116 /// form, so there should only be one definition.
117 MachineInstr *getVRegDef(unsigned Reg) const;
120 void dumpUses(unsigned RegNo) const;
123 //===--------------------------------------------------------------------===//
124 // Virtual Register Info
125 //===--------------------------------------------------------------------===//
127 /// getRegClass - Return the register class of the specified virtual register.
128 const TargetRegisterClass *getRegClass(unsigned Reg) const {
129 Reg -= TargetRegisterInfo::FirstVirtualRegister;
130 assert(Reg < VRegInfo.size() && "Invalid vreg!");
131 return VRegInfo[Reg].first;
134 /// createVirtualRegister - Create and return a new virtual register in the
135 /// function with the specified register class.
137 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
138 assert(RegClass && "Cannot create register without RegClass!");
139 // Add a reg, but keep track of whether the vector reallocated or not.
140 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
141 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
143 if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
144 return getLastVirtReg();
146 // Otherwise, the vector reallocated, handle this now.
147 HandleVRegListReallocation();
148 return getLastVirtReg();
151 /// getLastVirtReg - Return the highest currently assigned virtual register.
153 unsigned getLastVirtReg() const {
154 return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
158 //===--------------------------------------------------------------------===//
159 // Physical Register Use Info
160 //===--------------------------------------------------------------------===//
162 /// isPhysRegUsed - Return true if the specified register is used in this
163 /// function. This only works after register allocation.
164 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
166 /// setPhysRegUsed - Mark the specified register used in this function.
167 /// This should only be called during and after register allocation.
168 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
170 /// setPhysRegUnused - Mark the specified register unused in this function.
171 /// This should only be called during and after register allocation.
172 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
175 //===--------------------------------------------------------------------===//
176 // LiveIn/LiveOut Management
177 //===--------------------------------------------------------------------===//
179 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
180 /// is an error to add the same register to the same set more than once.
181 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
182 LiveIns.push_back(std::make_pair(Reg, vreg));
184 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
186 // Iteration support for live in/out sets. These sets are kept in sorted
187 // order by their register number.
188 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
190 typedef std::vector<unsigned>::const_iterator liveout_iterator;
191 livein_iterator livein_begin() const { return LiveIns.begin(); }
192 livein_iterator livein_end() const { return LiveIns.end(); }
193 bool livein_empty() const { return LiveIns.empty(); }
194 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
195 liveout_iterator liveout_end() const { return LiveOuts.end(); }
196 bool liveout_empty() const { return LiveOuts.empty(); }
198 void HandleVRegListReallocation();
201 /// defusechain_iterator - This class provides iterator support for machine
202 /// operands in the function that use or define a specific register. If
203 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
204 /// returns defs. If neither are true then you are silly and it always
206 template<bool ReturnUses, bool ReturnDefs>
207 class defusechain_iterator
208 : public forward_iterator<MachineInstr, ptrdiff_t> {
210 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
211 // If the first node isn't one we're interested in, advance to one that
212 // we are interested in.
214 if ((!ReturnUses && op->isUse()) ||
215 (!ReturnDefs && op->isDef()))
219 friend class MachineRegisterInfo;
221 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
222 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
224 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
225 defusechain_iterator() : Op(0) {}
227 bool operator==(const defusechain_iterator &x) const {
230 bool operator!=(const defusechain_iterator &x) const {
231 return !operator==(x);
234 /// atEnd - return true if this iterator is equal to reg_end() on the value.
235 bool atEnd() const { return Op == 0; }
237 // Iterator traversal: forward iteration only
238 defusechain_iterator &operator++() { // Preincrement
239 assert(Op && "Cannot increment end iterator!");
240 Op = Op->getNextOperandForReg();
242 // If this is an operand we don't care about, skip it.
243 while (Op && ((!ReturnUses && Op->isUse()) ||
244 (!ReturnDefs && Op->isDef())))
245 Op = Op->getNextOperandForReg();
249 defusechain_iterator operator++(int) { // Postincrement
250 defusechain_iterator tmp = *this; ++*this; return tmp;
253 MachineOperand &getOperand() const {
254 assert(Op && "Cannot dereference end iterator!");
258 /// getOperandNo - Return the operand # of this MachineOperand in its
260 unsigned getOperandNo() const {
261 assert(Op && "Cannot dereference end iterator!");
262 return Op - &Op->getParent()->getOperand(0);
265 // Retrieve a reference to the current operand.
266 MachineInstr &operator*() const {
267 assert(Op && "Cannot dereference end iterator!");
268 return *Op->getParent();
271 MachineInstr *operator->() const {
272 assert(Op && "Cannot dereference end iterator!");
273 return Op->getParent();
279 } // End llvm namespace