1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
27 /// MachineRegisterInfo - Keep track of information for virtual and physical
28 /// registers, including vreg register classes, use/def chains for registers,
30 class MachineRegisterInfo {
33 virtual void anchor();
35 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
37 virtual ~Delegate() {}
41 const TargetMachine &TM;
42 Delegate *TheDelegate;
44 /// IsSSA - True when the machine function is in SSA form and virtual
45 /// registers have a single def.
48 /// TracksLiveness - True while register liveness is being tracked accurately.
49 /// Basic block live-in lists, kill flags, and implicit defs may not be
50 /// accurate when after this flag is cleared.
53 /// VRegInfo - Information we keep for each virtual register.
55 /// Each element in this list contains the register class of the vreg and the
56 /// start of the use/def list for the register.
57 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
58 VirtReg2IndexFunctor> VRegInfo;
60 /// RegAllocHints - This vector records register allocation hints for virtual
61 /// registers. For each virtual register, it keeps a register and hint type
62 /// pair making up the allocation hint. Hint type is target specific except
63 /// for the value 0 which means the second value of the pair is the preferred
64 /// register for allocation. For example, if the hint is <0, 1024>, it means
65 /// the allocator should prefer the physical register allocated to the virtual
66 /// register of the hint.
67 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
69 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
70 /// physical registers.
71 MachineOperand **PhysRegUseDefLists;
73 /// getRegUseDefListHead - Return the head pointer for the register use/def
74 /// list for the specified virtual or physical register.
75 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
76 if (TargetRegisterInfo::isVirtualRegister(RegNo))
77 return VRegInfo[RegNo].second;
78 return PhysRegUseDefLists[RegNo];
81 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
82 if (TargetRegisterInfo::isVirtualRegister(RegNo))
83 return VRegInfo[RegNo].second;
84 return PhysRegUseDefLists[RegNo];
87 /// Get the next element in the use-def chain.
88 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
89 assert(MO && MO->isReg() && "This is not a register operand!");
90 return MO->Contents.Reg.Next;
93 /// UsedRegUnits - This is a bit vector that is computed and set by the
94 /// register allocator, and must be kept up to date by passes that run after
95 /// register allocation (though most don't modify this). This is used
96 /// so that the code generator knows which callee save registers to save and
97 /// for other target specific uses.
98 /// This vector has bits set for register units that are modified in the
99 /// current function. It doesn't include registers clobbered by function
100 /// calls with register mask operands.
101 BitVector UsedRegUnits;
103 /// UsedPhysRegMask - Additional used physregs including aliases.
104 /// This bit vector represents all the registers clobbered by function calls.
105 /// It can model things that UsedRegUnits can't, such as function calls that
106 /// clobber ymm7 but preserve the low half in xmm7.
107 BitVector UsedPhysRegMask;
109 /// ReservedRegs - This is a bit vector of reserved registers. The target
110 /// may change its mind about which registers should be reserved. This
111 /// vector is the frozen set of reserved registers when register allocation
113 BitVector ReservedRegs;
115 /// Keep track of the physical registers that are live in to the function.
116 /// Live in values are typically arguments in registers. LiveIn values are
117 /// allowed to have virtual registers associated with them, stored in the
119 std::vector<std::pair<unsigned, unsigned> > LiveIns;
121 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
122 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
124 explicit MachineRegisterInfo(const TargetMachine &TM);
125 ~MachineRegisterInfo();
127 const TargetRegisterInfo *getTargetRegisterInfo() const {
128 return TM.getRegisterInfo();
131 void resetDelegate(Delegate *delegate) {
132 // Ensure another delegate does not take over unless the current
133 // delegate first unattaches itself. If we ever need to multicast
134 // notifications, we will need to change to using a list.
135 assert(TheDelegate == delegate &&
136 "Only the current delegate can perform reset!");
140 void setDelegate(Delegate *delegate) {
141 assert(delegate && !TheDelegate &&
142 "Attempted to set delegate to null, or to change it without "
143 "first resetting it!");
145 TheDelegate = delegate;
148 //===--------------------------------------------------------------------===//
150 //===--------------------------------------------------------------------===//
152 // isSSA - Returns true when the machine function is in SSA form. Early
153 // passes require the machine function to be in SSA form where every virtual
154 // register has a single defining instruction.
156 // The TwoAddressInstructionPass and PHIElimination passes take the machine
157 // function out of SSA form when they introduce multiple defs per virtual
159 bool isSSA() const { return IsSSA; }
161 // leaveSSA - Indicates that the machine function is no longer in SSA form.
162 void leaveSSA() { IsSSA = false; }
164 /// tracksLiveness - Returns true when tracking register liveness accurately.
166 /// While this flag is true, register liveness information in basic block
167 /// live-in lists and machine instruction operands is accurate. This means it
168 /// can be used to change the code in ways that affect the values in
169 /// registers, for example by the register scavenger.
171 /// When this flag is false, liveness is no longer reliable.
172 bool tracksLiveness() const { return TracksLiveness; }
174 /// invalidateLiveness - Indicates that register liveness is no longer being
175 /// tracked accurately.
177 /// This should be called by late passes that invalidate the liveness
179 void invalidateLiveness() { TracksLiveness = false; }
181 //===--------------------------------------------------------------------===//
183 //===--------------------------------------------------------------------===//
185 // Strictly for use by MachineInstr.cpp.
186 void addRegOperandToUseList(MachineOperand *MO);
188 // Strictly for use by MachineInstr.cpp.
189 void removeRegOperandFromUseList(MachineOperand *MO);
191 // Strictly for use by MachineInstr.cpp.
192 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
194 /// Verify the sanity of the use list for Reg.
195 void verifyUseList(unsigned Reg) const;
197 /// Verify the use list of all registers.
198 void verifyUseLists() const;
200 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
201 /// and uses of a register within the MachineFunction that corresponds to this
202 /// MachineRegisterInfo object.
203 template<bool Uses, bool Defs, bool SkipDebug>
204 class defusechain_iterator;
206 // Make it a friend so it can access getNextOperandForReg().
207 template<bool, bool, bool> friend class defusechain_iterator;
209 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
211 typedef defusechain_iterator<true,true,false> reg_iterator;
212 reg_iterator reg_begin(unsigned RegNo) const {
213 return reg_iterator(getRegUseDefListHead(RegNo));
215 static reg_iterator reg_end() { return reg_iterator(0); }
217 /// reg_empty - Return true if there are no instructions using or defining the
218 /// specified register (it may be live-in).
219 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
221 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
222 /// of the specified register, skipping those marked as Debug.
223 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
224 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
225 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
227 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
229 /// reg_nodbg_empty - Return true if the only instructions using or defining
230 /// Reg are Debug instructions.
231 bool reg_nodbg_empty(unsigned RegNo) const {
232 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
235 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
236 typedef defusechain_iterator<false,true,false> def_iterator;
237 def_iterator def_begin(unsigned RegNo) const {
238 return def_iterator(getRegUseDefListHead(RegNo));
240 static def_iterator def_end() { return def_iterator(0); }
242 /// def_empty - Return true if there are no instructions defining the
243 /// specified register (it may be live-in).
244 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
246 /// hasOneDef - Return true if there is exactly one instruction defining the
247 /// specified register.
248 bool hasOneDef(unsigned RegNo) const {
249 def_iterator DI = def_begin(RegNo);
252 return ++DI == def_end();
255 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
256 typedef defusechain_iterator<true,false,false> use_iterator;
257 use_iterator use_begin(unsigned RegNo) const {
258 return use_iterator(getRegUseDefListHead(RegNo));
260 static use_iterator use_end() { return use_iterator(0); }
262 /// use_empty - Return true if there are no instructions using the specified
264 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
266 /// hasOneUse - Return true if there is exactly one instruction using the
267 /// specified register.
268 bool hasOneUse(unsigned RegNo) const {
269 use_iterator UI = use_begin(RegNo);
272 return ++UI == use_end();
275 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
276 /// specified register, skipping those marked as Debug.
277 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
278 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
279 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
281 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
283 /// use_nodbg_empty - Return true if there are no non-Debug instructions
284 /// using the specified register.
285 bool use_nodbg_empty(unsigned RegNo) const {
286 return use_nodbg_begin(RegNo) == use_nodbg_end();
289 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
290 /// instruction using the specified register.
291 bool hasOneNonDBGUse(unsigned RegNo) const;
293 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
294 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
295 /// except that it also changes any definitions of the register as well.
297 /// Note that it is usually necessary to first constrain ToReg's register
298 /// class to match the FromReg constraints using:
300 /// constrainRegClass(ToReg, getRegClass(FromReg))
302 /// That function will return NULL if the virtual registers have incompatible
304 void replaceRegWith(unsigned FromReg, unsigned ToReg);
306 /// getVRegDef - Return the machine instr that defines the specified virtual
307 /// register or null if none is found. This assumes that the code is in SSA
308 /// form, so there should only be one definition.
309 MachineInstr *getVRegDef(unsigned Reg) const;
311 /// getUniqueVRegDef - Return the unique machine instr that defines the
312 /// specified virtual register or null if none is found. If there are
313 /// multiple definitions or no definition, return null.
314 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
316 /// clearKillFlags - Iterate over all the uses of the given register and
317 /// clear the kill flag from the MachineOperand. This function is used by
318 /// optimization passes which extend register lifetimes and need only
319 /// preserve conservative kill flag information.
320 void clearKillFlags(unsigned Reg) const;
323 void dumpUses(unsigned RegNo) const;
326 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
327 /// throughout the function. It is safe to move instructions that read such
329 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
331 /// Get an iterator over the pressure sets affected by the given physical or
332 /// virtual register. If RegUnit is physical, it must be a register unit (from
333 /// MCRegUnitIterator).
334 PSetIterator getPressureSets(unsigned RegUnit) const;
336 //===--------------------------------------------------------------------===//
337 // Virtual Register Info
338 //===--------------------------------------------------------------------===//
340 /// getRegClass - Return the register class of the specified virtual register.
342 const TargetRegisterClass *getRegClass(unsigned Reg) const {
343 return VRegInfo[Reg].first;
346 /// setRegClass - Set the register class of the specified virtual register.
348 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
350 /// constrainRegClass - Constrain the register class of the specified virtual
351 /// register to be a common subclass of RC and the current register class,
352 /// but only if the new class has at least MinNumRegs registers. Return the
353 /// new register class, or NULL if no such class exists.
354 /// This should only be used when the constraint is known to be trivial, like
355 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
357 const TargetRegisterClass *constrainRegClass(unsigned Reg,
358 const TargetRegisterClass *RC,
359 unsigned MinNumRegs = 0);
361 /// recomputeRegClass - Try to find a legal super-class of Reg's register
362 /// class that still satisfies the constraints from the instructions using
363 /// Reg. Returns true if Reg was upgraded.
365 /// This method can be used after constraints have been removed from a
366 /// virtual register, for example after removing instructions or splitting
369 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
371 /// createVirtualRegister - Create and return a new virtual register in the
372 /// function with the specified register class.
374 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
376 /// getNumVirtRegs - Return the number of virtual registers created.
378 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
380 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
381 void clearVirtRegs();
383 /// setRegAllocationHint - Specify a register allocation hint for the
384 /// specified virtual register.
385 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
386 RegAllocHints[Reg].first = Type;
387 RegAllocHints[Reg].second = PrefReg;
390 /// getRegAllocationHint - Return the register allocation hint for the
391 /// specified virtual register.
392 std::pair<unsigned, unsigned>
393 getRegAllocationHint(unsigned Reg) const {
394 return RegAllocHints[Reg];
397 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
398 /// standard simple hint (Type == 0) is not set.
399 unsigned getSimpleHint(unsigned Reg) const {
400 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
401 return Hint.first ? 0 : Hint.second;
405 //===--------------------------------------------------------------------===//
406 // Physical Register Use Info
407 //===--------------------------------------------------------------------===//
409 /// isPhysRegUsed - Return true if the specified register is used in this
410 /// function. Also check for clobbered aliases and registers clobbered by
411 /// function calls with register mask operands.
413 /// This only works after register allocation. It is primarily used by
414 /// PrologEpilogInserter to determine which callee-saved registers need
416 bool isPhysRegUsed(unsigned Reg) const {
417 if (UsedPhysRegMask.test(Reg))
419 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
420 Units.isValid(); ++Units)
421 if (UsedRegUnits.test(*Units))
426 /// Mark the specified register unit as used in this function.
427 /// This should only be called during and after register allocation.
428 void setRegUnitUsed(unsigned RegUnit) {
429 UsedRegUnits.set(RegUnit);
432 /// setPhysRegUsed - Mark the specified register used in this function.
433 /// This should only be called during and after register allocation.
434 void setPhysRegUsed(unsigned Reg) {
435 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
436 Units.isValid(); ++Units)
437 UsedRegUnits.set(*Units);
440 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
441 /// This corresponds to the bit mask attached to register mask operands.
442 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
443 UsedPhysRegMask.setBitsNotInMask(RegMask);
446 /// setPhysRegUnused - Mark the specified register unused in this function.
447 /// This should only be called during and after register allocation.
448 void setPhysRegUnused(unsigned Reg) {
449 UsedPhysRegMask.reset(Reg);
450 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
451 Units.isValid(); ++Units)
452 UsedRegUnits.reset(*Units);
456 //===--------------------------------------------------------------------===//
457 // Reserved Register Info
458 //===--------------------------------------------------------------------===//
460 // The set of reserved registers must be invariant during register
461 // allocation. For example, the target cannot suddenly decide it needs a
462 // frame pointer when the register allocator has already used the frame
463 // pointer register for something else.
465 // These methods can be used by target hooks like hasFP() to avoid changing
466 // the reserved register set during register allocation.
468 /// freezeReservedRegs - Called by the register allocator to freeze the set
469 /// of reserved registers before allocation begins.
470 void freezeReservedRegs(const MachineFunction&);
472 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
473 /// to ensure the set of reserved registers stays constant.
474 bool reservedRegsFrozen() const {
475 return !ReservedRegs.empty();
478 /// canReserveReg - Returns true if PhysReg can be used as a reserved
479 /// register. Any register can be reserved before freezeReservedRegs() is
481 bool canReserveReg(unsigned PhysReg) const {
482 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
485 /// getReservedRegs - Returns a reference to the frozen set of reserved
486 /// registers. This method should always be preferred to calling
487 /// TRI::getReservedRegs() when possible.
488 const BitVector &getReservedRegs() const {
489 assert(reservedRegsFrozen() &&
490 "Reserved registers haven't been frozen yet. "
491 "Use TRI::getReservedRegs().");
495 /// isReserved - Returns true when PhysReg is a reserved register.
497 /// Reserved registers may belong to an allocatable register class, but the
498 /// target has explicitly requested that they are not used.
500 bool isReserved(unsigned PhysReg) const {
501 return getReservedRegs().test(PhysReg);
504 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
505 /// register class and it hasn't been reserved.
507 /// Allocatable registers may show up in the allocation order of some virtual
508 /// register, so a register allocator needs to track its liveness and
510 bool isAllocatable(unsigned PhysReg) const {
511 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
512 !isReserved(PhysReg);
515 //===--------------------------------------------------------------------===//
517 //===--------------------------------------------------------------------===//
519 /// addLiveIn - Add the specified register as a live-in. Note that it
520 /// is an error to add the same register to the same set more than once.
521 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
522 LiveIns.push_back(std::make_pair(Reg, vreg));
525 // Iteration support for the live-ins set. It's kept in sorted order
526 // by register number.
527 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
529 livein_iterator livein_begin() const { return LiveIns.begin(); }
530 livein_iterator livein_end() const { return LiveIns.end(); }
531 bool livein_empty() const { return LiveIns.empty(); }
533 bool isLiveIn(unsigned Reg) const;
535 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
536 /// corresponding live-in physical register.
537 unsigned getLiveInPhysReg(unsigned VReg) const;
539 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
540 /// corresponding live-in physical register.
541 unsigned getLiveInVirtReg(unsigned PReg) const;
543 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
544 /// into the given entry block.
545 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
546 const TargetRegisterInfo &TRI,
547 const TargetInstrInfo &TII);
549 /// defusechain_iterator - This class provides iterator support for machine
550 /// operands in the function that use or define a specific register. If
551 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
552 /// returns defs. If neither are true then you are silly and it always
553 /// returns end(). If SkipDebug is true it skips uses marked Debug
554 /// when incrementing.
555 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
556 class defusechain_iterator
557 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
559 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
560 // If the first node isn't one we're interested in, advance to one that
561 // we are interested in.
563 if ((!ReturnUses && op->isUse()) ||
564 (!ReturnDefs && op->isDef()) ||
565 (SkipDebug && op->isDebug()))
569 friend class MachineRegisterInfo;
571 typedef std::iterator<std::forward_iterator_tag,
572 MachineInstr, ptrdiff_t>::reference reference;
573 typedef std::iterator<std::forward_iterator_tag,
574 MachineInstr, ptrdiff_t>::pointer pointer;
576 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
577 defusechain_iterator() : Op(0) {}
579 bool operator==(const defusechain_iterator &x) const {
582 bool operator!=(const defusechain_iterator &x) const {
583 return !operator==(x);
586 /// atEnd - return true if this iterator is equal to reg_end() on the value.
587 bool atEnd() const { return Op == 0; }
589 // Iterator traversal: forward iteration only
590 defusechain_iterator &operator++() { // Preincrement
591 assert(Op && "Cannot increment end iterator!");
592 Op = getNextOperandForReg(Op);
594 // All defs come before the uses, so stop def_iterator early.
600 assert(!Op->isDebug() && "Can't have debug defs");
603 // If this is an operand we don't care about, skip it.
604 while (Op && ((!ReturnDefs && Op->isDef()) ||
605 (SkipDebug && Op->isDebug())))
606 Op = getNextOperandForReg(Op);
611 defusechain_iterator operator++(int) { // Postincrement
612 defusechain_iterator tmp = *this; ++*this; return tmp;
615 /// skipInstruction - move forward until reaching a different instruction.
616 /// Return the skipped instruction that is no longer pointed to, or NULL if
617 /// already pointing to end().
618 MachineInstr *skipInstruction() {
620 MachineInstr *MI = Op->getParent();
622 while (Op && Op->getParent() == MI);
626 MachineInstr *skipBundle() {
628 MachineInstr *MI = getBundleStart(Op->getParent());
630 while (Op && getBundleStart(Op->getParent()) == MI);
634 MachineOperand &getOperand() const {
635 assert(Op && "Cannot dereference end iterator!");
639 /// getOperandNo - Return the operand # of this MachineOperand in its
641 unsigned getOperandNo() const {
642 assert(Op && "Cannot dereference end iterator!");
643 return Op - &Op->getParent()->getOperand(0);
646 // Retrieve a reference to the current operand.
647 MachineInstr &operator*() const {
648 assert(Op && "Cannot dereference end iterator!");
649 return *Op->getParent();
652 MachineInstr *operator->() const {
653 assert(Op && "Cannot dereference end iterator!");
654 return Op->getParent();
659 /// Iterate over the pressure sets affected by the given physical or virtual
660 /// register. If Reg is physical, it must be a register unit (from
661 /// MCRegUnitIterator).
666 PSetIterator(): PSet(0), Weight(0) {}
667 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
668 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
669 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
670 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
671 PSet = TRI->getRegClassPressureSets(RC);
672 Weight = TRI->getRegClassWeight(RC).RegWeight;
675 PSet = TRI->getRegUnitPressureSets(RegUnit);
676 Weight = TRI->getRegUnitWeight(RegUnit);
681 bool isValid() const { return PSet; }
683 unsigned getWeight() const { return Weight; }
685 unsigned operator*() const { return *PSet; }
688 assert(isValid() && "Invalid PSetIterator.");
695 inline PSetIterator MachineRegisterInfo::
696 getPressureSets(unsigned RegUnit) const {
697 return PSetIterator(RegUnit, this);
700 } // End llvm namespace