1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/CodeGen/MachineInstrBundle.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/IndexedMap.h"
25 /// MachineRegisterInfo - Keep track of information for virtual and physical
26 /// registers, including vreg register classes, use/def chains for registers,
28 class MachineRegisterInfo {
29 const TargetRegisterInfo *const TRI;
31 /// IsSSA - True when the machine function is in SSA form and virtual
32 /// registers have a single def.
35 /// TracksLiveness - True while register liveness is being tracked accurately.
36 /// Basic block live-in lists, kill flags, and implicit defs may not be
37 /// accurate when after this flag is cleared.
40 /// VRegInfo - Information we keep for each virtual register.
42 /// Each element in this list contains the register class of the vreg and the
43 /// start of the use/def list for the register.
44 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
45 VirtReg2IndexFunctor> VRegInfo;
47 /// RegAllocHints - This vector records register allocation hints for virtual
48 /// registers. For each virtual register, it keeps a register and hint type
49 /// pair making up the allocation hint. Hint type is target specific except
50 /// for the value 0 which means the second value of the pair is the preferred
51 /// register for allocation. For example, if the hint is <0, 1024>, it means
52 /// the allocator should prefer the physical register allocated to the virtual
53 /// register of the hint.
54 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
56 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
57 /// physical registers.
58 MachineOperand **PhysRegUseDefLists;
60 /// UsedPhysRegs - This is a bit vector that is computed and set by the
61 /// register allocator, and must be kept up to date by passes that run after
62 /// register allocation (though most don't modify this). This is used
63 /// so that the code generator knows which callee save registers to save and
64 /// for other target specific uses.
65 /// This vector only has bits set for registers explicitly used, not their
67 BitVector UsedPhysRegs;
69 /// UsedPhysRegMask - Additional used physregs, but including aliases.
70 BitVector UsedPhysRegMask;
72 /// ReservedRegs - This is a bit vector of reserved registers. The target
73 /// may change its mind about which registers should be reserved. This
74 /// vector is the frozen set of reserved registers when register allocation
76 BitVector ReservedRegs;
78 /// AllocatableRegs - From TRI->getAllocatableSet.
79 mutable BitVector AllocatableRegs;
81 /// LiveIns/LiveOuts - Keep track of the physical registers that are
82 /// livein/liveout of the function. Live in values are typically arguments in
83 /// registers, live out values are typically return values in registers.
84 /// LiveIn values are allowed to have virtual registers associated with them,
85 /// stored in the second element.
86 std::vector<std::pair<unsigned, unsigned> > LiveIns;
87 std::vector<unsigned> LiveOuts;
89 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
90 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
92 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
93 ~MachineRegisterInfo();
95 //===--------------------------------------------------------------------===//
97 //===--------------------------------------------------------------------===//
99 // isSSA - Returns true when the machine function is in SSA form. Early
100 // passes require the machine function to be in SSA form where every virtual
101 // register has a single defining instruction.
103 // The TwoAddressInstructionPass and PHIElimination passes take the machine
104 // function out of SSA form when they introduce multiple defs per virtual
106 bool isSSA() const { return IsSSA; }
108 // leaveSSA - Indicates that the machine function is no longer in SSA form.
109 void leaveSSA() { IsSSA = false; }
111 /// tracksLiveness - Returns true when tracking register liveness accurately.
113 /// While this flag is true, register liveness information in basic block
114 /// live-in lists and machine instruction operands is accurate. This means it
115 /// can be used to change the code in ways that affect the values in
116 /// registers, for example by the register scavenger.
118 /// When this flag is false, liveness is no longer reliable.
119 bool tracksLiveness() const { return TracksLiveness; }
121 /// invalidateLiveness - Indicates that register liveness is no longer being
122 /// tracked accurately.
124 /// This should be called by late passes that invalidate the liveness
126 void invalidateLiveness() { TracksLiveness = false; }
128 //===--------------------------------------------------------------------===//
130 //===--------------------------------------------------------------------===//
132 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
133 /// and uses of a register within the MachineFunction that corresponds to this
134 /// MachineRegisterInfo object.
135 template<bool Uses, bool Defs, bool SkipDebug>
136 class defusechain_iterator;
138 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
140 typedef defusechain_iterator<true,true,false> reg_iterator;
141 reg_iterator reg_begin(unsigned RegNo) const {
142 return reg_iterator(getRegUseDefListHead(RegNo));
144 static reg_iterator reg_end() { return reg_iterator(0); }
146 /// reg_empty - Return true if there are no instructions using or defining the
147 /// specified register (it may be live-in).
148 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
150 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
151 /// of the specified register, skipping those marked as Debug.
152 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
153 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
154 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
156 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
158 /// reg_nodbg_empty - Return true if the only instructions using or defining
159 /// Reg are Debug instructions.
160 bool reg_nodbg_empty(unsigned RegNo) const {
161 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
164 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
165 typedef defusechain_iterator<false,true,false> def_iterator;
166 def_iterator def_begin(unsigned RegNo) const {
167 return def_iterator(getRegUseDefListHead(RegNo));
169 static def_iterator def_end() { return def_iterator(0); }
171 /// def_empty - Return true if there are no instructions defining the
172 /// specified register (it may be live-in).
173 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
175 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
176 typedef defusechain_iterator<true,false,false> use_iterator;
177 use_iterator use_begin(unsigned RegNo) const {
178 return use_iterator(getRegUseDefListHead(RegNo));
180 static use_iterator use_end() { return use_iterator(0); }
182 /// use_empty - Return true if there are no instructions using the specified
184 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
186 /// hasOneUse - Return true if there is exactly one instruction using the
187 /// specified register.
188 bool hasOneUse(unsigned RegNo) const;
190 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
191 /// specified register, skipping those marked as Debug.
192 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
193 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
194 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
196 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
198 /// use_nodbg_empty - Return true if there are no non-Debug instructions
199 /// using the specified register.
200 bool use_nodbg_empty(unsigned RegNo) const {
201 return use_nodbg_begin(RegNo) == use_nodbg_end();
204 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
205 /// instruction using the specified register.
206 bool hasOneNonDBGUse(unsigned RegNo) const;
208 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
209 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
210 /// except that it also changes any definitions of the register as well.
212 /// Note that it is usually necessary to first constrain ToReg's register
213 /// class to match the FromReg constraints using:
215 /// constrainRegClass(ToReg, getRegClass(FromReg))
217 /// That function will return NULL if the virtual registers have incompatible
219 void replaceRegWith(unsigned FromReg, unsigned ToReg);
221 /// getRegUseDefListHead - Return the head pointer for the register use/def
222 /// list for the specified virtual or physical register.
223 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
224 if (TargetRegisterInfo::isVirtualRegister(RegNo))
225 return VRegInfo[RegNo].second;
226 return PhysRegUseDefLists[RegNo];
229 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
230 if (TargetRegisterInfo::isVirtualRegister(RegNo))
231 return VRegInfo[RegNo].second;
232 return PhysRegUseDefLists[RegNo];
235 /// getVRegDef - Return the machine instr that defines the specified virtual
236 /// register or null if none is found. This assumes that the code is in SSA
237 /// form, so there should only be one definition.
238 MachineInstr *getVRegDef(unsigned Reg) const;
240 /// clearKillFlags - Iterate over all the uses of the given register and
241 /// clear the kill flag from the MachineOperand. This function is used by
242 /// optimization passes which extend register lifetimes and need only
243 /// preserve conservative kill flag information.
244 void clearKillFlags(unsigned Reg) const;
247 void dumpUses(unsigned RegNo) const;
250 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
251 /// throughout the function. It is safe to move instructions that read such
253 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
255 //===--------------------------------------------------------------------===//
256 // Virtual Register Info
257 //===--------------------------------------------------------------------===//
259 /// getRegClass - Return the register class of the specified virtual register.
261 const TargetRegisterClass *getRegClass(unsigned Reg) const {
262 return VRegInfo[Reg].first;
265 /// setRegClass - Set the register class of the specified virtual register.
267 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
269 /// constrainRegClass - Constrain the register class of the specified virtual
270 /// register to be a common subclass of RC and the current register class,
271 /// but only if the new class has at least MinNumRegs registers. Return the
272 /// new register class, or NULL if no such class exists.
273 /// This should only be used when the constraint is known to be trivial, like
274 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
276 const TargetRegisterClass *constrainRegClass(unsigned Reg,
277 const TargetRegisterClass *RC,
278 unsigned MinNumRegs = 0);
280 /// recomputeRegClass - Try to find a legal super-class of Reg's register
281 /// class that still satisfies the constraints from the instructions using
282 /// Reg. Returns true if Reg was upgraded.
284 /// This method can be used after constraints have been removed from a
285 /// virtual register, for example after removing instructions or splitting
288 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
290 /// createVirtualRegister - Create and return a new virtual register in the
291 /// function with the specified register class.
293 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
295 /// getNumVirtRegs - Return the number of virtual registers created.
297 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
299 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
300 void clearVirtRegs();
302 /// setRegAllocationHint - Specify a register allocation hint for the
303 /// specified virtual register.
304 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
305 RegAllocHints[Reg].first = Type;
306 RegAllocHints[Reg].second = PrefReg;
309 /// getRegAllocationHint - Return the register allocation hint for the
310 /// specified virtual register.
311 std::pair<unsigned, unsigned>
312 getRegAllocationHint(unsigned Reg) const {
313 return RegAllocHints[Reg];
316 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
317 /// standard simple hint (Type == 0) is not set.
318 unsigned getSimpleHint(unsigned Reg) const {
319 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
320 return Hint.first ? 0 : Hint.second;
324 //===--------------------------------------------------------------------===//
325 // Physical Register Use Info
326 //===--------------------------------------------------------------------===//
328 /// isPhysRegUsed - Return true if the specified register is used in this
329 /// function. This only works after register allocation.
330 bool isPhysRegUsed(unsigned Reg) const {
331 return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg);
334 /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register
335 /// is used in this function.
336 bool isPhysRegOrOverlapUsed(unsigned Reg) const {
337 if (UsedPhysRegMask.test(Reg))
339 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
340 if (UsedPhysRegs.test(*AI))
345 /// setPhysRegUsed - Mark the specified register used in this function.
346 /// This should only be called during and after register allocation.
347 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }
349 /// addPhysRegsUsed - Mark the specified registers used in this function.
350 /// This should only be called during and after register allocation.
351 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
353 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
354 /// This corresponds to the bit mask attached to register mask operands.
355 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
356 UsedPhysRegMask.setBitsNotInMask(RegMask);
359 /// setPhysRegUnused - Mark the specified register unused in this function.
360 /// This should only be called during and after register allocation.
361 void setPhysRegUnused(unsigned Reg) {
362 UsedPhysRegs.reset(Reg);
363 UsedPhysRegMask.reset(Reg);
367 //===--------------------------------------------------------------------===//
368 // Reserved Register Info
369 //===--------------------------------------------------------------------===//
371 // The set of reserved registers must be invariant during register
372 // allocation. For example, the target cannot suddenly decide it needs a
373 // frame pointer when the register allocator has already used the frame
374 // pointer register for something else.
376 // These methods can be used by target hooks like hasFP() to avoid changing
377 // the reserved register set during register allocation.
379 /// freezeReservedRegs - Called by the register allocator to freeze the set
380 /// of reserved registers before allocation begins.
381 void freezeReservedRegs(const MachineFunction&);
383 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
384 /// to ensure the set of reserved registers stays constant.
385 bool reservedRegsFrozen() const {
386 return !ReservedRegs.empty();
389 /// canReserveReg - Returns true if PhysReg can be used as a reserved
390 /// register. Any register can be reserved before freezeReservedRegs() is
392 bool canReserveReg(unsigned PhysReg) const {
393 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
397 //===--------------------------------------------------------------------===//
398 // LiveIn/LiveOut Management
399 //===--------------------------------------------------------------------===//
401 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
402 /// is an error to add the same register to the same set more than once.
403 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
404 LiveIns.push_back(std::make_pair(Reg, vreg));
406 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
408 // Iteration support for live in/out sets. These sets are kept in sorted
409 // order by their register number.
410 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
412 typedef std::vector<unsigned>::const_iterator liveout_iterator;
413 livein_iterator livein_begin() const { return LiveIns.begin(); }
414 livein_iterator livein_end() const { return LiveIns.end(); }
415 bool livein_empty() const { return LiveIns.empty(); }
416 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
417 liveout_iterator liveout_end() const { return LiveOuts.end(); }
418 bool liveout_empty() const { return LiveOuts.empty(); }
420 bool isLiveIn(unsigned Reg) const;
421 bool isLiveOut(unsigned Reg) const;
423 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
424 /// corresponding live-in physical register.
425 unsigned getLiveInPhysReg(unsigned VReg) const;
427 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
428 /// corresponding live-in physical register.
429 unsigned getLiveInVirtReg(unsigned PReg) const;
431 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
432 /// into the given entry block.
433 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
434 const TargetRegisterInfo &TRI,
435 const TargetInstrInfo &TII);
438 void HandleVRegListReallocation();
441 /// defusechain_iterator - This class provides iterator support for machine
442 /// operands in the function that use or define a specific register. If
443 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
444 /// returns defs. If neither are true then you are silly and it always
445 /// returns end(). If SkipDebug is true it skips uses marked Debug
446 /// when incrementing.
447 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
448 class defusechain_iterator
449 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
451 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
452 // If the first node isn't one we're interested in, advance to one that
453 // we are interested in.
455 if ((!ReturnUses && op->isUse()) ||
456 (!ReturnDefs && op->isDef()) ||
457 (SkipDebug && op->isDebug()))
461 friend class MachineRegisterInfo;
463 typedef std::iterator<std::forward_iterator_tag,
464 MachineInstr, ptrdiff_t>::reference reference;
465 typedef std::iterator<std::forward_iterator_tag,
466 MachineInstr, ptrdiff_t>::pointer pointer;
468 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
469 defusechain_iterator() : Op(0) {}
471 bool operator==(const defusechain_iterator &x) const {
474 bool operator!=(const defusechain_iterator &x) const {
475 return !operator==(x);
478 /// atEnd - return true if this iterator is equal to reg_end() on the value.
479 bool atEnd() const { return Op == 0; }
481 // Iterator traversal: forward iteration only
482 defusechain_iterator &operator++() { // Preincrement
483 assert(Op && "Cannot increment end iterator!");
484 Op = Op->getNextOperandForReg();
486 // If this is an operand we don't care about, skip it.
487 while (Op && ((!ReturnUses && Op->isUse()) ||
488 (!ReturnDefs && Op->isDef()) ||
489 (SkipDebug && Op->isDebug())))
490 Op = Op->getNextOperandForReg();
494 defusechain_iterator operator++(int) { // Postincrement
495 defusechain_iterator tmp = *this; ++*this; return tmp;
498 /// skipInstruction - move forward until reaching a different instruction.
499 /// Return the skipped instruction that is no longer pointed to, or NULL if
500 /// already pointing to end().
501 MachineInstr *skipInstruction() {
503 MachineInstr *MI = Op->getParent();
505 while (Op && Op->getParent() == MI);
509 MachineInstr *skipBundle() {
511 MachineInstr *MI = getBundleStart(Op->getParent());
513 while (Op && getBundleStart(Op->getParent()) == MI);
517 MachineOperand &getOperand() const {
518 assert(Op && "Cannot dereference end iterator!");
522 /// getOperandNo - Return the operand # of this MachineOperand in its
524 unsigned getOperandNo() const {
525 assert(Op && "Cannot dereference end iterator!");
526 return Op - &Op->getParent()->getOperand(0);
529 // Retrieve a reference to the current operand.
530 MachineInstr &operator*() const {
531 assert(Op && "Cannot dereference end iterator!");
532 return *Op->getParent();
535 MachineInstr *operator->() const {
536 assert(Op && "Cannot dereference end iterator!");
537 return Op->getParent();
543 } // End llvm namespace