1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
23 /// MachineRegisterInfo - Keep track of information for each virtual register,
24 /// including its register class.
25 class MachineRegisterInfo {
26 /// VRegInfo - Information we keep for each virtual register. The entries in
27 /// this vector are actually converted to vreg numbers by adding the
28 /// MRegisterInfo::FirstVirtualRegister delta to their index.
30 /// Each element in this list contains the register class of the vreg and the
31 /// start of the use/def list for the register.
32 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
34 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
35 /// physical registers.
36 MachineOperand **PhysRegUseDefLists;
38 /// UsedPhysRegs - This is a bit vector that is computed and set by the
39 /// register allocator, and must be kept up to date by passes that run after
40 /// register allocation (though most don't modify this). This is used
41 /// so that the code generator knows which callee save registers to save and
42 /// for other target specific uses.
43 BitVector UsedPhysRegs;
45 /// LiveIns/LiveOuts - Keep track of the physical registers that are
46 /// livein/liveout of the function. Live in values are typically arguments in
47 /// registers, live out values are typically return values in registers.
48 /// LiveIn values are allowed to have virtual registers associated with them,
49 /// stored in the second element.
50 std::vector<std::pair<unsigned, unsigned> > LiveIns;
51 std::vector<unsigned> LiveOuts;
53 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
54 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
56 MachineRegisterInfo(const MRegisterInfo &MRI);
57 ~MachineRegisterInfo();
59 /// getRegUseDefListHead - Return the head pointer for the register use/def
60 /// list for the specified virtual or physical register.
61 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
62 if (RegNo < MRegisterInfo::FirstVirtualRegister)
63 return PhysRegUseDefLists[RegNo];
64 RegNo -= MRegisterInfo::FirstVirtualRegister;
65 return VRegInfo[RegNo].second;
69 //===--------------------------------------------------------------------===//
70 // Virtual Register Info
71 //===--------------------------------------------------------------------===//
73 /// getRegClass - Return the register class of the specified virtual register.
74 const TargetRegisterClass *getRegClass(unsigned Reg) {
75 Reg -= MRegisterInfo::FirstVirtualRegister;
76 assert(Reg < VRegInfo.size() && "Invalid vreg!");
77 return VRegInfo[Reg].first;
80 /// createVirtualRegister - Create and return a new virtual register in the
81 /// function with the specified register class.
83 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
84 assert(RegClass && "Cannot create register without RegClass!");
85 // Add a reg, but keep track of whether the vector reallocated or not.
86 void *ArrayBase = &VRegInfo[0];
87 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
89 if (&VRegInfo[0] == ArrayBase)
90 return getLastVirtReg();
92 // Otherwise, the vector reallocated, handle this now.
93 HandleVRegListReallocation();
94 return getLastVirtReg();
97 /// getLastVirtReg - Return the highest currently assigned virtual register.
99 unsigned getLastVirtReg() const {
100 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
103 //===--------------------------------------------------------------------===//
104 // Physical Register Use Info
105 //===--------------------------------------------------------------------===//
107 /// isPhysRegUsed - Return true if the specified register is used in this
108 /// function. This only works after register allocation.
109 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
111 /// setPhysRegUsed - Mark the specified register used in this function.
112 /// This should only be called during and after register allocation.
113 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
115 /// setPhysRegUnused - Mark the specified register unused in this function.
116 /// This should only be called during and after register allocation.
117 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
120 //===--------------------------------------------------------------------===//
121 // LiveIn/LiveOut Management
122 //===--------------------------------------------------------------------===//
124 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
125 /// is an error to add the same register to the same set more than once.
126 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
127 LiveIns.push_back(std::make_pair(Reg, vreg));
129 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
131 // Iteration support for live in/out sets. These sets are kept in sorted
132 // order by their register number.
133 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
135 typedef std::vector<unsigned>::const_iterator liveout_iterator;
136 livein_iterator livein_begin() const { return LiveIns.begin(); }
137 livein_iterator livein_end() const { return LiveIns.end(); }
138 bool livein_empty() const { return LiveIns.empty(); }
139 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
140 liveout_iterator liveout_end() const { return LiveOuts.end(); }
141 bool liveout_empty() const { return LiveOuts.empty(); }
143 void HandleVRegListReallocation();
146 } // End llvm namespace