1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBundle.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
29 /// MachineRegisterInfo - Keep track of information for virtual and physical
30 /// registers, including vreg register classes, use/def chains for registers,
32 class MachineRegisterInfo {
35 virtual void anchor();
37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
39 virtual ~Delegate() {}
43 const MachineFunction *MF;
44 Delegate *TheDelegate;
46 /// IsSSA - True when the machine function is in SSA form and virtual
47 /// registers have a single def.
50 /// TracksLiveness - True while register liveness is being tracked accurately.
51 /// Basic block live-in lists, kill flags, and implicit defs may not be
52 /// accurate when after this flag is cleared.
55 /// True if subregister liveness is tracked.
56 bool TracksSubRegLiveness;
58 /// VRegInfo - Information we keep for each virtual register.
60 /// Each element in this list contains the register class of the vreg and the
61 /// start of the use/def list for the register.
62 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
63 VirtReg2IndexFunctor> VRegInfo;
65 /// RegAllocHints - This vector records register allocation hints for virtual
66 /// registers. For each virtual register, it keeps a register and hint type
67 /// pair making up the allocation hint. Hint type is target specific except
68 /// for the value 0 which means the second value of the pair is the preferred
69 /// register for allocation. For example, if the hint is <0, 1024>, it means
70 /// the allocator should prefer the physical register allocated to the virtual
71 /// register of the hint.
72 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
74 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
75 /// physical registers.
76 std::vector<MachineOperand *> PhysRegUseDefLists;
78 /// getRegUseDefListHead - Return the head pointer for the register use/def
79 /// list for the specified virtual or physical register.
80 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
81 if (TargetRegisterInfo::isVirtualRegister(RegNo))
82 return VRegInfo[RegNo].second;
83 return PhysRegUseDefLists[RegNo];
86 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
87 if (TargetRegisterInfo::isVirtualRegister(RegNo))
88 return VRegInfo[RegNo].second;
89 return PhysRegUseDefLists[RegNo];
92 /// Get the next element in the use-def chain.
93 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
94 assert(MO && MO->isReg() && "This is not a register operand!");
95 return MO->Contents.Reg.Next;
98 /// UsedPhysRegMask - Additional used physregs including aliases.
99 /// This bit vector represents all the registers clobbered by function calls.
100 BitVector UsedPhysRegMask;
102 /// ReservedRegs - This is a bit vector of reserved registers. The target
103 /// may change its mind about which registers should be reserved. This
104 /// vector is the frozen set of reserved registers when register allocation
106 BitVector ReservedRegs;
108 /// Keep track of the physical registers that are live in to the function.
109 /// Live in values are typically arguments in registers. LiveIn values are
110 /// allowed to have virtual registers associated with them, stored in the
112 std::vector<std::pair<unsigned, unsigned> > LiveIns;
114 MachineRegisterInfo(const MachineRegisterInfo&) = delete;
115 void operator=(const MachineRegisterInfo&) = delete;
117 explicit MachineRegisterInfo(const MachineFunction *MF);
119 const TargetRegisterInfo *getTargetRegisterInfo() const {
120 return MF->getSubtarget().getRegisterInfo();
123 void resetDelegate(Delegate *delegate) {
124 // Ensure another delegate does not take over unless the current
125 // delegate first unattaches itself. If we ever need to multicast
126 // notifications, we will need to change to using a list.
127 assert(TheDelegate == delegate &&
128 "Only the current delegate can perform reset!");
129 TheDelegate = nullptr;
132 void setDelegate(Delegate *delegate) {
133 assert(delegate && !TheDelegate &&
134 "Attempted to set delegate to null, or to change it without "
135 "first resetting it!");
137 TheDelegate = delegate;
140 //===--------------------------------------------------------------------===//
142 //===--------------------------------------------------------------------===//
144 // isSSA - Returns true when the machine function is in SSA form. Early
145 // passes require the machine function to be in SSA form where every virtual
146 // register has a single defining instruction.
148 // The TwoAddressInstructionPass and PHIElimination passes take the machine
149 // function out of SSA form when they introduce multiple defs per virtual
151 bool isSSA() const { return IsSSA; }
153 // leaveSSA - Indicates that the machine function is no longer in SSA form.
154 void leaveSSA() { IsSSA = false; }
156 /// tracksLiveness - Returns true when tracking register liveness accurately.
158 /// While this flag is true, register liveness information in basic block
159 /// live-in lists and machine instruction operands is accurate. This means it
160 /// can be used to change the code in ways that affect the values in
161 /// registers, for example by the register scavenger.
163 /// When this flag is false, liveness is no longer reliable.
164 bool tracksLiveness() const { return TracksLiveness; }
166 /// invalidateLiveness - Indicates that register liveness is no longer being
167 /// tracked accurately.
169 /// This should be called by late passes that invalidate the liveness
171 void invalidateLiveness() { TracksLiveness = false; }
173 /// Returns true if liveness for register class @p RC should be tracked at
174 /// the subregister level.
175 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
176 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
178 bool shouldTrackSubRegLiveness(unsigned VReg) const {
179 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
180 return shouldTrackSubRegLiveness(*getRegClass(VReg));
182 bool subRegLivenessEnabled() const {
183 return TracksSubRegLiveness;
186 void enableSubRegLiveness(bool Enable = true) {
187 TracksSubRegLiveness = Enable;
190 //===--------------------------------------------------------------------===//
192 //===--------------------------------------------------------------------===//
194 // Strictly for use by MachineInstr.cpp.
195 void addRegOperandToUseList(MachineOperand *MO);
197 // Strictly for use by MachineInstr.cpp.
198 void removeRegOperandFromUseList(MachineOperand *MO);
200 // Strictly for use by MachineInstr.cpp.
201 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
203 /// Verify the sanity of the use list for Reg.
204 void verifyUseList(unsigned Reg) const;
206 /// Verify the use list of all registers.
207 void verifyUseLists() const;
209 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
210 /// and uses of a register within the MachineFunction that corresponds to this
211 /// MachineRegisterInfo object.
212 template<bool Uses, bool Defs, bool SkipDebug,
213 bool ByOperand, bool ByInstr, bool ByBundle>
214 class defusechain_iterator;
215 template<bool Uses, bool Defs, bool SkipDebug,
216 bool ByOperand, bool ByInstr, bool ByBundle>
217 class defusechain_instr_iterator;
219 // Make it a friend so it can access getNextOperandForReg().
220 template<bool, bool, bool, bool, bool, bool>
221 friend class defusechain_iterator;
222 template<bool, bool, bool, bool, bool, bool>
223 friend class defusechain_instr_iterator;
227 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
229 typedef defusechain_iterator<true,true,false,true,false,false>
231 reg_iterator reg_begin(unsigned RegNo) const {
232 return reg_iterator(getRegUseDefListHead(RegNo));
234 static reg_iterator reg_end() { return reg_iterator(nullptr); }
236 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
237 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
240 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
241 /// of the specified register, stepping by MachineInstr.
242 typedef defusechain_instr_iterator<true,true,false,false,true,false>
244 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
245 return reg_instr_iterator(getRegUseDefListHead(RegNo));
247 static reg_instr_iterator reg_instr_end() {
248 return reg_instr_iterator(nullptr);
251 inline iterator_range<reg_instr_iterator>
252 reg_instructions(unsigned Reg) const {
253 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
257 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
258 /// of the specified register, stepping by bundle.
259 typedef defusechain_instr_iterator<true,true,false,false,false,true>
261 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
262 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
264 static reg_bundle_iterator reg_bundle_end() {
265 return reg_bundle_iterator(nullptr);
268 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
269 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
273 /// reg_empty - Return true if there are no instructions using or defining the
274 /// specified register (it may be live-in).
275 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
277 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
278 /// of the specified register, skipping those marked as Debug.
279 typedef defusechain_iterator<true,true,true,true,false,false>
281 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
282 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
284 static reg_nodbg_iterator reg_nodbg_end() {
285 return reg_nodbg_iterator(nullptr);
288 inline iterator_range<reg_nodbg_iterator>
289 reg_nodbg_operands(unsigned Reg) const {
290 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
294 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
295 /// all defs and uses of the specified register, stepping by MachineInstr,
296 /// skipping those marked as Debug.
297 typedef defusechain_instr_iterator<true,true,true,false,true,false>
298 reg_instr_nodbg_iterator;
299 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
300 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
302 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
303 return reg_instr_nodbg_iterator(nullptr);
306 inline iterator_range<reg_instr_nodbg_iterator>
307 reg_nodbg_instructions(unsigned Reg) const {
308 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
309 reg_instr_nodbg_end());
312 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
313 /// all defs and uses of the specified register, stepping by bundle,
314 /// skipping those marked as Debug.
315 typedef defusechain_instr_iterator<true,true,true,false,false,true>
316 reg_bundle_nodbg_iterator;
317 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
318 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
320 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
321 return reg_bundle_nodbg_iterator(nullptr);
324 inline iterator_range<reg_bundle_nodbg_iterator>
325 reg_nodbg_bundles(unsigned Reg) const {
326 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
327 reg_bundle_nodbg_end());
330 /// reg_nodbg_empty - Return true if the only instructions using or defining
331 /// Reg are Debug instructions.
332 bool reg_nodbg_empty(unsigned RegNo) const {
333 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
336 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
337 typedef defusechain_iterator<false,true,false,true,false,false>
339 def_iterator def_begin(unsigned RegNo) const {
340 return def_iterator(getRegUseDefListHead(RegNo));
342 static def_iterator def_end() { return def_iterator(nullptr); }
344 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
345 return iterator_range<def_iterator>(def_begin(Reg), def_end());
348 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
349 /// specified register, stepping by MachineInst.
350 typedef defusechain_instr_iterator<false,true,false,false,true,false>
352 def_instr_iterator def_instr_begin(unsigned RegNo) const {
353 return def_instr_iterator(getRegUseDefListHead(RegNo));
355 static def_instr_iterator def_instr_end() {
356 return def_instr_iterator(nullptr);
359 inline iterator_range<def_instr_iterator>
360 def_instructions(unsigned Reg) const {
361 return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
365 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
366 /// specified register, stepping by bundle.
367 typedef defusechain_instr_iterator<false,true,false,false,false,true>
369 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
370 return def_bundle_iterator(getRegUseDefListHead(RegNo));
372 static def_bundle_iterator def_bundle_end() {
373 return def_bundle_iterator(nullptr);
376 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
377 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
381 /// def_empty - Return true if there are no instructions defining the
382 /// specified register (it may be live-in).
383 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
385 /// hasOneDef - Return true if there is exactly one instruction defining the
386 /// specified register.
387 bool hasOneDef(unsigned RegNo) const {
388 def_iterator DI = def_begin(RegNo);
391 return ++DI == def_end();
394 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
395 typedef defusechain_iterator<true,false,false,true,false,false>
397 use_iterator use_begin(unsigned RegNo) const {
398 return use_iterator(getRegUseDefListHead(RegNo));
400 static use_iterator use_end() { return use_iterator(nullptr); }
402 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
403 return iterator_range<use_iterator>(use_begin(Reg), use_end());
406 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
407 /// specified register, stepping by MachineInstr.
408 typedef defusechain_instr_iterator<true,false,false,false,true,false>
410 use_instr_iterator use_instr_begin(unsigned RegNo) const {
411 return use_instr_iterator(getRegUseDefListHead(RegNo));
413 static use_instr_iterator use_instr_end() {
414 return use_instr_iterator(nullptr);
417 inline iterator_range<use_instr_iterator>
418 use_instructions(unsigned Reg) const {
419 return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
423 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
424 /// specified register, stepping by bundle.
425 typedef defusechain_instr_iterator<true,false,false,false,false,true>
427 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
428 return use_bundle_iterator(getRegUseDefListHead(RegNo));
430 static use_bundle_iterator use_bundle_end() {
431 return use_bundle_iterator(nullptr);
434 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
435 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
439 /// use_empty - Return true if there are no instructions using the specified
441 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
443 /// hasOneUse - Return true if there is exactly one instruction using the
444 /// specified register.
445 bool hasOneUse(unsigned RegNo) const {
446 use_iterator UI = use_begin(RegNo);
449 return ++UI == use_end();
452 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
453 /// specified register, skipping those marked as Debug.
454 typedef defusechain_iterator<true,false,true,true,false,false>
456 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
457 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
459 static use_nodbg_iterator use_nodbg_end() {
460 return use_nodbg_iterator(nullptr);
463 inline iterator_range<use_nodbg_iterator>
464 use_nodbg_operands(unsigned Reg) const {
465 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
469 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
470 /// all uses of the specified register, stepping by MachineInstr, skipping
471 /// those marked as Debug.
472 typedef defusechain_instr_iterator<true,false,true,false,true,false>
473 use_instr_nodbg_iterator;
474 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
475 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
477 static use_instr_nodbg_iterator use_instr_nodbg_end() {
478 return use_instr_nodbg_iterator(nullptr);
481 inline iterator_range<use_instr_nodbg_iterator>
482 use_nodbg_instructions(unsigned Reg) const {
483 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
484 use_instr_nodbg_end());
487 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
488 /// all uses of the specified register, stepping by bundle, skipping
489 /// those marked as Debug.
490 typedef defusechain_instr_iterator<true,false,true,false,false,true>
491 use_bundle_nodbg_iterator;
492 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
493 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
495 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
496 return use_bundle_nodbg_iterator(nullptr);
499 inline iterator_range<use_bundle_nodbg_iterator>
500 use_nodbg_bundles(unsigned Reg) const {
501 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
502 use_bundle_nodbg_end());
505 /// use_nodbg_empty - Return true if there are no non-Debug instructions
506 /// using the specified register.
507 bool use_nodbg_empty(unsigned RegNo) const {
508 return use_nodbg_begin(RegNo) == use_nodbg_end();
511 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
512 /// instruction using the specified register.
513 bool hasOneNonDBGUse(unsigned RegNo) const;
515 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
516 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
517 /// except that it also changes any definitions of the register as well.
519 /// Note that it is usually necessary to first constrain ToReg's register
520 /// class to match the FromReg constraints using:
522 /// constrainRegClass(ToReg, getRegClass(FromReg))
524 /// That function will return NULL if the virtual registers have incompatible
527 /// Note that if ToReg is a physical register the function will replace and
528 /// apply sub registers to ToReg in order to obtain a final/proper physical
530 void replaceRegWith(unsigned FromReg, unsigned ToReg);
532 /// getVRegDef - Return the machine instr that defines the specified virtual
533 /// register or null if none is found. This assumes that the code is in SSA
534 /// form, so there should only be one definition.
535 MachineInstr *getVRegDef(unsigned Reg) const;
537 /// getUniqueVRegDef - Return the unique machine instr that defines the
538 /// specified virtual register or null if none is found. If there are
539 /// multiple definitions or no definition, return null.
540 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
542 /// clearKillFlags - Iterate over all the uses of the given register and
543 /// clear the kill flag from the MachineOperand. This function is used by
544 /// optimization passes which extend register lifetimes and need only
545 /// preserve conservative kill flag information.
546 void clearKillFlags(unsigned Reg) const;
549 void dumpUses(unsigned RegNo) const;
552 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
553 /// throughout the function. It is safe to move instructions that read such
555 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
557 /// Get an iterator over the pressure sets affected by the given physical or
558 /// virtual register. If RegUnit is physical, it must be a register unit (from
559 /// MCRegUnitIterator).
560 PSetIterator getPressureSets(unsigned RegUnit) const;
562 //===--------------------------------------------------------------------===//
563 // Virtual Register Info
564 //===--------------------------------------------------------------------===//
566 /// getRegClass - Return the register class of the specified virtual register.
568 const TargetRegisterClass *getRegClass(unsigned Reg) const {
569 return VRegInfo[Reg].first;
572 /// setRegClass - Set the register class of the specified virtual register.
574 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
576 /// constrainRegClass - Constrain the register class of the specified virtual
577 /// register to be a common subclass of RC and the current register class,
578 /// but only if the new class has at least MinNumRegs registers. Return the
579 /// new register class, or NULL if no such class exists.
580 /// This should only be used when the constraint is known to be trivial, like
581 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
583 const TargetRegisterClass *constrainRegClass(unsigned Reg,
584 const TargetRegisterClass *RC,
585 unsigned MinNumRegs = 0);
587 /// recomputeRegClass - Try to find a legal super-class of Reg's register
588 /// class that still satisfies the constraints from the instructions using
589 /// Reg. Returns true if Reg was upgraded.
591 /// This method can be used after constraints have been removed from a
592 /// virtual register, for example after removing instructions or splitting
595 bool recomputeRegClass(unsigned Reg);
597 /// createVirtualRegister - Create and return a new virtual register in the
598 /// function with the specified register class.
600 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
602 /// getNumVirtRegs - Return the number of virtual registers created.
604 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
606 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
607 void clearVirtRegs();
609 /// setRegAllocationHint - Specify a register allocation hint for the
610 /// specified virtual register.
611 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
612 assert(TargetRegisterInfo::isVirtualRegister(VReg));
613 RegAllocHints[VReg].first = Type;
614 RegAllocHints[VReg].second = PrefReg;
617 /// getRegAllocationHint - Return the register allocation hint for the
618 /// specified virtual register.
619 std::pair<unsigned, unsigned>
620 getRegAllocationHint(unsigned VReg) const {
621 assert(TargetRegisterInfo::isVirtualRegister(VReg));
622 return RegAllocHints[VReg];
625 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
626 /// standard simple hint (Type == 0) is not set.
627 unsigned getSimpleHint(unsigned VReg) const {
628 assert(TargetRegisterInfo::isVirtualRegister(VReg));
629 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
630 return Hint.first ? 0 : Hint.second;
633 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
634 /// specified register as undefined which causes the DBG_VALUE to be
635 /// deleted during LiveDebugVariables analysis.
636 void markUsesInDebugValueAsUndef(unsigned Reg) const;
638 /// Return true if the specified register is modified in this function.
639 /// This checks that no defining machine operands exist for the register or
640 /// any of its aliases. Definitions found on functions marked noreturn are
642 bool isPhysRegModified(unsigned PhysReg) const;
644 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
645 /// This corresponds to the bit mask attached to register mask operands.
646 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
647 UsedPhysRegMask.setBitsNotInMask(RegMask);
650 //===--------------------------------------------------------------------===//
651 // Reserved Register Info
652 //===--------------------------------------------------------------------===//
654 // The set of reserved registers must be invariant during register
655 // allocation. For example, the target cannot suddenly decide it needs a
656 // frame pointer when the register allocator has already used the frame
657 // pointer register for something else.
659 // These methods can be used by target hooks like hasFP() to avoid changing
660 // the reserved register set during register allocation.
662 /// freezeReservedRegs - Called by the register allocator to freeze the set
663 /// of reserved registers before allocation begins.
664 void freezeReservedRegs(const MachineFunction&);
666 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
667 /// to ensure the set of reserved registers stays constant.
668 bool reservedRegsFrozen() const {
669 return !ReservedRegs.empty();
672 /// canReserveReg - Returns true if PhysReg can be used as a reserved
673 /// register. Any register can be reserved before freezeReservedRegs() is
675 bool canReserveReg(unsigned PhysReg) const {
676 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
679 /// getReservedRegs - Returns a reference to the frozen set of reserved
680 /// registers. This method should always be preferred to calling
681 /// TRI::getReservedRegs() when possible.
682 const BitVector &getReservedRegs() const {
683 assert(reservedRegsFrozen() &&
684 "Reserved registers haven't been frozen yet. "
685 "Use TRI::getReservedRegs().");
689 /// isReserved - Returns true when PhysReg is a reserved register.
691 /// Reserved registers may belong to an allocatable register class, but the
692 /// target has explicitly requested that they are not used.
694 bool isReserved(unsigned PhysReg) const {
695 return getReservedRegs().test(PhysReg);
698 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
699 /// register class and it hasn't been reserved.
701 /// Allocatable registers may show up in the allocation order of some virtual
702 /// register, so a register allocator needs to track its liveness and
704 bool isAllocatable(unsigned PhysReg) const {
705 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
706 !isReserved(PhysReg);
709 //===--------------------------------------------------------------------===//
711 //===--------------------------------------------------------------------===//
713 /// addLiveIn - Add the specified register as a live-in. Note that it
714 /// is an error to add the same register to the same set more than once.
715 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
716 LiveIns.push_back(std::make_pair(Reg, vreg));
719 // Iteration support for the live-ins set. It's kept in sorted order
720 // by register number.
721 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
723 livein_iterator livein_begin() const { return LiveIns.begin(); }
724 livein_iterator livein_end() const { return LiveIns.end(); }
725 bool livein_empty() const { return LiveIns.empty(); }
727 bool isLiveIn(unsigned Reg) const;
729 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
730 /// corresponding live-in physical register.
731 unsigned getLiveInPhysReg(unsigned VReg) const;
733 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
734 /// corresponding live-in physical register.
735 unsigned getLiveInVirtReg(unsigned PReg) const;
737 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
738 /// into the given entry block.
739 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
740 const TargetRegisterInfo &TRI,
741 const TargetInstrInfo &TII);
743 /// Returns a mask covering all bits that can appear in lane masks of
744 /// subregisters of the virtual register @p Reg.
745 unsigned getMaxLaneMaskForVReg(unsigned Reg) const;
747 /// defusechain_iterator - This class provides iterator support for machine
748 /// operands in the function that use or define a specific register. If
749 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
750 /// returns defs. If neither are true then you are silly and it always
751 /// returns end(). If SkipDebug is true it skips uses marked Debug
752 /// when incrementing.
753 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
754 bool ByOperand, bool ByInstr, bool ByBundle>
755 class defusechain_iterator
756 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
758 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
759 // If the first node isn't one we're interested in, advance to one that
760 // we are interested in.
762 if ((!ReturnUses && op->isUse()) ||
763 (!ReturnDefs && op->isDef()) ||
764 (SkipDebug && op->isDebug()))
768 friend class MachineRegisterInfo;
771 assert(Op && "Cannot increment end iterator!");
772 Op = getNextOperandForReg(Op);
774 // All defs come before the uses, so stop def_iterator early.
780 assert(!Op->isDebug() && "Can't have debug defs");
783 // If this is an operand we don't care about, skip it.
784 while (Op && ((!ReturnDefs && Op->isDef()) ||
785 (SkipDebug && Op->isDebug())))
786 Op = getNextOperandForReg(Op);
790 typedef std::iterator<std::forward_iterator_tag,
791 MachineInstr, ptrdiff_t>::reference reference;
792 typedef std::iterator<std::forward_iterator_tag,
793 MachineInstr, ptrdiff_t>::pointer pointer;
795 defusechain_iterator() : Op(nullptr) {}
797 bool operator==(const defusechain_iterator &x) const {
800 bool operator!=(const defusechain_iterator &x) const {
801 return !operator==(x);
804 /// atEnd - return true if this iterator is equal to reg_end() on the value.
805 bool atEnd() const { return Op == nullptr; }
807 // Iterator traversal: forward iteration only
808 defusechain_iterator &operator++() { // Preincrement
809 assert(Op && "Cannot increment end iterator!");
813 MachineInstr *P = Op->getParent();
816 } while (Op && Op->getParent() == P);
817 } else if (ByBundle) {
818 MachineInstr *P = getBundleStart(Op->getParent());
821 } while (Op && getBundleStart(Op->getParent()) == P);
826 defusechain_iterator operator++(int) { // Postincrement
827 defusechain_iterator tmp = *this; ++*this; return tmp;
830 /// getOperandNo - Return the operand # of this MachineOperand in its
832 unsigned getOperandNo() const {
833 assert(Op && "Cannot dereference end iterator!");
834 return Op - &Op->getParent()->getOperand(0);
837 // Retrieve a reference to the current operand.
838 MachineOperand &operator*() const {
839 assert(Op && "Cannot dereference end iterator!");
843 MachineOperand *operator->() const {
844 assert(Op && "Cannot dereference end iterator!");
849 /// defusechain_iterator - This class provides iterator support for machine
850 /// operands in the function that use or define a specific register. If
851 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
852 /// returns defs. If neither are true then you are silly and it always
853 /// returns end(). If SkipDebug is true it skips uses marked Debug
854 /// when incrementing.
855 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
856 bool ByOperand, bool ByInstr, bool ByBundle>
857 class defusechain_instr_iterator
858 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
860 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
861 // If the first node isn't one we're interested in, advance to one that
862 // we are interested in.
864 if ((!ReturnUses && op->isUse()) ||
865 (!ReturnDefs && op->isDef()) ||
866 (SkipDebug && op->isDebug()))
870 friend class MachineRegisterInfo;
873 assert(Op && "Cannot increment end iterator!");
874 Op = getNextOperandForReg(Op);
876 // All defs come before the uses, so stop def_iterator early.
882 assert(!Op->isDebug() && "Can't have debug defs");
885 // If this is an operand we don't care about, skip it.
886 while (Op && ((!ReturnDefs && Op->isDef()) ||
887 (SkipDebug && Op->isDebug())))
888 Op = getNextOperandForReg(Op);
892 typedef std::iterator<std::forward_iterator_tag,
893 MachineInstr, ptrdiff_t>::reference reference;
894 typedef std::iterator<std::forward_iterator_tag,
895 MachineInstr, ptrdiff_t>::pointer pointer;
897 defusechain_instr_iterator() : Op(nullptr) {}
899 bool operator==(const defusechain_instr_iterator &x) const {
902 bool operator!=(const defusechain_instr_iterator &x) const {
903 return !operator==(x);
906 /// atEnd - return true if this iterator is equal to reg_end() on the value.
907 bool atEnd() const { return Op == nullptr; }
909 // Iterator traversal: forward iteration only
910 defusechain_instr_iterator &operator++() { // Preincrement
911 assert(Op && "Cannot increment end iterator!");
915 MachineInstr *P = Op->getParent();
918 } while (Op && Op->getParent() == P);
919 } else if (ByBundle) {
920 MachineInstr *P = getBundleStart(Op->getParent());
923 } while (Op && getBundleStart(Op->getParent()) == P);
928 defusechain_instr_iterator operator++(int) { // Postincrement
929 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
932 // Retrieve a reference to the current operand.
933 MachineInstr &operator*() const {
934 assert(Op && "Cannot dereference end iterator!");
935 if (ByBundle) return *(getBundleStart(Op->getParent()));
936 return *Op->getParent();
939 MachineInstr *operator->() const {
940 assert(Op && "Cannot dereference end iterator!");
941 if (ByBundle) return getBundleStart(Op->getParent());
942 return Op->getParent();
947 /// Iterate over the pressure sets affected by the given physical or virtual
948 /// register. If Reg is physical, it must be a register unit (from
949 /// MCRegUnitIterator).
954 PSetIterator(): PSet(nullptr), Weight(0) {}
955 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
956 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
957 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
958 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
959 PSet = TRI->getRegClassPressureSets(RC);
960 Weight = TRI->getRegClassWeight(RC).RegWeight;
963 PSet = TRI->getRegUnitPressureSets(RegUnit);
964 Weight = TRI->getRegUnitWeight(RegUnit);
969 bool isValid() const { return PSet; }
971 unsigned getWeight() const { return Weight; }
973 unsigned operator*() const { return *PSet; }
976 assert(isValid() && "Invalid PSetIterator.");
983 inline PSetIterator MachineRegisterInfo::
984 getPressureSets(unsigned RegUnit) const {
985 return PSetIterator(RegUnit, this);
988 } // End llvm namespace