1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Support/DebugLoc.h"
26 /// MachineRegisterInfo - Keep track of information for virtual and physical
27 /// registers, including vreg register classes, use/def chains for registers,
29 class MachineRegisterInfo {
30 /// VRegInfo - Information we keep for each virtual register.
32 /// Each element in this list contains the register class of the vreg and the
33 /// start of the use/def list for the register.
34 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
35 VirtReg2IndexFunctor> VRegInfo;
37 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
38 /// virtual registers. For each target register class, it keeps a list of
39 /// virtual registers belonging to the class.
40 std::vector<unsigned> *RegClass2VRegMap;
42 /// RegAllocHints - This vector records register allocation hints for virtual
43 /// registers. For each virtual register, it keeps a register and hint type
44 /// pair making up the allocation hint. Hint type is target specific except
45 /// for the value 0 which means the second value of the pair is the preferred
46 /// register for allocation. For example, if the hint is <0, 1024>, it means
47 /// the allocator should prefer the physical register allocated to the virtual
48 /// register of the hint.
49 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
51 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
52 /// physical registers.
53 MachineOperand **PhysRegUseDefLists;
55 /// UsedPhysRegs - This is a bit vector that is computed and set by the
56 /// register allocator, and must be kept up to date by passes that run after
57 /// register allocation (though most don't modify this). This is used
58 /// so that the code generator knows which callee save registers to save and
59 /// for other target specific uses.
60 BitVector UsedPhysRegs;
62 /// LiveIns/LiveOuts - Keep track of the physical registers that are
63 /// livein/liveout of the function. Live in values are typically arguments in
64 /// registers, live out values are typically return values in registers.
65 /// LiveIn values are allowed to have virtual registers associated with them,
66 /// stored in the second element.
67 std::vector<std::pair<unsigned, unsigned> > LiveIns;
68 std::vector<unsigned> LiveOuts;
70 /// LiveInLocs - Keep track of location livein registers.
71 DenseMap<unsigned, DebugLoc> LiveInLocs;
73 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
74 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
76 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
77 ~MachineRegisterInfo();
79 //===--------------------------------------------------------------------===//
81 //===--------------------------------------------------------------------===//
83 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
84 /// and uses of a register within the MachineFunction that corresponds to this
85 /// MachineRegisterInfo object.
86 template<bool Uses, bool Defs, bool SkipDebug>
87 class defusechain_iterator;
89 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
91 typedef defusechain_iterator<true,true,false> reg_iterator;
92 reg_iterator reg_begin(unsigned RegNo) const {
93 return reg_iterator(getRegUseDefListHead(RegNo));
95 static reg_iterator reg_end() { return reg_iterator(0); }
97 /// reg_empty - Return true if there are no instructions using or defining the
98 /// specified register (it may be live-in).
99 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
101 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
102 /// of the specified register, skipping those marked as Debug.
103 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
104 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
105 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
107 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
109 /// reg_nodbg_empty - Return true if the only instructions using or defining
110 /// Reg are Debug instructions.
111 bool reg_nodbg_empty(unsigned RegNo) const {
112 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
115 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
116 typedef defusechain_iterator<false,true,false> def_iterator;
117 def_iterator def_begin(unsigned RegNo) const {
118 return def_iterator(getRegUseDefListHead(RegNo));
120 static def_iterator def_end() { return def_iterator(0); }
122 /// def_empty - Return true if there are no instructions defining the
123 /// specified register (it may be live-in).
124 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
126 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
127 typedef defusechain_iterator<true,false,false> use_iterator;
128 use_iterator use_begin(unsigned RegNo) const {
129 return use_iterator(getRegUseDefListHead(RegNo));
131 static use_iterator use_end() { return use_iterator(0); }
133 /// use_empty - Return true if there are no instructions using the specified
135 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
137 /// hasOneUse - Return true if there is exactly one instruction using the
138 /// specified register.
139 bool hasOneUse(unsigned RegNo) const;
141 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
142 /// specified register, skipping those marked as Debug.
143 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
144 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
145 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
147 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
149 /// use_nodbg_empty - Return true if there are no non-Debug instructions
150 /// using the specified register.
151 bool use_nodbg_empty(unsigned RegNo) const {
152 return use_nodbg_begin(RegNo) == use_nodbg_end();
155 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
156 /// instruction using the specified register.
157 bool hasOneNonDBGUse(unsigned RegNo) const;
159 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
160 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
161 /// except that it also changes any definitions of the register as well.
162 void replaceRegWith(unsigned FromReg, unsigned ToReg);
164 /// getRegUseDefListHead - Return the head pointer for the register use/def
165 /// list for the specified virtual or physical register.
166 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
167 if (TargetRegisterInfo::isVirtualRegister(RegNo))
168 return VRegInfo[RegNo].second;
169 return PhysRegUseDefLists[RegNo];
172 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
173 if (TargetRegisterInfo::isVirtualRegister(RegNo))
174 return VRegInfo[RegNo].second;
175 return PhysRegUseDefLists[RegNo];
178 /// getVRegDef - Return the machine instr that defines the specified virtual
179 /// register or null if none is found. This assumes that the code is in SSA
180 /// form, so there should only be one definition.
181 MachineInstr *getVRegDef(unsigned Reg) const;
183 /// clearKillFlags - Iterate over all the uses of the given register and
184 /// clear the kill flag from the MachineOperand. This function is used by
185 /// optimization passes which extend register lifetimes and need only
186 /// preserve conservative kill flag information.
187 void clearKillFlags(unsigned Reg) const;
190 void dumpUses(unsigned RegNo) const;
193 //===--------------------------------------------------------------------===//
194 // Virtual Register Info
195 //===--------------------------------------------------------------------===//
197 /// getRegClass - Return the register class of the specified virtual register.
199 const TargetRegisterClass *getRegClass(unsigned Reg) const {
200 return VRegInfo[Reg].first;
203 /// setRegClass - Set the register class of the specified virtual register.
205 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
207 /// constrainRegClass - Constrain the register class of the specified virtual
208 /// register to be a common subclass of RC and the current register class.
209 /// Return the new register class, or NULL if no such class exists.
210 /// This should only be used when the constraint is known to be trivial, like
211 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
212 const TargetRegisterClass *constrainRegClass(unsigned Reg,
213 const TargetRegisterClass *RC);
215 /// createVirtualRegister - Create and return a new virtual register in the
216 /// function with the specified register class.
218 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
220 /// getNumVirtRegs - Return the number of virtual registers created.
222 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
224 /// getRegClassVirtRegs - Return the list of virtual registers of the given
225 /// target register class.
226 const std::vector<unsigned> &
227 getRegClassVirtRegs(const TargetRegisterClass *RC) const {
228 return RegClass2VRegMap[RC->getID()];
231 /// setRegAllocationHint - Specify a register allocation hint for the
232 /// specified virtual register.
233 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
234 RegAllocHints[Reg].first = Type;
235 RegAllocHints[Reg].second = PrefReg;
238 /// getRegAllocationHint - Return the register allocation hint for the
239 /// specified virtual register.
240 std::pair<unsigned, unsigned>
241 getRegAllocationHint(unsigned Reg) const {
242 return RegAllocHints[Reg];
245 //===--------------------------------------------------------------------===//
246 // Physical Register Use Info
247 //===--------------------------------------------------------------------===//
249 /// isPhysRegUsed - Return true if the specified register is used in this
250 /// function. This only works after register allocation.
251 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
253 /// setPhysRegUsed - Mark the specified register used in this function.
254 /// This should only be called during and after register allocation.
255 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
257 /// addPhysRegsUsed - Mark the specified registers used in this function.
258 /// This should only be called during and after register allocation.
259 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
261 /// setPhysRegUnused - Mark the specified register unused in this function.
262 /// This should only be called during and after register allocation.
263 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
265 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over
266 /// subregisters. That means that if R is used, so are all subregisters.
267 void closePhysRegsUsed(const TargetRegisterInfo&);
269 //===--------------------------------------------------------------------===//
270 // LiveIn/LiveOut Management
271 //===--------------------------------------------------------------------===//
273 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
274 /// is an error to add the same register to the same set more than once.
275 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
276 LiveIns.push_back(std::make_pair(Reg, vreg));
278 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
280 /// addLiveInLoc - Keep track of location info for live in reg.
281 void addLiveInLoc(unsigned VReg, DebugLoc DL) {
282 LiveInLocs[VReg] = DL;
285 // Iteration support for live in/out sets. These sets are kept in sorted
286 // order by their register number.
287 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
289 typedef std::vector<unsigned>::const_iterator liveout_iterator;
290 livein_iterator livein_begin() const { return LiveIns.begin(); }
291 livein_iterator livein_end() const { return LiveIns.end(); }
292 bool livein_empty() const { return LiveIns.empty(); }
293 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
294 liveout_iterator liveout_end() const { return LiveOuts.end(); }
295 bool liveout_empty() const { return LiveOuts.empty(); }
297 bool isLiveIn(unsigned Reg) const;
298 bool isLiveOut(unsigned Reg) const;
300 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
301 /// corresponding live-in physical register.
302 unsigned getLiveInPhysReg(unsigned VReg) const;
304 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
305 /// corresponding live-in physical register.
306 unsigned getLiveInVirtReg(unsigned PReg) const;
308 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
309 /// into the given entry block.
310 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
311 const TargetRegisterInfo &TRI,
312 const TargetInstrInfo &TII);
315 void HandleVRegListReallocation();
318 /// defusechain_iterator - This class provides iterator support for machine
319 /// operands in the function that use or define a specific register. If
320 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
321 /// returns defs. If neither are true then you are silly and it always
322 /// returns end(). If SkipDebug is true it skips uses marked Debug
323 /// when incrementing.
324 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
325 class defusechain_iterator
326 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
328 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
329 // If the first node isn't one we're interested in, advance to one that
330 // we are interested in.
332 if ((!ReturnUses && op->isUse()) ||
333 (!ReturnDefs && op->isDef()) ||
334 (SkipDebug && op->isDebug()))
338 friend class MachineRegisterInfo;
340 typedef std::iterator<std::forward_iterator_tag,
341 MachineInstr, ptrdiff_t>::reference reference;
342 typedef std::iterator<std::forward_iterator_tag,
343 MachineInstr, ptrdiff_t>::pointer pointer;
345 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
346 defusechain_iterator() : Op(0) {}
348 bool operator==(const defusechain_iterator &x) const {
351 bool operator!=(const defusechain_iterator &x) const {
352 return !operator==(x);
355 /// atEnd - return true if this iterator is equal to reg_end() on the value.
356 bool atEnd() const { return Op == 0; }
358 // Iterator traversal: forward iteration only
359 defusechain_iterator &operator++() { // Preincrement
360 assert(Op && "Cannot increment end iterator!");
361 Op = Op->getNextOperandForReg();
363 // If this is an operand we don't care about, skip it.
364 while (Op && ((!ReturnUses && Op->isUse()) ||
365 (!ReturnDefs && Op->isDef()) ||
366 (SkipDebug && Op->isDebug())))
367 Op = Op->getNextOperandForReg();
371 defusechain_iterator operator++(int) { // Postincrement
372 defusechain_iterator tmp = *this; ++*this; return tmp;
375 /// skipInstruction - move forward until reaching a different instruction.
376 /// Return the skipped instruction that is no longer pointed to, or NULL if
377 /// already pointing to end().
378 MachineInstr *skipInstruction() {
380 MachineInstr *MI = Op->getParent();
382 while (Op && Op->getParent() == MI);
386 MachineOperand &getOperand() const {
387 assert(Op && "Cannot dereference end iterator!");
391 /// getOperandNo - Return the operand # of this MachineOperand in its
393 unsigned getOperandNo() const {
394 assert(Op && "Cannot dereference end iterator!");
395 return Op - &Op->getParent()->getOperand(0);
398 // Retrieve a reference to the current operand.
399 MachineInstr &operator*() const {
400 assert(Op && "Cannot dereference end iterator!");
401 return *Op->getParent();
404 MachineInstr *operator->() const {
405 assert(Op && "Cannot dereference end iterator!");
406 return Op->getParent();
412 } // End llvm namespace