1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
23 /// MachineRegisterInfo - Keep track of information for virtual and physical
24 /// registers, including vreg register classes, use/def chains for registers,
26 class MachineRegisterInfo {
27 /// VRegInfo - Information we keep for each virtual register. The entries in
28 /// this vector are actually converted to vreg numbers by adding the
29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
31 /// Each element in this list contains the register class of the vreg and the
32 /// start of the use/def list for the register.
33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
36 /// virtual registers. For each target register class, it keeps a list of
37 /// virtual registers belonging to the class.
38 std::vector<std::vector<unsigned> > RegClass2VRegMap;
40 /// RegAllocHints - This vector records register allocation hints for virtual
41 /// registers. For each virtual register, it keeps a register and hint type
42 /// pair making up the allocation hint. Hint type is target specific except
43 /// for the value 0 which means the second value of the pair is the preferred
44 /// register for allocation. For example, if the hint is <0, 1024>, it means
45 /// the allocator should prefer the physical register allocated to the virtual
46 /// register of the hint.
47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
50 /// physical registers.
51 MachineOperand **PhysRegUseDefLists;
53 /// UsedPhysRegs - This is a bit vector that is computed and set by the
54 /// register allocator, and must be kept up to date by passes that run after
55 /// register allocation (though most don't modify this). This is used
56 /// so that the code generator knows which callee save registers to save and
57 /// for other target specific uses.
58 BitVector UsedPhysRegs;
60 /// LiveIns/LiveOuts - Keep track of the physical registers that are
61 /// livein/liveout of the function. Live in values are typically arguments in
62 /// registers, live out values are typically return values in registers.
63 /// LiveIn values are allowed to have virtual registers associated with them,
64 /// stored in the second element.
65 std::vector<std::pair<unsigned, unsigned> > LiveIns;
66 std::vector<unsigned> LiveOuts;
68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
72 ~MachineRegisterInfo();
74 //===--------------------------------------------------------------------===//
76 //===--------------------------------------------------------------------===//
78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
79 /// and uses of a register within the MachineFunction that corresponds to this
80 /// MachineRegisterInfo object.
81 template<bool Uses, bool Defs>
82 class defusechain_iterator;
84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
86 typedef defusechain_iterator<true,true> reg_iterator;
87 reg_iterator reg_begin(unsigned RegNo) const {
88 return reg_iterator(getRegUseDefListHead(RegNo));
90 static reg_iterator reg_end() { return reg_iterator(0); }
92 /// reg_empty - Return true if there are no instructions using or defining the
93 /// specified register (it may be live-in).
94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
96 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
97 typedef defusechain_iterator<false,true> def_iterator;
98 def_iterator def_begin(unsigned RegNo) const {
99 return def_iterator(getRegUseDefListHead(RegNo));
101 static def_iterator def_end() { return def_iterator(0); }
103 /// def_empty - Return true if there are no instructions defining the
104 /// specified register (it may be live-in).
105 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
107 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
108 typedef defusechain_iterator<true,false> use_iterator;
109 use_iterator use_begin(unsigned RegNo) const {
110 return use_iterator(getRegUseDefListHead(RegNo));
112 static use_iterator use_end() { return use_iterator(0); }
114 /// use_empty - Return true if there are no instructions using the specified
116 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
119 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
120 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
121 /// except that it also changes any definitions of the register as well.
122 void replaceRegWith(unsigned FromReg, unsigned ToReg);
124 /// getRegUseDefListHead - Return the head pointer for the register use/def
125 /// list for the specified virtual or physical register.
126 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
127 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
128 return PhysRegUseDefLists[RegNo];
129 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
130 return VRegInfo[RegNo].second;
133 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
134 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
135 return PhysRegUseDefLists[RegNo];
136 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
137 return VRegInfo[RegNo].second;
140 /// getVRegDef - Return the machine instr that defines the specified virtual
141 /// register or null if none is found. This assumes that the code is in SSA
142 /// form, so there should only be one definition.
143 MachineInstr *getVRegDef(unsigned Reg) const;
146 void dumpUses(unsigned RegNo) const;
149 //===--------------------------------------------------------------------===//
150 // Virtual Register Info
151 //===--------------------------------------------------------------------===//
153 /// getRegClass - Return the register class of the specified virtual register.
155 const TargetRegisterClass *getRegClass(unsigned Reg) const {
156 Reg -= TargetRegisterInfo::FirstVirtualRegister;
157 assert(Reg < VRegInfo.size() && "Invalid vreg!");
158 return VRegInfo[Reg].first;
161 /// setRegClass - Set the register class of the specified virtual register.
163 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
165 /// createVirtualRegister - Create and return a new virtual register in the
166 /// function with the specified register class.
168 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
170 /// getLastVirtReg - Return the highest currently assigned virtual register.
172 unsigned getLastVirtReg() const {
173 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
176 /// getRegClassVirtRegs - Return the list of virtual registers of the given
177 /// target register class.
178 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
179 return RegClass2VRegMap[RC->getID()];
182 /// setRegAllocationHint - Specify a register allocation hint for the
183 /// specified virtual register.
184 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
185 Reg -= TargetRegisterInfo::FirstVirtualRegister;
186 assert(Reg < VRegInfo.size() && "Invalid vreg!");
187 RegAllocHints[Reg].first = Type;
188 RegAllocHints[Reg].second = PrefReg;
191 /// getRegAllocationHint - Return the register allocation hint for the
192 /// specified virtual register.
193 std::pair<unsigned, unsigned>
194 getRegAllocationHint(unsigned Reg) const {
195 Reg -= TargetRegisterInfo::FirstVirtualRegister;
196 assert(Reg < VRegInfo.size() && "Invalid vreg!");
197 return RegAllocHints[Reg];
200 //===--------------------------------------------------------------------===//
201 // Physical Register Use Info
202 //===--------------------------------------------------------------------===//
204 /// isPhysRegUsed - Return true if the specified register is used in this
205 /// function. This only works after register allocation.
206 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
208 /// setPhysRegUsed - Mark the specified register used in this function.
209 /// This should only be called during and after register allocation.
210 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
212 /// setPhysRegUnused - Mark the specified register unused in this function.
213 /// This should only be called during and after register allocation.
214 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
217 //===--------------------------------------------------------------------===//
218 // LiveIn/LiveOut Management
219 //===--------------------------------------------------------------------===//
221 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
222 /// is an error to add the same register to the same set more than once.
223 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
224 LiveIns.push_back(std::make_pair(Reg, vreg));
226 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
228 // Iteration support for live in/out sets. These sets are kept in sorted
229 // order by their register number.
230 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
232 typedef std::vector<unsigned>::const_iterator liveout_iterator;
233 livein_iterator livein_begin() const { return LiveIns.begin(); }
234 livein_iterator livein_end() const { return LiveIns.end(); }
235 bool livein_empty() const { return LiveIns.empty(); }
236 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
237 liveout_iterator liveout_end() const { return LiveOuts.end(); }
238 bool liveout_empty() const { return LiveOuts.empty(); }
240 bool isLiveIn(unsigned Reg) const {
241 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
242 if (I->first == Reg || I->second == Reg)
246 bool isLiveOut(unsigned Reg) const {
247 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
254 void HandleVRegListReallocation();
257 /// defusechain_iterator - This class provides iterator support for machine
258 /// operands in the function that use or define a specific register. If
259 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
260 /// returns defs. If neither are true then you are silly and it always
262 template<bool ReturnUses, bool ReturnDefs>
263 class defusechain_iterator
264 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
266 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
267 // If the first node isn't one we're interested in, advance to one that
268 // we are interested in.
270 if ((!ReturnUses && op->isUse()) ||
271 (!ReturnDefs && op->isDef()))
275 friend class MachineRegisterInfo;
277 typedef std::iterator<std::forward_iterator_tag,
278 MachineInstr, ptrdiff_t>::reference reference;
279 typedef std::iterator<std::forward_iterator_tag,
280 MachineInstr, ptrdiff_t>::pointer pointer;
282 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
283 defusechain_iterator() : Op(0) {}
285 bool operator==(const defusechain_iterator &x) const {
288 bool operator!=(const defusechain_iterator &x) const {
289 return !operator==(x);
292 /// atEnd - return true if this iterator is equal to reg_end() on the value.
293 bool atEnd() const { return Op == 0; }
295 // Iterator traversal: forward iteration only
296 defusechain_iterator &operator++() { // Preincrement
297 assert(Op && "Cannot increment end iterator!");
298 Op = Op->getNextOperandForReg();
300 // If this is an operand we don't care about, skip it.
301 while (Op && ((!ReturnUses && Op->isUse()) ||
302 (!ReturnDefs && Op->isDef())))
303 Op = Op->getNextOperandForReg();
307 defusechain_iterator operator++(int) { // Postincrement
308 defusechain_iterator tmp = *this; ++*this; return tmp;
311 MachineOperand &getOperand() const {
312 assert(Op && "Cannot dereference end iterator!");
316 /// getOperandNo - Return the operand # of this MachineOperand in its
318 unsigned getOperandNo() const {
319 assert(Op && "Cannot dereference end iterator!");
320 return Op - &Op->getParent()->getOperand(0);
323 // Retrieve a reference to the current operand.
324 MachineInstr &operator*() const {
325 assert(Op && "Cannot dereference end iterator!");
326 return *Op->getParent();
329 MachineInstr *operator->() const {
330 assert(Op && "Cannot dereference end iterator!");
331 return Op->getParent();
337 } // End llvm namespace