1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
27 /// MachineRegisterInfo - Keep track of information for virtual and physical
28 /// registers, including vreg register classes, use/def chains for registers,
30 class MachineRegisterInfo {
33 virtual void anchor();
35 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
37 virtual ~Delegate() {}
41 const TargetMachine &TM;
42 Delegate *TheDelegate;
44 /// IsSSA - True when the machine function is in SSA form and virtual
45 /// registers have a single def.
48 /// TracksLiveness - True while register liveness is being tracked accurately.
49 /// Basic block live-in lists, kill flags, and implicit defs may not be
50 /// accurate when after this flag is cleared.
53 /// VRegInfo - Information we keep for each virtual register.
55 /// Each element in this list contains the register class of the vreg and the
56 /// start of the use/def list for the register.
57 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
58 VirtReg2IndexFunctor> VRegInfo;
60 /// RegAllocHints - This vector records register allocation hints for virtual
61 /// registers. For each virtual register, it keeps a register and hint type
62 /// pair making up the allocation hint. Hint type is target specific except
63 /// for the value 0 which means the second value of the pair is the preferred
64 /// register for allocation. For example, if the hint is <0, 1024>, it means
65 /// the allocator should prefer the physical register allocated to the virtual
66 /// register of the hint.
67 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
69 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
70 /// physical registers.
71 MachineOperand **PhysRegUseDefLists;
73 /// getRegUseDefListHead - Return the head pointer for the register use/def
74 /// list for the specified virtual or physical register.
75 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
76 if (TargetRegisterInfo::isVirtualRegister(RegNo))
77 return VRegInfo[RegNo].second;
78 return PhysRegUseDefLists[RegNo];
81 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
82 if (TargetRegisterInfo::isVirtualRegister(RegNo))
83 return VRegInfo[RegNo].second;
84 return PhysRegUseDefLists[RegNo];
87 /// Get the next element in the use-def chain.
88 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
89 assert(MO && MO->isReg() && "This is not a register operand!");
90 return MO->Contents.Reg.Next;
93 /// UsedRegUnits - This is a bit vector that is computed and set by the
94 /// register allocator, and must be kept up to date by passes that run after
95 /// register allocation (though most don't modify this). This is used
96 /// so that the code generator knows which callee save registers to save and
97 /// for other target specific uses.
98 /// This vector has bits set for register units that are modified in the
99 /// current function. It doesn't include registers clobbered by function
100 /// calls with register mask operands.
101 BitVector UsedRegUnits;
103 /// UsedPhysRegMask - Additional used physregs including aliases.
104 /// This bit vector represents all the registers clobbered by function calls.
105 /// It can model things that UsedRegUnits can't, such as function calls that
106 /// clobber ymm7 but preserve the low half in xmm7.
107 BitVector UsedPhysRegMask;
109 /// ReservedRegs - This is a bit vector of reserved registers. The target
110 /// may change its mind about which registers should be reserved. This
111 /// vector is the frozen set of reserved registers when register allocation
113 BitVector ReservedRegs;
115 /// Keep track of the physical registers that are live in to the function.
116 /// Live in values are typically arguments in registers. LiveIn values are
117 /// allowed to have virtual registers associated with them, stored in the
119 std::vector<std::pair<unsigned, unsigned> > LiveIns;
121 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
122 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
124 explicit MachineRegisterInfo(const TargetMachine &TM);
125 ~MachineRegisterInfo();
127 const TargetRegisterInfo *getTargetRegisterInfo() const {
128 return TM.getRegisterInfo();
131 void resetDelegate(Delegate *delegate) {
132 // Ensure another delegate does not take over unless the current
133 // delegate first unattaches itself. If we ever need to multicast
134 // notifications, we will need to change to using a list.
135 assert(TheDelegate == delegate &&
136 "Only the current delegate can perform reset!");
140 void setDelegate(Delegate *delegate) {
141 assert(delegate && !TheDelegate &&
142 "Attempted to set delegate to null, or to change it without "
143 "first resetting it!");
145 TheDelegate = delegate;
148 //===--------------------------------------------------------------------===//
150 //===--------------------------------------------------------------------===//
152 // isSSA - Returns true when the machine function is in SSA form. Early
153 // passes require the machine function to be in SSA form where every virtual
154 // register has a single defining instruction.
156 // The TwoAddressInstructionPass and PHIElimination passes take the machine
157 // function out of SSA form when they introduce multiple defs per virtual
159 bool isSSA() const { return IsSSA; }
161 // leaveSSA - Indicates that the machine function is no longer in SSA form.
162 void leaveSSA() { IsSSA = false; }
164 /// tracksLiveness - Returns true when tracking register liveness accurately.
166 /// While this flag is true, register liveness information in basic block
167 /// live-in lists and machine instruction operands is accurate. This means it
168 /// can be used to change the code in ways that affect the values in
169 /// registers, for example by the register scavenger.
171 /// When this flag is false, liveness is no longer reliable.
172 bool tracksLiveness() const { return TracksLiveness; }
174 /// invalidateLiveness - Indicates that register liveness is no longer being
175 /// tracked accurately.
177 /// This should be called by late passes that invalidate the liveness
179 void invalidateLiveness() { TracksLiveness = false; }
181 //===--------------------------------------------------------------------===//
183 //===--------------------------------------------------------------------===//
185 // Strictly for use by MachineInstr.cpp.
186 void addRegOperandToUseList(MachineOperand *MO);
188 // Strictly for use by MachineInstr.cpp.
189 void removeRegOperandFromUseList(MachineOperand *MO);
191 // Strictly for use by MachineInstr.cpp.
192 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
194 /// Verify the sanity of the use list for Reg.
195 void verifyUseList(unsigned Reg) const;
197 /// Verify the use list of all registers.
198 void verifyUseLists() const;
200 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
201 /// and uses of a register within the MachineFunction that corresponds to this
202 /// MachineRegisterInfo object.
203 template<bool Uses, bool Defs, bool SkipDebug,
204 bool ByOperand, bool ByInstr, bool ByBundle>
205 class defusechain_iterator;
206 template<bool Uses, bool Defs, bool SkipDebug,
207 bool ByOperand, bool ByInstr, bool ByBundle>
208 class defusechain_instr_iterator;
210 // Make it a friend so it can access getNextOperandForReg().
211 template<bool, bool, bool, bool, bool, bool>
212 friend class defusechain_iterator;
213 template<bool, bool, bool, bool, bool, bool>
214 friend class defusechain_instr_iterator;
218 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
220 typedef defusechain_iterator<true,true,false,true,false,false>
222 reg_iterator reg_begin(unsigned RegNo) const {
223 return reg_iterator(getRegUseDefListHead(RegNo));
225 static reg_iterator reg_end() { return reg_iterator(0); }
227 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
228 /// of the specified register, stepping by MachineInstr.
229 typedef defusechain_instr_iterator<true,true,false,false,true,false>
231 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
232 return reg_instr_iterator(getRegUseDefListHead(RegNo));
234 static reg_instr_iterator reg_instr_end() { return reg_instr_iterator(0); }
236 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
237 /// of the specified register, stepping by bundle.
238 typedef defusechain_instr_iterator<true,true,false,false,false,true>
240 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
241 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
243 static reg_bundle_iterator reg_bundle_end() { return reg_bundle_iterator(0); }
245 /// reg_empty - Return true if there are no instructions using or defining the
246 /// specified register (it may be live-in).
247 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
249 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
250 /// of the specified register, skipping those marked as Debug.
251 typedef defusechain_iterator<true,true,true,true,false,false>
253 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
254 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
256 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
258 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
259 /// all defs and uses of the specified register, stepping by MachineInstr,
260 /// skipping those marked as Debug.
261 typedef defusechain_instr_iterator<true,true,true,false,true,false>
262 reg_instr_nodbg_iterator;
263 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
264 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
266 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
267 return reg_instr_nodbg_iterator(0);
270 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
271 /// all defs and uses of the specified register, stepping by bundle,
272 /// skipping those marked as Debug.
273 typedef defusechain_instr_iterator<true,true,true,false,false,true>
274 reg_bundle_nodbg_iterator;
275 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
276 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
278 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
279 return reg_bundle_nodbg_iterator(0);
282 /// reg_nodbg_empty - Return true if the only instructions using or defining
283 /// Reg are Debug instructions.
284 bool reg_nodbg_empty(unsigned RegNo) const {
285 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
288 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
289 typedef defusechain_iterator<false,true,false,true,false,false>
291 def_iterator def_begin(unsigned RegNo) const {
292 return def_iterator(getRegUseDefListHead(RegNo));
294 static def_iterator def_end() { return def_iterator(0); }
296 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
297 /// specified register, stepping by MachineInst.
298 typedef defusechain_instr_iterator<false,true,false,false,true,false>
300 def_instr_iterator def_instr_begin(unsigned RegNo) const {
301 return def_instr_iterator(getRegUseDefListHead(RegNo));
303 static def_instr_iterator def_instr_end() { return def_instr_iterator(0); }
305 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
306 /// specified register, stepping by bundle.
307 typedef defusechain_instr_iterator<false,true,false,false,false,true>
309 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
310 return def_bundle_iterator(getRegUseDefListHead(RegNo));
312 static def_bundle_iterator def_bundle_end() { return def_bundle_iterator(0); }
314 /// def_empty - Return true if there are no instructions defining the
315 /// specified register (it may be live-in).
316 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
318 /// hasOneDef - Return true if there is exactly one instruction defining the
319 /// specified register.
320 bool hasOneDef(unsigned RegNo) const {
321 def_iterator DI = def_begin(RegNo);
324 return ++DI == def_end();
327 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
328 typedef defusechain_iterator<true,false,false,true,false,false>
330 use_iterator use_begin(unsigned RegNo) const {
331 return use_iterator(getRegUseDefListHead(RegNo));
333 static use_iterator use_end() { return use_iterator(0); }
335 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
336 /// specified register, stepping by MachineInstr.
337 typedef defusechain_instr_iterator<true,false,false,false,true,false>
339 use_instr_iterator use_instr_begin(unsigned RegNo) const {
340 return use_instr_iterator(getRegUseDefListHead(RegNo));
342 static use_instr_iterator use_instr_end() { return use_instr_iterator(0); }
344 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
345 /// specified register, stepping by bundle.
346 typedef defusechain_instr_iterator<true,false,false,false,false,true>
348 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
349 return use_bundle_iterator(getRegUseDefListHead(RegNo));
351 static use_bundle_iterator use_bundle_end() { return use_bundle_iterator(0); }
353 /// use_empty - Return true if there are no instructions using the specified
355 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
357 /// hasOneUse - Return true if there is exactly one instruction using the
358 /// specified register.
359 bool hasOneUse(unsigned RegNo) const {
360 use_iterator UI = use_begin(RegNo);
363 return ++UI == use_end();
366 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
367 /// specified register, skipping those marked as Debug.
368 typedef defusechain_iterator<true,false,true,true,false,false>
370 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
371 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
373 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
375 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
376 /// all uses of the specified register, stepping by MachineInstr, skipping
377 /// those marked as Debug.
378 typedef defusechain_instr_iterator<true,false,true,false,true,false>
379 use_instr_nodbg_iterator;
380 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
381 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
383 static use_instr_nodbg_iterator use_instr_nodbg_end() {
384 return use_instr_nodbg_iterator(0);
387 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
388 /// all uses of the specified register, stepping by bundle, skipping
389 /// those marked as Debug.
390 typedef defusechain_instr_iterator<true,false,true,false,false,true>
391 use_bundle_nodbg_iterator;
392 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
393 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
395 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
396 return use_bundle_nodbg_iterator(0);
399 /// use_nodbg_empty - Return true if there are no non-Debug instructions
400 /// using the specified register.
401 bool use_nodbg_empty(unsigned RegNo) const {
402 return use_nodbg_begin(RegNo) == use_nodbg_end();
405 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
406 /// instruction using the specified register.
407 bool hasOneNonDBGUse(unsigned RegNo) const;
409 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
410 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
411 /// except that it also changes any definitions of the register as well.
413 /// Note that it is usually necessary to first constrain ToReg's register
414 /// class to match the FromReg constraints using:
416 /// constrainRegClass(ToReg, getRegClass(FromReg))
418 /// That function will return NULL if the virtual registers have incompatible
420 void replaceRegWith(unsigned FromReg, unsigned ToReg);
422 /// getVRegDef - Return the machine instr that defines the specified virtual
423 /// register or null if none is found. This assumes that the code is in SSA
424 /// form, so there should only be one definition.
425 MachineInstr *getVRegDef(unsigned Reg) const;
427 /// getUniqueVRegDef - Return the unique machine instr that defines the
428 /// specified virtual register or null if none is found. If there are
429 /// multiple definitions or no definition, return null.
430 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
432 /// clearKillFlags - Iterate over all the uses of the given register and
433 /// clear the kill flag from the MachineOperand. This function is used by
434 /// optimization passes which extend register lifetimes and need only
435 /// preserve conservative kill flag information.
436 void clearKillFlags(unsigned Reg) const;
439 void dumpUses(unsigned RegNo) const;
442 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
443 /// throughout the function. It is safe to move instructions that read such
445 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
447 /// Get an iterator over the pressure sets affected by the given physical or
448 /// virtual register. If RegUnit is physical, it must be a register unit (from
449 /// MCRegUnitIterator).
450 PSetIterator getPressureSets(unsigned RegUnit) const;
452 //===--------------------------------------------------------------------===//
453 // Virtual Register Info
454 //===--------------------------------------------------------------------===//
456 /// getRegClass - Return the register class of the specified virtual register.
458 const TargetRegisterClass *getRegClass(unsigned Reg) const {
459 return VRegInfo[Reg].first;
462 /// setRegClass - Set the register class of the specified virtual register.
464 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
466 /// constrainRegClass - Constrain the register class of the specified virtual
467 /// register to be a common subclass of RC and the current register class,
468 /// but only if the new class has at least MinNumRegs registers. Return the
469 /// new register class, or NULL if no such class exists.
470 /// This should only be used when the constraint is known to be trivial, like
471 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
473 const TargetRegisterClass *constrainRegClass(unsigned Reg,
474 const TargetRegisterClass *RC,
475 unsigned MinNumRegs = 0);
477 /// recomputeRegClass - Try to find a legal super-class of Reg's register
478 /// class that still satisfies the constraints from the instructions using
479 /// Reg. Returns true if Reg was upgraded.
481 /// This method can be used after constraints have been removed from a
482 /// virtual register, for example after removing instructions or splitting
485 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
487 /// createVirtualRegister - Create and return a new virtual register in the
488 /// function with the specified register class.
490 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
492 /// getNumVirtRegs - Return the number of virtual registers created.
494 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
496 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
497 void clearVirtRegs();
499 /// setRegAllocationHint - Specify a register allocation hint for the
500 /// specified virtual register.
501 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
502 RegAllocHints[Reg].first = Type;
503 RegAllocHints[Reg].second = PrefReg;
506 /// getRegAllocationHint - Return the register allocation hint for the
507 /// specified virtual register.
508 std::pair<unsigned, unsigned>
509 getRegAllocationHint(unsigned Reg) const {
510 return RegAllocHints[Reg];
513 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
514 /// standard simple hint (Type == 0) is not set.
515 unsigned getSimpleHint(unsigned Reg) const {
516 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
517 return Hint.first ? 0 : Hint.second;
520 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
521 /// specified register as undefined which causes the DBG_VALUE to be
522 /// deleted during LiveDebugVariables analysis.
523 void markUsesInDebugValueAsUndef(unsigned Reg) const;
525 //===--------------------------------------------------------------------===//
526 // Physical Register Use Info
527 //===--------------------------------------------------------------------===//
529 /// isPhysRegUsed - Return true if the specified register is used in this
530 /// function. Also check for clobbered aliases and registers clobbered by
531 /// function calls with register mask operands.
533 /// This only works after register allocation. It is primarily used by
534 /// PrologEpilogInserter to determine which callee-saved registers need
536 bool isPhysRegUsed(unsigned Reg) const {
537 if (UsedPhysRegMask.test(Reg))
539 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
540 Units.isValid(); ++Units)
541 if (UsedRegUnits.test(*Units))
546 /// Mark the specified register unit as used in this function.
547 /// This should only be called during and after register allocation.
548 void setRegUnitUsed(unsigned RegUnit) {
549 UsedRegUnits.set(RegUnit);
552 /// setPhysRegUsed - Mark the specified register used in this function.
553 /// This should only be called during and after register allocation.
554 void setPhysRegUsed(unsigned Reg) {
555 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
556 Units.isValid(); ++Units)
557 UsedRegUnits.set(*Units);
560 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
561 /// This corresponds to the bit mask attached to register mask operands.
562 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
563 UsedPhysRegMask.setBitsNotInMask(RegMask);
566 /// setPhysRegUnused - Mark the specified register unused in this function.
567 /// This should only be called during and after register allocation.
568 void setPhysRegUnused(unsigned Reg) {
569 UsedPhysRegMask.reset(Reg);
570 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
571 Units.isValid(); ++Units)
572 UsedRegUnits.reset(*Units);
576 //===--------------------------------------------------------------------===//
577 // Reserved Register Info
578 //===--------------------------------------------------------------------===//
580 // The set of reserved registers must be invariant during register
581 // allocation. For example, the target cannot suddenly decide it needs a
582 // frame pointer when the register allocator has already used the frame
583 // pointer register for something else.
585 // These methods can be used by target hooks like hasFP() to avoid changing
586 // the reserved register set during register allocation.
588 /// freezeReservedRegs - Called by the register allocator to freeze the set
589 /// of reserved registers before allocation begins.
590 void freezeReservedRegs(const MachineFunction&);
592 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
593 /// to ensure the set of reserved registers stays constant.
594 bool reservedRegsFrozen() const {
595 return !ReservedRegs.empty();
598 /// canReserveReg - Returns true if PhysReg can be used as a reserved
599 /// register. Any register can be reserved before freezeReservedRegs() is
601 bool canReserveReg(unsigned PhysReg) const {
602 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
605 /// getReservedRegs - Returns a reference to the frozen set of reserved
606 /// registers. This method should always be preferred to calling
607 /// TRI::getReservedRegs() when possible.
608 const BitVector &getReservedRegs() const {
609 assert(reservedRegsFrozen() &&
610 "Reserved registers haven't been frozen yet. "
611 "Use TRI::getReservedRegs().");
615 /// isReserved - Returns true when PhysReg is a reserved register.
617 /// Reserved registers may belong to an allocatable register class, but the
618 /// target has explicitly requested that they are not used.
620 bool isReserved(unsigned PhysReg) const {
621 return getReservedRegs().test(PhysReg);
624 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
625 /// register class and it hasn't been reserved.
627 /// Allocatable registers may show up in the allocation order of some virtual
628 /// register, so a register allocator needs to track its liveness and
630 bool isAllocatable(unsigned PhysReg) const {
631 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
632 !isReserved(PhysReg);
635 //===--------------------------------------------------------------------===//
637 //===--------------------------------------------------------------------===//
639 /// addLiveIn - Add the specified register as a live-in. Note that it
640 /// is an error to add the same register to the same set more than once.
641 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
642 LiveIns.push_back(std::make_pair(Reg, vreg));
645 // Iteration support for the live-ins set. It's kept in sorted order
646 // by register number.
647 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
649 livein_iterator livein_begin() const { return LiveIns.begin(); }
650 livein_iterator livein_end() const { return LiveIns.end(); }
651 bool livein_empty() const { return LiveIns.empty(); }
653 bool isLiveIn(unsigned Reg) const;
655 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
656 /// corresponding live-in physical register.
657 unsigned getLiveInPhysReg(unsigned VReg) const;
659 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
660 /// corresponding live-in physical register.
661 unsigned getLiveInVirtReg(unsigned PReg) const;
663 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
664 /// into the given entry block.
665 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
666 const TargetRegisterInfo &TRI,
667 const TargetInstrInfo &TII);
669 /// defusechain_iterator - This class provides iterator support for machine
670 /// operands in the function that use or define a specific register. If
671 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
672 /// returns defs. If neither are true then you are silly and it always
673 /// returns end(). If SkipDebug is true it skips uses marked Debug
674 /// when incrementing.
675 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
676 bool ByOperand, bool ByInstr, bool ByBundle>
677 class defusechain_iterator
678 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
680 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
681 // If the first node isn't one we're interested in, advance to one that
682 // we are interested in.
684 if ((!ReturnUses && op->isUse()) ||
685 (!ReturnDefs && op->isDef()) ||
686 (SkipDebug && op->isDebug()))
690 friend class MachineRegisterInfo;
693 assert(Op && "Cannot increment end iterator!");
694 Op = getNextOperandForReg(Op);
696 // All defs come before the uses, so stop def_iterator early.
702 assert(!Op->isDebug() && "Can't have debug defs");
705 // If this is an operand we don't care about, skip it.
706 while (Op && ((!ReturnDefs && Op->isDef()) ||
707 (SkipDebug && Op->isDebug())))
708 Op = getNextOperandForReg(Op);
712 typedef std::iterator<std::forward_iterator_tag,
713 MachineInstr, ptrdiff_t>::reference reference;
714 typedef std::iterator<std::forward_iterator_tag,
715 MachineInstr, ptrdiff_t>::pointer pointer;
717 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
718 defusechain_iterator() : Op(0) {}
720 bool operator==(const defusechain_iterator &x) const {
723 bool operator!=(const defusechain_iterator &x) const {
724 return !operator==(x);
727 /// atEnd - return true if this iterator is equal to reg_end() on the value.
728 bool atEnd() const { return Op == 0; }
730 // Iterator traversal: forward iteration only
731 defusechain_iterator &operator++() { // Preincrement
732 assert(Op && "Cannot increment end iterator!");
736 MachineInstr *P = Op->getParent();
739 } while (Op && Op->getParent() == P);
740 } else if (ByBundle) {
741 MachineInstr *P = getBundleStart(Op->getParent());
744 } while (Op && getBundleStart(Op->getParent()) == P);
749 defusechain_iterator operator++(int) { // Postincrement
750 defusechain_iterator tmp = *this; ++*this; return tmp;
753 /// getOperandNo - Return the operand # of this MachineOperand in its
755 unsigned getOperandNo() const {
756 assert(Op && "Cannot dereference end iterator!");
757 return Op - &Op->getParent()->getOperand(0);
760 // Retrieve a reference to the current operand.
761 MachineOperand &operator*() const {
762 assert(Op && "Cannot dereference end iterator!");
766 MachineOperand *operator->() const {
767 assert(Op && "Cannot dereference end iterator!");
772 /// defusechain_iterator - This class provides iterator support for machine
773 /// operands in the function that use or define a specific register. If
774 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
775 /// returns defs. If neither are true then you are silly and it always
776 /// returns end(). If SkipDebug is true it skips uses marked Debug
777 /// when incrementing.
778 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
779 bool ByOperand, bool ByInstr, bool ByBundle>
780 class defusechain_instr_iterator
781 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
783 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
784 // If the first node isn't one we're interested in, advance to one that
785 // we are interested in.
787 if ((!ReturnUses && op->isUse()) ||
788 (!ReturnDefs && op->isDef()) ||
789 (SkipDebug && op->isDebug()))
793 friend class MachineRegisterInfo;
796 assert(Op && "Cannot increment end iterator!");
797 Op = getNextOperandForReg(Op);
799 // All defs come before the uses, so stop def_iterator early.
805 assert(!Op->isDebug() && "Can't have debug defs");
808 // If this is an operand we don't care about, skip it.
809 while (Op && ((!ReturnDefs && Op->isDef()) ||
810 (SkipDebug && Op->isDebug())))
811 Op = getNextOperandForReg(Op);
815 typedef std::iterator<std::forward_iterator_tag,
816 MachineInstr, ptrdiff_t>::reference reference;
817 typedef std::iterator<std::forward_iterator_tag,
818 MachineInstr, ptrdiff_t>::pointer pointer;
820 defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
821 defusechain_instr_iterator() : Op(0) {}
823 bool operator==(const defusechain_instr_iterator &x) const {
826 bool operator!=(const defusechain_instr_iterator &x) const {
827 return !operator==(x);
830 /// atEnd - return true if this iterator is equal to reg_end() on the value.
831 bool atEnd() const { return Op == 0; }
833 // Iterator traversal: forward iteration only
834 defusechain_instr_iterator &operator++() { // Preincrement
835 assert(Op && "Cannot increment end iterator!");
839 MachineInstr *P = Op->getParent();
842 } while (Op && Op->getParent() == P);
843 } else if (ByBundle) {
844 MachineInstr *P = getBundleStart(Op->getParent());
847 } while (Op && getBundleStart(Op->getParent()) == P);
852 defusechain_instr_iterator operator++(int) { // Postincrement
853 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
856 // Retrieve a reference to the current operand.
857 MachineInstr &operator*() const {
858 assert(Op && "Cannot dereference end iterator!");
859 if (ByBundle) return *(getBundleStart(Op->getParent()));
860 return *Op->getParent();
863 MachineInstr *operator->() const {
864 assert(Op && "Cannot dereference end iterator!");
865 if (ByBundle) return getBundleStart(Op->getParent());
866 return Op->getParent();
871 /// Iterate over the pressure sets affected by the given physical or virtual
872 /// register. If Reg is physical, it must be a register unit (from
873 /// MCRegUnitIterator).
878 PSetIterator(): PSet(0), Weight(0) {}
879 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
880 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
881 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
882 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
883 PSet = TRI->getRegClassPressureSets(RC);
884 Weight = TRI->getRegClassWeight(RC).RegWeight;
887 PSet = TRI->getRegUnitPressureSets(RegUnit);
888 Weight = TRI->getRegUnitWeight(RegUnit);
893 bool isValid() const { return PSet; }
895 unsigned getWeight() const { return Weight; }
897 unsigned operator*() const { return *PSet; }
900 assert(isValid() && "Invalid PSetIterator.");
907 inline PSetIterator MachineRegisterInfo::
908 getPressureSets(unsigned RegUnit) const {
909 return PSetIterator(RegUnit, this);
912 } // End llvm namespace