1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/CodeGen/MachineInstrBundle.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
27 /// MachineRegisterInfo - Keep track of information for virtual and physical
28 /// registers, including vreg register classes, use/def chains for registers,
30 class MachineRegisterInfo {
33 virtual void anchor();
35 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
37 virtual ~Delegate() {}
41 const TargetMachine &TM;
42 Delegate *TheDelegate;
44 /// IsSSA - True when the machine function is in SSA form and virtual
45 /// registers have a single def.
48 /// TracksLiveness - True while register liveness is being tracked accurately.
49 /// Basic block live-in lists, kill flags, and implicit defs may not be
50 /// accurate when after this flag is cleared.
53 /// VRegInfo - Information we keep for each virtual register.
55 /// Each element in this list contains the register class of the vreg and the
56 /// start of the use/def list for the register.
57 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
58 VirtReg2IndexFunctor> VRegInfo;
60 /// RegAllocHints - This vector records register allocation hints for virtual
61 /// registers. For each virtual register, it keeps a register and hint type
62 /// pair making up the allocation hint. Hint type is target specific except
63 /// for the value 0 which means the second value of the pair is the preferred
64 /// register for allocation. For example, if the hint is <0, 1024>, it means
65 /// the allocator should prefer the physical register allocated to the virtual
66 /// register of the hint.
67 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
69 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
70 /// physical registers.
71 MachineOperand **PhysRegUseDefLists;
73 /// getRegUseDefListHead - Return the head pointer for the register use/def
74 /// list for the specified virtual or physical register.
75 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
76 if (TargetRegisterInfo::isVirtualRegister(RegNo))
77 return VRegInfo[RegNo].second;
78 return PhysRegUseDefLists[RegNo];
81 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
82 if (TargetRegisterInfo::isVirtualRegister(RegNo))
83 return VRegInfo[RegNo].second;
84 return PhysRegUseDefLists[RegNo];
87 /// Get the next element in the use-def chain.
88 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
89 assert(MO && MO->isReg() && "This is not a register operand!");
90 return MO->Contents.Reg.Next;
93 /// UsedRegUnits - This is a bit vector that is computed and set by the
94 /// register allocator, and must be kept up to date by passes that run after
95 /// register allocation (though most don't modify this). This is used
96 /// so that the code generator knows which callee save registers to save and
97 /// for other target specific uses.
98 /// This vector has bits set for register units that are modified in the
99 /// current function. It doesn't include registers clobbered by function
100 /// calls with register mask operands.
101 BitVector UsedRegUnits;
103 /// UsedPhysRegMask - Additional used physregs including aliases.
104 /// This bit vector represents all the registers clobbered by function calls.
105 /// It can model things that UsedRegUnits can't, such as function calls that
106 /// clobber ymm7 but preserve the low half in xmm7.
107 BitVector UsedPhysRegMask;
109 /// ReservedRegs - This is a bit vector of reserved registers. The target
110 /// may change its mind about which registers should be reserved. This
111 /// vector is the frozen set of reserved registers when register allocation
113 BitVector ReservedRegs;
115 /// Keep track of the physical registers that are live in to the function.
116 /// Live in values are typically arguments in registers. LiveIn values are
117 /// allowed to have virtual registers associated with them, stored in the
119 std::vector<std::pair<unsigned, unsigned> > LiveIns;
121 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
122 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
124 explicit MachineRegisterInfo(const TargetMachine &TM);
125 ~MachineRegisterInfo();
127 const TargetRegisterInfo *getTargetRegisterInfo() const {
128 return TM.getRegisterInfo();
131 void resetDelegate(Delegate *delegate) {
132 // Ensure another delegate does not take over unless the current
133 // delegate first unattaches itself. If we ever need to multicast
134 // notifications, we will need to change to using a list.
135 assert(TheDelegate == delegate &&
136 "Only the current delegate can perform reset!");
140 void setDelegate(Delegate *delegate) {
141 assert(delegate && !TheDelegate &&
142 "Attempted to set delegate to null, or to change it without "
143 "first resetting it!");
145 TheDelegate = delegate;
148 //===--------------------------------------------------------------------===//
150 //===--------------------------------------------------------------------===//
152 // isSSA - Returns true when the machine function is in SSA form. Early
153 // passes require the machine function to be in SSA form where every virtual
154 // register has a single defining instruction.
156 // The TwoAddressInstructionPass and PHIElimination passes take the machine
157 // function out of SSA form when they introduce multiple defs per virtual
159 bool isSSA() const { return IsSSA; }
161 // leaveSSA - Indicates that the machine function is no longer in SSA form.
162 void leaveSSA() { IsSSA = false; }
164 /// tracksLiveness - Returns true when tracking register liveness accurately.
166 /// While this flag is true, register liveness information in basic block
167 /// live-in lists and machine instruction operands is accurate. This means it
168 /// can be used to change the code in ways that affect the values in
169 /// registers, for example by the register scavenger.
171 /// When this flag is false, liveness is no longer reliable.
172 bool tracksLiveness() const { return TracksLiveness; }
174 /// invalidateLiveness - Indicates that register liveness is no longer being
175 /// tracked accurately.
177 /// This should be called by late passes that invalidate the liveness
179 void invalidateLiveness() { TracksLiveness = false; }
181 //===--------------------------------------------------------------------===//
183 //===--------------------------------------------------------------------===//
185 // Strictly for use by MachineInstr.cpp.
186 void addRegOperandToUseList(MachineOperand *MO);
188 // Strictly for use by MachineInstr.cpp.
189 void removeRegOperandFromUseList(MachineOperand *MO);
191 // Strictly for use by MachineInstr.cpp.
192 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
194 /// Verify the sanity of the use list for Reg.
195 void verifyUseList(unsigned Reg) const;
197 /// Verify the use list of all registers.
198 void verifyUseLists() const;
200 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
201 /// and uses of a register within the MachineFunction that corresponds to this
202 /// MachineRegisterInfo object.
203 template<bool Uses, bool Defs, bool SkipDebug,
204 bool ByOperand, bool ByInstr, bool ByBundle>
205 class defusechain_iterator;
207 // Make it a friend so it can access getNextOperandForReg().
208 template<bool, bool, bool, bool, bool, bool>
209 friend class defusechain_iterator;
211 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
213 typedef defusechain_iterator<true,true,false,true,false,false>
215 reg_iterator reg_begin(unsigned RegNo) const {
216 return reg_iterator(getRegUseDefListHead(RegNo));
218 static reg_iterator reg_end() { return reg_iterator(0); }
220 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
221 /// of the specified register, stepping by MachineInstr.
222 typedef defusechain_iterator<true,true,false,false,true,false>
224 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
225 return reg_instr_iterator(getRegUseDefListHead(RegNo));
227 static reg_instr_iterator reg_instr_end() { return reg_instr_iterator(0); }
229 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
230 /// of the specified register, stepping by bundle.
231 typedef defusechain_iterator<true,true,false,false,false,true>
233 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
234 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
236 static reg_bundle_iterator reg_bundle_end() { return reg_bundle_iterator(0); }
238 /// reg_empty - Return true if there are no instructions using or defining the
239 /// specified register (it may be live-in).
240 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
242 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
243 /// of the specified register, skipping those marked as Debug.
244 typedef defusechain_iterator<true,true,true,true,false,false>
246 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
247 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
249 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
251 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
252 /// all defs and uses of the specified register, stepping by MachineInstr,
253 /// skipping those marked as Debug.
254 typedef defusechain_iterator<true,true,true,false,true,false>
255 reg_instr_nodbg_iterator;
256 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
257 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
259 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
260 return reg_instr_nodbg_iterator(0);
263 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
264 /// all defs and uses of the specified register, stepping by bundle,
265 /// skipping those marked as Debug.
266 typedef defusechain_iterator<true,true,true,false,false,true>
267 reg_bundle_nodbg_iterator;
268 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
269 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
271 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
272 return reg_bundle_nodbg_iterator(0);
275 /// reg_nodbg_empty - Return true if the only instructions using or defining
276 /// Reg are Debug instructions.
277 bool reg_nodbg_empty(unsigned RegNo) const {
278 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
281 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
282 typedef defusechain_iterator<false,true,false,true,false,false>
284 def_iterator def_begin(unsigned RegNo) const {
285 return def_iterator(getRegUseDefListHead(RegNo));
287 static def_iterator def_end() { return def_iterator(0); }
289 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
290 /// specified register, stepping by MachineInst.
291 typedef defusechain_iterator<false,true,false,false,true,false>
293 def_instr_iterator def_instr_begin(unsigned RegNo) const {
294 return def_instr_iterator(getRegUseDefListHead(RegNo));
296 static def_instr_iterator def_instr_end() { return def_instr_iterator(0); }
298 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
299 /// specified register, stepping by bundle.
300 typedef defusechain_iterator<false,true,false,false,false,true>
302 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
303 return def_bundle_iterator(getRegUseDefListHead(RegNo));
305 static def_bundle_iterator def_bundle_end() { return def_bundle_iterator(0); }
307 /// def_empty - Return true if there are no instructions defining the
308 /// specified register (it may be live-in).
309 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
311 /// hasOneDef - Return true if there is exactly one instruction defining the
312 /// specified register.
313 bool hasOneDef(unsigned RegNo) const {
314 def_iterator DI = def_begin(RegNo);
317 return ++DI == def_end();
320 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
321 typedef defusechain_iterator<true,false,false,true,false,false>
323 use_iterator use_begin(unsigned RegNo) const {
324 return use_iterator(getRegUseDefListHead(RegNo));
326 static use_iterator use_end() { return use_iterator(0); }
328 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
329 /// specified register, stepping by MachineInstr.
330 typedef defusechain_iterator<true,false,false,false,true,false>
332 use_instr_iterator use_instr_begin(unsigned RegNo) const {
333 return use_instr_iterator(getRegUseDefListHead(RegNo));
335 static use_instr_iterator use_instr_end() { return use_instr_iterator(0); }
337 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
338 /// specified register, stepping by bundle.
339 typedef defusechain_iterator<true,false,false,false,false,true>
341 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
342 return use_bundle_iterator(getRegUseDefListHead(RegNo));
344 static use_bundle_iterator use_bundle_end() { return use_bundle_iterator(0); }
346 /// use_empty - Return true if there are no instructions using the specified
348 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
350 /// hasOneUse - Return true if there is exactly one instruction using the
351 /// specified register.
352 bool hasOneUse(unsigned RegNo) const {
353 use_iterator UI = use_begin(RegNo);
356 return ++UI == use_end();
359 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
360 /// specified register, skipping those marked as Debug.
361 typedef defusechain_iterator<true,false,true,true,false,false>
363 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
364 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
366 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
368 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
369 /// all uses of the specified register, stepping by MachineInstr, skipping
370 /// those marked as Debug.
371 typedef defusechain_iterator<true,false,true,false,true,false>
372 use_instr_nodbg_iterator;
373 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
374 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
376 static use_instr_nodbg_iterator use_instr_nodbg_end() {
377 return use_instr_nodbg_iterator(0);
380 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
381 /// all uses of the specified register, stepping by bundle, skipping
382 /// those marked as Debug.
383 typedef defusechain_iterator<true,false,true,false,false,true>
384 use_bundle_nodbg_iterator;
385 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
386 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
388 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
389 return use_bundle_nodbg_iterator(0);
392 /// use_nodbg_empty - Return true if there are no non-Debug instructions
393 /// using the specified register.
394 bool use_nodbg_empty(unsigned RegNo) const {
395 return use_nodbg_begin(RegNo) == use_nodbg_end();
398 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
399 /// instruction using the specified register.
400 bool hasOneNonDBGUse(unsigned RegNo) const;
402 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
403 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
404 /// except that it also changes any definitions of the register as well.
406 /// Note that it is usually necessary to first constrain ToReg's register
407 /// class to match the FromReg constraints using:
409 /// constrainRegClass(ToReg, getRegClass(FromReg))
411 /// That function will return NULL if the virtual registers have incompatible
413 void replaceRegWith(unsigned FromReg, unsigned ToReg);
415 /// getVRegDef - Return the machine instr that defines the specified virtual
416 /// register or null if none is found. This assumes that the code is in SSA
417 /// form, so there should only be one definition.
418 MachineInstr *getVRegDef(unsigned Reg) const;
420 /// getUniqueVRegDef - Return the unique machine instr that defines the
421 /// specified virtual register or null if none is found. If there are
422 /// multiple definitions or no definition, return null.
423 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
425 /// clearKillFlags - Iterate over all the uses of the given register and
426 /// clear the kill flag from the MachineOperand. This function is used by
427 /// optimization passes which extend register lifetimes and need only
428 /// preserve conservative kill flag information.
429 void clearKillFlags(unsigned Reg) const;
432 void dumpUses(unsigned RegNo) const;
435 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
436 /// throughout the function. It is safe to move instructions that read such
438 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
440 /// Get an iterator over the pressure sets affected by the given physical or
441 /// virtual register. If RegUnit is physical, it must be a register unit (from
442 /// MCRegUnitIterator).
443 PSetIterator getPressureSets(unsigned RegUnit) const;
445 //===--------------------------------------------------------------------===//
446 // Virtual Register Info
447 //===--------------------------------------------------------------------===//
449 /// getRegClass - Return the register class of the specified virtual register.
451 const TargetRegisterClass *getRegClass(unsigned Reg) const {
452 return VRegInfo[Reg].first;
455 /// setRegClass - Set the register class of the specified virtual register.
457 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
459 /// constrainRegClass - Constrain the register class of the specified virtual
460 /// register to be a common subclass of RC and the current register class,
461 /// but only if the new class has at least MinNumRegs registers. Return the
462 /// new register class, or NULL if no such class exists.
463 /// This should only be used when the constraint is known to be trivial, like
464 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
466 const TargetRegisterClass *constrainRegClass(unsigned Reg,
467 const TargetRegisterClass *RC,
468 unsigned MinNumRegs = 0);
470 /// recomputeRegClass - Try to find a legal super-class of Reg's register
471 /// class that still satisfies the constraints from the instructions using
472 /// Reg. Returns true if Reg was upgraded.
474 /// This method can be used after constraints have been removed from a
475 /// virtual register, for example after removing instructions or splitting
478 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
480 /// createVirtualRegister - Create and return a new virtual register in the
481 /// function with the specified register class.
483 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
485 /// getNumVirtRegs - Return the number of virtual registers created.
487 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
489 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
490 void clearVirtRegs();
492 /// setRegAllocationHint - Specify a register allocation hint for the
493 /// specified virtual register.
494 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
495 RegAllocHints[Reg].first = Type;
496 RegAllocHints[Reg].second = PrefReg;
499 /// getRegAllocationHint - Return the register allocation hint for the
500 /// specified virtual register.
501 std::pair<unsigned, unsigned>
502 getRegAllocationHint(unsigned Reg) const {
503 return RegAllocHints[Reg];
506 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
507 /// standard simple hint (Type == 0) is not set.
508 unsigned getSimpleHint(unsigned Reg) const {
509 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
510 return Hint.first ? 0 : Hint.second;
513 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
514 /// specified register as undefined which causes the DBG_VALUE to be
515 /// deleted during LiveDebugVariables analysis.
516 void markUsesInDebugValueAsUndef(unsigned Reg) const;
518 //===--------------------------------------------------------------------===//
519 // Physical Register Use Info
520 //===--------------------------------------------------------------------===//
522 /// isPhysRegUsed - Return true if the specified register is used in this
523 /// function. Also check for clobbered aliases and registers clobbered by
524 /// function calls with register mask operands.
526 /// This only works after register allocation. It is primarily used by
527 /// PrologEpilogInserter to determine which callee-saved registers need
529 bool isPhysRegUsed(unsigned Reg) const {
530 if (UsedPhysRegMask.test(Reg))
532 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
533 Units.isValid(); ++Units)
534 if (UsedRegUnits.test(*Units))
539 /// Mark the specified register unit as used in this function.
540 /// This should only be called during and after register allocation.
541 void setRegUnitUsed(unsigned RegUnit) {
542 UsedRegUnits.set(RegUnit);
545 /// setPhysRegUsed - Mark the specified register used in this function.
546 /// This should only be called during and after register allocation.
547 void setPhysRegUsed(unsigned Reg) {
548 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
549 Units.isValid(); ++Units)
550 UsedRegUnits.set(*Units);
553 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
554 /// This corresponds to the bit mask attached to register mask operands.
555 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
556 UsedPhysRegMask.setBitsNotInMask(RegMask);
559 /// setPhysRegUnused - Mark the specified register unused in this function.
560 /// This should only be called during and after register allocation.
561 void setPhysRegUnused(unsigned Reg) {
562 UsedPhysRegMask.reset(Reg);
563 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
564 Units.isValid(); ++Units)
565 UsedRegUnits.reset(*Units);
569 //===--------------------------------------------------------------------===//
570 // Reserved Register Info
571 //===--------------------------------------------------------------------===//
573 // The set of reserved registers must be invariant during register
574 // allocation. For example, the target cannot suddenly decide it needs a
575 // frame pointer when the register allocator has already used the frame
576 // pointer register for something else.
578 // These methods can be used by target hooks like hasFP() to avoid changing
579 // the reserved register set during register allocation.
581 /// freezeReservedRegs - Called by the register allocator to freeze the set
582 /// of reserved registers before allocation begins.
583 void freezeReservedRegs(const MachineFunction&);
585 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
586 /// to ensure the set of reserved registers stays constant.
587 bool reservedRegsFrozen() const {
588 return !ReservedRegs.empty();
591 /// canReserveReg - Returns true if PhysReg can be used as a reserved
592 /// register. Any register can be reserved before freezeReservedRegs() is
594 bool canReserveReg(unsigned PhysReg) const {
595 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
598 /// getReservedRegs - Returns a reference to the frozen set of reserved
599 /// registers. This method should always be preferred to calling
600 /// TRI::getReservedRegs() when possible.
601 const BitVector &getReservedRegs() const {
602 assert(reservedRegsFrozen() &&
603 "Reserved registers haven't been frozen yet. "
604 "Use TRI::getReservedRegs().");
608 /// isReserved - Returns true when PhysReg is a reserved register.
610 /// Reserved registers may belong to an allocatable register class, but the
611 /// target has explicitly requested that they are not used.
613 bool isReserved(unsigned PhysReg) const {
614 return getReservedRegs().test(PhysReg);
617 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
618 /// register class and it hasn't been reserved.
620 /// Allocatable registers may show up in the allocation order of some virtual
621 /// register, so a register allocator needs to track its liveness and
623 bool isAllocatable(unsigned PhysReg) const {
624 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
625 !isReserved(PhysReg);
628 //===--------------------------------------------------------------------===//
630 //===--------------------------------------------------------------------===//
632 /// addLiveIn - Add the specified register as a live-in. Note that it
633 /// is an error to add the same register to the same set more than once.
634 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
635 LiveIns.push_back(std::make_pair(Reg, vreg));
638 // Iteration support for the live-ins set. It's kept in sorted order
639 // by register number.
640 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
642 livein_iterator livein_begin() const { return LiveIns.begin(); }
643 livein_iterator livein_end() const { return LiveIns.end(); }
644 bool livein_empty() const { return LiveIns.empty(); }
646 bool isLiveIn(unsigned Reg) const;
648 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
649 /// corresponding live-in physical register.
650 unsigned getLiveInPhysReg(unsigned VReg) const;
652 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
653 /// corresponding live-in physical register.
654 unsigned getLiveInVirtReg(unsigned PReg) const;
656 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
657 /// into the given entry block.
658 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
659 const TargetRegisterInfo &TRI,
660 const TargetInstrInfo &TII);
662 /// defusechain_iterator - This class provides iterator support for machine
663 /// operands in the function that use or define a specific register. If
664 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
665 /// returns defs. If neither are true then you are silly and it always
666 /// returns end(). If SkipDebug is true it skips uses marked Debug
667 /// when incrementing.
668 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
669 bool ByOperand, bool ByInstr, bool ByBundle>
670 class defusechain_iterator
671 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
673 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
674 // If the first node isn't one we're interested in, advance to one that
675 // we are interested in.
677 if ((!ReturnUses && op->isUse()) ||
678 (!ReturnDefs && op->isDef()) ||
679 (SkipDebug && op->isDebug()))
683 friend class MachineRegisterInfo;
686 assert(Op && "Cannot increment end iterator!");
687 Op = getNextOperandForReg(Op);
689 // All defs come before the uses, so stop def_iterator early.
695 assert(!Op->isDebug() && "Can't have debug defs");
698 // If this is an operand we don't care about, skip it.
699 while (Op && ((!ReturnDefs && Op->isDef()) ||
700 (SkipDebug && Op->isDebug())))
701 Op = getNextOperandForReg(Op);
705 typedef std::iterator<std::forward_iterator_tag,
706 MachineInstr, ptrdiff_t>::reference reference;
707 typedef std::iterator<std::forward_iterator_tag,
708 MachineInstr, ptrdiff_t>::pointer pointer;
710 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
711 defusechain_iterator() : Op(0) {}
713 bool operator==(const defusechain_iterator &x) const {
716 bool operator!=(const defusechain_iterator &x) const {
717 return !operator==(x);
720 /// atEnd - return true if this iterator is equal to reg_end() on the value.
721 bool atEnd() const { return Op == 0; }
723 // Iterator traversal: forward iteration only
724 defusechain_iterator &operator++() { // Preincrement
725 assert(Op && "Cannot increment end iterator!");
729 MachineInstr *P = Op->getParent();
732 } while (Op && Op->getParent() == P);
733 } else if (ByBundle) {
734 MachineInstr *P = getBundleStart(Op->getParent());
737 } while (Op && getBundleStart(Op->getParent()) == P);
742 defusechain_iterator operator++(int) { // Postincrement
743 defusechain_iterator tmp = *this; ++*this; return tmp;
746 MachineOperand &getOperand() const {
747 assert(Op && "Cannot dereference end iterator!");
751 /// getOperandNo - Return the operand # of this MachineOperand in its
753 unsigned getOperandNo() const {
754 assert(Op && "Cannot dereference end iterator!");
755 return Op - &Op->getParent()->getOperand(0);
758 // Retrieve a reference to the current operand.
759 MachineInstr &operator*() const {
760 assert(Op && "Cannot dereference end iterator!");
761 return *Op->getParent();
764 MachineInstr *operator->() const {
765 assert(Op && "Cannot dereference end iterator!");
766 return Op->getParent();
771 /// Iterate over the pressure sets affected by the given physical or virtual
772 /// register. If Reg is physical, it must be a register unit (from
773 /// MCRegUnitIterator).
778 PSetIterator(): PSet(0), Weight(0) {}
779 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
780 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
781 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
782 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
783 PSet = TRI->getRegClassPressureSets(RC);
784 Weight = TRI->getRegClassWeight(RC).RegWeight;
787 PSet = TRI->getRegUnitPressureSets(RegUnit);
788 Weight = TRI->getRegUnitWeight(RegUnit);
793 bool isValid() const { return PSet; }
795 unsigned getWeight() const { return Weight; }
797 unsigned operator*() const { return *PSet; }
800 assert(isValid() && "Invalid PSetIterator.");
807 inline PSetIterator MachineRegisterInfo::
808 getPressureSets(unsigned RegUnit) const {
809 return PSetIterator(RegUnit, this);
812 } // End llvm namespace