1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides an interface for customizing the standard MachineScheduler
11 // pass. Note that the entire pass may be replaced as follows:
13 // <Target>TargetMachine::createPassConfig(PassManagerBase &PM) {
14 // PM.substitutePass(&MachineSchedulerID, &CustomSchedulerPassID);
17 // The MachineScheduler pass is only responsible for choosing the regions to be
18 // scheduled. Targets can override the DAG builder and scheduler without
19 // replacing the pass as follows:
21 // ScheduleDAGInstrs *<Target>PassConfig::
22 // createMachineScheduler(MachineSchedContext *C) {
23 // return new CustomMachineScheduler(C);
26 // The default scheduler, ScheduleDAGMILive, builds the DAG and drives list
27 // scheduling while updating the instruction stream, register pressure, and live
28 // intervals. Most targets don't need to override the DAG builder and list
29 // schedulier, but subtargets that require custom scheduling heuristics may
30 // plugin an alternate MachineSchedStrategy. The strategy is responsible for
31 // selecting the highest priority node from the list:
33 // ScheduleDAGInstrs *<Target>PassConfig::
34 // createMachineScheduler(MachineSchedContext *C) {
35 // return new ScheduleDAGMI(C, CustomStrategy(C));
38 // The DAG builder can also be customized in a sense by adding DAG mutations
39 // that will run after DAG building and before list scheduling. DAG mutations
40 // can adjust dependencies based on target-specific knowledge or add weak edges
43 // ScheduleDAGInstrs *<Target>PassConfig::
44 // createMachineScheduler(MachineSchedContext *C) {
45 // ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
50 // A target that supports alternative schedulers can use the
51 // MachineSchedRegistry to allow command line selection. This can be done by
52 // implementing the following boilerplate:
54 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
55 // return new CustomMachineScheduler(C);
57 // static MachineSchedRegistry
58 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
59 // createCustomMachineSched);
62 // Finally, subtargets that don't need to implement custom heuristics but would
63 // like to configure the GenericScheduler's policy for a given scheduler region,
64 // including scheduling direction and register pressure tracking policy, can do
67 // void <SubTarget>Subtarget::
68 // overrideSchedPolicy(MachineSchedPolicy &Policy,
69 // MachineInstr *begin,
71 // unsigned NumRegionInstrs) const {
72 // Policy.<Flag> = true;
75 //===----------------------------------------------------------------------===//
77 #ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
78 #define LLVM_CODEGEN_MACHINESCHEDULER_H
80 #include "llvm/Analysis/AliasAnalysis.h"
81 #include "llvm/CodeGen/MachinePassRegistry.h"
82 #include "llvm/CodeGen/RegisterPressure.h"
83 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
88 extern cl::opt<bool> ForceTopDown;
89 extern cl::opt<bool> ForceBottomUp;
92 class MachineDominatorTree;
93 class MachineLoopInfo;
94 class RegisterClassInfo;
95 class ScheduleDAGInstrs;
97 class ScheduleHazardRecognizer;
99 /// MachineSchedContext provides enough context from the MachineScheduler pass
100 /// for the target to instantiate a scheduler.
101 struct MachineSchedContext {
103 const MachineLoopInfo *MLI;
104 const MachineDominatorTree *MDT;
105 const TargetPassConfig *PassConfig;
109 RegisterClassInfo *RegClassInfo;
111 MachineSchedContext();
112 virtual ~MachineSchedContext();
115 /// MachineSchedRegistry provides a selection of available machine instruction
117 class MachineSchedRegistry : public MachinePassRegistryNode {
119 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
121 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
122 typedef ScheduleDAGCtor FunctionPassCtor;
124 static MachinePassRegistry Registry;
126 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
127 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
130 ~MachineSchedRegistry() { Registry.Remove(this); }
134 MachineSchedRegistry *getNext() const {
135 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
137 static MachineSchedRegistry *getList() {
138 return (MachineSchedRegistry *)Registry.getList();
140 static void setListener(MachinePassRegistryListener *L) {
141 Registry.setListener(L);
147 /// Define a generic scheduling policy for targets that don't provide their own
148 /// MachineSchedStrategy. This can be overriden for each scheduling region
149 /// before building the DAG.
150 struct MachineSchedPolicy {
151 // Allow the scheduler to disable register pressure tracking.
152 bool ShouldTrackPressure;
154 // Allow the scheduler to force top-down or bottom-up scheduling. If neither
155 // is true, the scheduler runs in both directions and converges.
159 MachineSchedPolicy(): ShouldTrackPressure(false), OnlyTopDown(false),
160 OnlyBottomUp(false) {}
163 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
166 /// Initialization sequence:
167 /// initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
168 class MachineSchedStrategy {
169 virtual void anchor();
171 virtual ~MachineSchedStrategy() {}
173 /// Optionally override the per-region scheduling policy.
174 virtual void initPolicy(MachineBasicBlock::iterator Begin,
175 MachineBasicBlock::iterator End,
176 unsigned NumRegionInstrs) {}
178 virtual void dumpPolicy() {}
180 /// Check if pressure tracking is needed before building the DAG and
181 /// initializing this strategy. Called after initPolicy.
182 virtual bool shouldTrackPressure() const { return true; }
184 /// Initialize the strategy after building the DAG for a new region.
185 virtual void initialize(ScheduleDAGMI *DAG) = 0;
187 /// Notify this strategy that all roots have been released (including those
188 /// that depend on EntrySU or ExitSU).
189 virtual void registerRoots() {}
191 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
192 /// schedule the node at the top of the unscheduled region. Otherwise it will
193 /// be scheduled at the bottom.
194 virtual SUnit *pickNode(bool &IsTopNode) = 0;
196 /// \brief Scheduler callback to notify that a new subtree is scheduled.
197 virtual void scheduleTree(unsigned SubtreeID) {}
199 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
200 /// instruction and updated scheduled/remaining flags in the DAG nodes.
201 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
203 /// When all predecessor dependencies have been resolved, free this node for
204 /// top-down scheduling.
205 virtual void releaseTopNode(SUnit *SU) = 0;
206 /// When all successor dependencies have been resolved, free this node for
207 /// bottom-up scheduling.
208 virtual void releaseBottomNode(SUnit *SU) = 0;
211 /// Mutate the DAG as a postpass after normal DAG building.
212 class ScheduleDAGMutation {
213 virtual void anchor();
215 virtual ~ScheduleDAGMutation() {}
217 virtual void apply(ScheduleDAGMI *DAG) = 0;
220 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
221 /// schedules machine instructions according to the given MachineSchedStrategy
222 /// without much extra book-keeping. This is the common functionality between
223 /// PreRA and PostRA MachineScheduler.
224 class ScheduleDAGMI : public ScheduleDAGInstrs {
227 std::unique_ptr<MachineSchedStrategy> SchedImpl;
229 /// Topo - A topological ordering for SUnits which permits fast IsReachable
230 /// and similar queries.
231 ScheduleDAGTopologicalSort Topo;
233 /// Ordered list of DAG postprocessing steps.
234 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
236 /// The top of the unscheduled zone.
237 MachineBasicBlock::iterator CurrentTop;
239 /// The bottom of the unscheduled zone.
240 MachineBasicBlock::iterator CurrentBottom;
242 /// Record the next node in a scheduled cluster.
243 const SUnit *NextClusterPred;
244 const SUnit *NextClusterSucc;
247 /// The number of instructions scheduled so far. Used to cut off the
248 /// scheduler at the point determined by misched-cutoff.
249 unsigned NumInstrsScheduled;
252 ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
254 : ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA,
255 /*RemoveKillFlags=*/IsPostRA, C->LIS),
256 AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
257 CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
259 NumInstrsScheduled = 0;
263 // Provide a vtable anchor
264 ~ScheduleDAGMI() override;
266 /// Return true if this DAG supports VReg liveness and RegPressure.
267 virtual bool hasVRegLiveness() const { return false; }
269 /// Add a postprocessing step to the DAG builder.
270 /// Mutations are applied in the order that they are added after normal DAG
271 /// building and before MachineSchedStrategy initialization.
273 /// ScheduleDAGMI takes ownership of the Mutation object.
274 void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
275 Mutations.push_back(std::move(Mutation));
278 /// \brief True if an edge can be added from PredSU to SuccSU without creating
280 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
282 /// \brief Add a DAG edge to the given SU with the given predecessor
285 /// \returns true if the edge may be added without creating a cycle OR if an
286 /// equivalent edge already existed (false indicates failure).
287 bool addEdge(SUnit *SuccSU, const SDep &PredDep);
289 MachineBasicBlock::iterator top() const { return CurrentTop; }
290 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
292 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
293 /// region. This covers all instructions in a block, while schedule() may only
295 void enterRegion(MachineBasicBlock *bb,
296 MachineBasicBlock::iterator begin,
297 MachineBasicBlock::iterator end,
298 unsigned regioninstrs) override;
300 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
301 /// reorderable instructions.
302 void schedule() override;
304 /// Change the position of an instruction within the basic block and update
305 /// live ranges and region boundary iterators.
306 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
308 const SUnit *getNextClusterPred() const { return NextClusterPred; }
310 const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
312 void viewGraph(const Twine &Name, const Twine &Title) override;
313 void viewGraph() override;
316 // Top-Level entry points for the schedule() driver...
318 /// Apply each ScheduleDAGMutation step in order. This allows different
319 /// instances of ScheduleDAGMI to perform custom DAG postprocessing.
320 void postprocessDAG();
322 /// Release ExitSU predecessors and setup scheduler queues.
323 void initQueues(ArrayRef<SUnit*> TopRoots, ArrayRef<SUnit*> BotRoots);
325 /// Update scheduler DAG and queues after scheduling an instruction.
326 void updateQueues(SUnit *SU, bool IsTopNode);
328 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
329 void placeDebugValues();
331 /// \brief dump the scheduled Sequence.
332 void dumpSchedule() const;
335 bool checkSchedLimit();
337 void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
338 SmallVectorImpl<SUnit*> &BotRoots);
340 void releaseSucc(SUnit *SU, SDep *SuccEdge);
341 void releaseSuccessors(SUnit *SU);
342 void releasePred(SUnit *SU, SDep *PredEdge);
343 void releasePredecessors(SUnit *SU);
346 /// ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules
347 /// machine instructions while updating LiveIntervals and tracking regpressure.
348 class ScheduleDAGMILive : public ScheduleDAGMI {
350 RegisterClassInfo *RegClassInfo;
352 /// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
354 SchedDFSResult *DFSResult;
355 BitVector ScheduledTrees;
357 MachineBasicBlock::iterator LiveRegionEnd;
359 // Map each SU to its summary of pressure changes. This array is updated for
360 // liveness during bottom-up scheduling. Top-down scheduling may proceed but
361 // has no affect on the pressure diffs.
362 PressureDiffs SUPressureDiffs;
364 /// Register pressure in this region computed by initRegPressure.
365 bool ShouldTrackPressure;
366 IntervalPressure RegPressure;
367 RegPressureTracker RPTracker;
369 /// List of pressure sets that exceed the target's pressure limit before
370 /// scheduling, listed in increasing set ID order. Each pressure set is paired
371 /// with its max pressure in the currently scheduled regions.
372 std::vector<PressureChange> RegionCriticalPSets;
374 /// The top of the unscheduled zone.
375 IntervalPressure TopPressure;
376 RegPressureTracker TopRPTracker;
378 /// The bottom of the unscheduled zone.
379 IntervalPressure BotPressure;
380 RegPressureTracker BotRPTracker;
383 ScheduleDAGMILive(MachineSchedContext *C,
384 std::unique_ptr<MachineSchedStrategy> S)
385 : ScheduleDAGMI(C, std::move(S), /*IsPostRA=*/false),
386 RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
387 ShouldTrackPressure(false), RPTracker(RegPressure),
388 TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}
390 ~ScheduleDAGMILive() override;
392 /// Return true if this DAG supports VReg liveness and RegPressure.
393 bool hasVRegLiveness() const override { return true; }
395 /// \brief Return true if register pressure tracking is enabled.
396 bool isTrackingPressure() const { return ShouldTrackPressure; }
398 /// Get current register pressure for the top scheduled instructions.
399 const IntervalPressure &getTopPressure() const { return TopPressure; }
400 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
402 /// Get current register pressure for the bottom scheduled instructions.
403 const IntervalPressure &getBotPressure() const { return BotPressure; }
404 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
406 /// Get register pressure for the entire scheduling region before scheduling.
407 const IntervalPressure &getRegPressure() const { return RegPressure; }
409 const std::vector<PressureChange> &getRegionCriticalPSets() const {
410 return RegionCriticalPSets;
413 PressureDiff &getPressureDiff(const SUnit *SU) {
414 return SUPressureDiffs[SU->NodeNum];
417 /// Compute a DFSResult after DAG building is complete, and before any
418 /// queue comparisons.
419 void computeDFSResult();
421 /// Return a non-null DFS result if the scheduling strategy initialized it.
422 const SchedDFSResult *getDFSResult() const { return DFSResult; }
424 BitVector &getScheduledTrees() { return ScheduledTrees; }
426 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
427 /// region. This covers all instructions in a block, while schedule() may only
429 void enterRegion(MachineBasicBlock *bb,
430 MachineBasicBlock::iterator begin,
431 MachineBasicBlock::iterator end,
432 unsigned regioninstrs) override;
434 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
435 /// reorderable instructions.
436 void schedule() override;
438 /// Compute the cyclic critical path through the DAG.
439 unsigned computeCyclicCriticalPath();
442 // Top-Level entry points for the schedule() driver...
444 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
445 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
446 /// region, TopTracker and BottomTracker will be initialized to the top and
447 /// bottom of the DAG region without covereing any unscheduled instruction.
448 void buildDAGWithRegPressure();
450 /// Move an instruction and update register pressure.
451 void scheduleMI(SUnit *SU, bool IsTopNode);
455 void initRegPressure();
457 void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
459 void updateScheduledPressure(const SUnit *SU,
460 const std::vector<unsigned> &NewMaxPressure);
463 //===----------------------------------------------------------------------===//
465 /// Helpers for implementing custom MachineSchedStrategy classes. These take
466 /// care of the book-keeping associated with list scheduling heuristics.
468 //===----------------------------------------------------------------------===//
470 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
471 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
472 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
474 /// This is a convenience class that may be used by implementations of
475 /// MachineSchedStrategy.
479 std::vector<SUnit*> Queue;
482 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
484 unsigned getID() const { return ID; }
486 StringRef getName() const { return Name; }
488 // SU is in this queue if it's NodeQueueID is a superset of this ID.
489 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
491 bool empty() const { return Queue.empty(); }
493 void clear() { Queue.clear(); }
495 unsigned size() const { return Queue.size(); }
497 typedef std::vector<SUnit*>::iterator iterator;
499 iterator begin() { return Queue.begin(); }
501 iterator end() { return Queue.end(); }
503 ArrayRef<SUnit*> elements() { return Queue; }
505 iterator find(SUnit *SU) {
506 return std::find(Queue.begin(), Queue.end(), SU);
509 void push(SUnit *SU) {
511 SU->NodeQueueId |= ID;
514 iterator remove(iterator I) {
515 (*I)->NodeQueueId &= ~ID;
517 unsigned idx = I - Queue.begin();
519 return Queue.begin() + idx;
525 /// Summarize the unscheduled region.
526 struct SchedRemainder {
527 // Critical path through the DAG in expected latency.
528 unsigned CriticalPath;
529 unsigned CyclicCritPath;
531 // Scaled count of micro-ops left to schedule.
532 unsigned RemIssueCount;
534 bool IsAcyclicLatencyLimited;
536 // Unscheduled resources
537 SmallVector<unsigned, 16> RemainingCounts;
543 IsAcyclicLatencyLimited = false;
544 RemainingCounts.clear();
547 SchedRemainder() { reset(); }
549 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
552 /// Each Scheduling boundary is associated with ready queues. It tracks the
553 /// current cycle in the direction of movement, and maintains the state
554 /// of "hazards" and other interlocks at the current cycle.
555 class SchedBoundary {
557 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
565 const TargetSchedModel *SchedModel;
568 ReadyQueue Available;
571 ScheduleHazardRecognizer *HazardRec;
574 /// True if the pending Q should be checked/updated before scheduling another
578 // For heuristics, keep a list of the nodes that immediately depend on the
579 // most recently scheduled node.
580 SmallPtrSet<const SUnit*, 8> NextSUs;
582 /// Number of cycles it takes to issue the instructions scheduled in this
583 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
587 /// Micro-ops issued in the current cycle
590 /// MinReadyCycle - Cycle of the soonest available instruction.
591 unsigned MinReadyCycle;
593 // The expected latency of the critical path in this scheduled zone.
594 unsigned ExpectedLatency;
596 // The latency of dependence chains leading into this zone.
597 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
598 // For each cycle scheduled: DLat -= 1.
599 unsigned DependentLatency;
601 /// Count the scheduled (issued) micro-ops that can be retired by
602 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
603 unsigned RetiredMOps;
605 // Count scheduled resources that have been executed. Resources are
606 // considered executed if they become ready in the time that it takes to
607 // saturate any resource including the one in question. Counts are scaled
608 // for direct comparison with other resources. Counts can be compared with
609 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
610 SmallVector<unsigned, 16> ExecutedResCounts;
612 /// Cache the max count for a single resource.
613 unsigned MaxExecutedResCount;
615 // Cache the critical resources ID in this scheduled zone.
616 unsigned ZoneCritResIdx;
618 // Is the scheduled region resource limited vs. latency limited.
619 bool IsResourceLimited;
621 // Record the highest cycle at which each resource has been reserved by a
622 // scheduled instruction.
623 SmallVector<unsigned, 16> ReservedCycles;
626 // Remember the greatest possible stall as an upper bound on the number of
627 // times we should retry the pending queue because of a hazard.
628 unsigned MaxObservedStall;
632 /// Pending queues extend the ready queues with the same ID and the
634 SchedBoundary(unsigned ID, const Twine &Name):
635 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
636 Pending(ID << LogMaxQID, Name+".P"),
645 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
646 SchedRemainder *rem);
649 return Available.getID() == TopQID;
652 /// Number of cycles to issue the instructions scheduled in this zone.
653 unsigned getCurrCycle() const { return CurrCycle; }
655 /// Micro-ops issued in the current cycle
656 unsigned getCurrMOps() const { return CurrMOps; }
658 /// Return true if the given SU is used by the most recently scheduled
660 bool isNextSU(const SUnit *SU) const { return NextSUs.count(SU); }
662 // The latency of dependence chains leading into this zone.
663 unsigned getDependentLatency() const { return DependentLatency; }
665 /// Get the number of latency cycles "covered" by the scheduled
666 /// instructions. This is the larger of the critical path within the zone
667 /// and the number of cycles required to issue the instructions.
668 unsigned getScheduledLatency() const {
669 return std::max(ExpectedLatency, CurrCycle);
672 unsigned getUnscheduledLatency(SUnit *SU) const {
673 return isTop() ? SU->getHeight() : SU->getDepth();
676 unsigned getResourceCount(unsigned ResIdx) const {
677 return ExecutedResCounts[ResIdx];
680 /// Get the scaled count of scheduled micro-ops and resources, including
681 /// executed resources.
682 unsigned getCriticalCount() const {
684 return RetiredMOps * SchedModel->getMicroOpFactor();
685 return getResourceCount(ZoneCritResIdx);
688 /// Get a scaled count for the minimum execution time of the scheduled
689 /// micro-ops that are ready to execute by getExecutedCount. Notice the
691 unsigned getExecutedCount() const {
692 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
693 MaxExecutedResCount);
696 unsigned getZoneCritResIdx() const { return ZoneCritResIdx; }
698 // Is the scheduled region resource limited vs. latency limited.
699 bool isResourceLimited() const { return IsResourceLimited; }
701 /// Get the difference between the given SUnit's ready time and the current
703 unsigned getLatencyStallCycles(SUnit *SU);
705 unsigned getNextResourceCycle(unsigned PIdx, unsigned Cycles);
707 bool checkHazard(SUnit *SU);
709 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
711 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
713 void releaseNode(SUnit *SU, unsigned ReadyCycle);
715 void releaseTopNode(SUnit *SU);
717 void releaseBottomNode(SUnit *SU);
719 void bumpCycle(unsigned NextCycle);
721 void incExecutedResources(unsigned PIdx, unsigned Count);
723 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
725 void bumpNode(SUnit *SU);
727 void releasePending();
729 void removeReady(SUnit *SU);
731 /// Call this before applying any other heuristics to the Available queue.
732 /// Updates the Available/Pending Q's if necessary and returns the single
733 /// available instruction, or NULL if there are multiple candidates.
734 SUnit *pickOnlyChoice();
737 void dumpScheduledState();
741 /// Base class for GenericScheduler. This class maintains information about
742 /// scheduling candidates based on TargetSchedModel making it easy to implement
743 /// heuristics for either preRA or postRA scheduling.
744 class GenericSchedulerBase : public MachineSchedStrategy {
746 /// Represent the type of SchedCandidate found within a single queue.
747 /// pickNodeBidirectional depends on these listed by decreasing priority.
749 NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
750 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
751 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
754 static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
757 /// Policy for scheduling the next instruction in the candidate's zone.
760 unsigned ReduceResIdx;
761 unsigned DemandResIdx;
763 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
766 /// Status of an instruction's critical resource consumption.
767 struct SchedResourceDelta {
768 // Count critical resources in the scheduled region required by SU.
769 unsigned CritResources;
771 // Count critical resources from another region consumed by SU.
772 unsigned DemandedResources;
774 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
776 bool operator==(const SchedResourceDelta &RHS) const {
777 return CritResources == RHS.CritResources
778 && DemandedResources == RHS.DemandedResources;
780 bool operator!=(const SchedResourceDelta &RHS) const {
781 return !operator==(RHS);
785 /// Store the state used by GenericScheduler heuristics, required for the
786 /// lifetime of one invocation of pickNode().
787 struct SchedCandidate {
790 // The best SUnit candidate.
793 // The reason for this candidate.
796 // Set of reasons that apply to multiple candidates.
797 uint32_t RepeatReasonSet;
799 // Register pressure values for the best candidate.
800 RegPressureDelta RPDelta;
802 // Critical resource consumption of the best candidate.
803 SchedResourceDelta ResDelta;
805 SchedCandidate(const CandPolicy &policy)
806 : Policy(policy), SU(nullptr), Reason(NoCand), RepeatReasonSet(0) {}
808 bool isValid() const { return SU; }
810 // Copy the status of another candidate without changing policy.
811 void setBest(SchedCandidate &Best) {
812 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
814 Reason = Best.Reason;
815 RPDelta = Best.RPDelta;
816 ResDelta = Best.ResDelta;
819 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
820 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
822 void initResourceDelta(const ScheduleDAGMI *DAG,
823 const TargetSchedModel *SchedModel);
827 const MachineSchedContext *Context;
828 const TargetSchedModel *SchedModel;
829 const TargetRegisterInfo *TRI;
833 GenericSchedulerBase(const MachineSchedContext *C):
834 Context(C), SchedModel(nullptr), TRI(nullptr) {}
836 void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
837 SchedBoundary *OtherZone);
840 void traceCandidate(const SchedCandidate &Cand);
844 /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
846 class GenericScheduler : public GenericSchedulerBase {
847 ScheduleDAGMILive *DAG;
849 // State of the top and bottom scheduled instruction boundaries.
853 MachineSchedPolicy RegionPolicy;
855 GenericScheduler(const MachineSchedContext *C):
856 GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
857 Bot(SchedBoundary::BotQID, "BotQ") {}
859 void initPolicy(MachineBasicBlock::iterator Begin,
860 MachineBasicBlock::iterator End,
861 unsigned NumRegionInstrs) override;
863 void dumpPolicy() override;
865 bool shouldTrackPressure() const override {
866 return RegionPolicy.ShouldTrackPressure;
869 void initialize(ScheduleDAGMI *dag) override;
871 SUnit *pickNode(bool &IsTopNode) override;
873 void schedNode(SUnit *SU, bool IsTopNode) override;
875 void releaseTopNode(SUnit *SU) override {
876 Top.releaseTopNode(SU);
879 void releaseBottomNode(SUnit *SU) override {
880 Bot.releaseBottomNode(SU);
883 void registerRoots() override;
886 void checkAcyclicLatency();
888 void tryCandidate(SchedCandidate &Cand,
889 SchedCandidate &TryCand,
891 const RegPressureTracker &RPTracker,
892 RegPressureTracker &TempTracker);
894 SUnit *pickNodeBidirectional(bool &IsTopNode);
896 void pickNodeFromQueue(SchedBoundary &Zone,
897 const RegPressureTracker &RPTracker,
898 SchedCandidate &Candidate);
900 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
903 /// PostGenericScheduler - Interface to the scheduling algorithm used by
906 /// Callbacks from ScheduleDAGMI:
907 /// initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
908 class PostGenericScheduler : public GenericSchedulerBase {
911 SmallVector<SUnit*, 8> BotRoots;
913 PostGenericScheduler(const MachineSchedContext *C):
914 GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ") {}
916 ~PostGenericScheduler() override {}
918 void initPolicy(MachineBasicBlock::iterator Begin,
919 MachineBasicBlock::iterator End,
920 unsigned NumRegionInstrs) override {
921 /* no configurable policy */
924 /// PostRA scheduling does not track pressure.
925 bool shouldTrackPressure() const override { return false; }
927 void initialize(ScheduleDAGMI *Dag) override;
929 void registerRoots() override;
931 SUnit *pickNode(bool &IsTopNode) override;
933 void scheduleTree(unsigned SubtreeID) override {
934 llvm_unreachable("PostRA scheduler does not support subtree analysis.");
937 void schedNode(SUnit *SU, bool IsTopNode) override;
939 void releaseTopNode(SUnit *SU) override {
940 Top.releaseTopNode(SU);
943 // Only called for roots.
944 void releaseBottomNode(SUnit *SU) override {
945 BotRoots.push_back(SU);
949 void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
951 void pickNodeFromQueue(SchedCandidate &Cand);