1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides an interface for customizing the standard MachineScheduler
11 // pass. Note that the entire pass may be replaced as follows:
13 // <Target>TargetMachine::createPassConfig(PassManagerBase &PM) {
14 // PM.substitutePass(&MachineSchedulerID, &CustomSchedulerPassID);
17 // The MachineScheduler pass is only responsible for choosing the regions to be
18 // scheduled. Targets can override the DAG builder and scheduler without
19 // replacing the pass as follows:
21 // ScheduleDAGInstrs *<Target>PassConfig::
22 // createMachineScheduler(MachineSchedContext *C) {
23 // return new CustomMachineScheduler(C);
26 // The default scheduler, ScheduleDAGMILive, builds the DAG and drives list
27 // scheduling while updating the instruction stream, register pressure, and live
28 // intervals. Most targets don't need to override the DAG builder and list
29 // schedulier, but subtargets that require custom scheduling heuristics may
30 // plugin an alternate MachineSchedStrategy. The strategy is responsible for
31 // selecting the highest priority node from the list:
33 // ScheduleDAGInstrs *<Target>PassConfig::
34 // createMachineScheduler(MachineSchedContext *C) {
35 // return new ScheduleDAGMI(C, CustomStrategy(C));
38 // The DAG builder can also be customized in a sense by adding DAG mutations
39 // that will run after DAG building and before list scheduling. DAG mutations
40 // can adjust dependencies based on target-specific knowledge or add weak edges
43 // ScheduleDAGInstrs *<Target>PassConfig::
44 // createMachineScheduler(MachineSchedContext *C) {
45 // ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
50 // A target that supports alternative schedulers can use the
51 // MachineSchedRegistry to allow command line selection. This can be done by
52 // implementing the following boilerplate:
54 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
55 // return new CustomMachineScheduler(C);
57 // static MachineSchedRegistry
58 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
59 // createCustomMachineSched);
62 // Finally, subtargets that don't need to implement custom heuristics but would
63 // like to configure the GenericScheduler's policy for a given scheduler region,
64 // including scheduling direction and register pressure tracking policy, can do
67 // void <SubTarget>Subtarget::
68 // overrideSchedPolicy(MachineSchedPolicy &Policy,
69 // MachineInstr *begin,
71 // unsigned NumRegionInstrs) const {
72 // Policy.<Flag> = true;
75 //===----------------------------------------------------------------------===//
77 #ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
78 #define LLVM_CODEGEN_MACHINESCHEDULER_H
80 #include "llvm/Analysis/AliasAnalysis.h"
81 #include "llvm/CodeGen/MachinePassRegistry.h"
82 #include "llvm/CodeGen/RegisterPressure.h"
83 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
88 extern cl::opt<bool> ForceTopDown;
89 extern cl::opt<bool> ForceBottomUp;
92 class MachineDominatorTree;
93 class MachineLoopInfo;
94 class RegisterClassInfo;
95 class ScheduleDAGInstrs;
97 class ScheduleHazardRecognizer;
99 /// MachineSchedContext provides enough context from the MachineScheduler pass
100 /// for the target to instantiate a scheduler.
101 struct MachineSchedContext {
103 const MachineLoopInfo *MLI;
104 const MachineDominatorTree *MDT;
105 const TargetPassConfig *PassConfig;
109 RegisterClassInfo *RegClassInfo;
111 MachineSchedContext();
112 virtual ~MachineSchedContext();
115 /// MachineSchedRegistry provides a selection of available machine instruction
117 class MachineSchedRegistry : public MachinePassRegistryNode {
119 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
121 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
122 typedef ScheduleDAGCtor FunctionPassCtor;
124 static MachinePassRegistry Registry;
126 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
127 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
130 ~MachineSchedRegistry() { Registry.Remove(this); }
134 MachineSchedRegistry *getNext() const {
135 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
137 static MachineSchedRegistry *getList() {
138 return (MachineSchedRegistry *)Registry.getList();
140 static void setListener(MachinePassRegistryListener *L) {
141 Registry.setListener(L);
147 /// Define a generic scheduling policy for targets that don't provide their own
148 /// MachineSchedStrategy. This can be overriden for each scheduling region
149 /// before building the DAG.
150 struct MachineSchedPolicy {
151 // Allow the scheduler to disable register pressure tracking.
152 bool ShouldTrackPressure;
154 // Allow the scheduler to force top-down or bottom-up scheduling. If neither
155 // is true, the scheduler runs in both directions and converges.
159 // Disable heuristic that tries to fetch nodes from long dependency chains
161 bool DisableLatencyHeuristic;
163 MachineSchedPolicy(): ShouldTrackPressure(false), OnlyTopDown(false),
164 OnlyBottomUp(false), DisableLatencyHeuristic(false) {}
167 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
170 /// Initialization sequence:
171 /// initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
172 class MachineSchedStrategy {
173 virtual void anchor();
175 virtual ~MachineSchedStrategy() {}
177 /// Optionally override the per-region scheduling policy.
178 virtual void initPolicy(MachineBasicBlock::iterator Begin,
179 MachineBasicBlock::iterator End,
180 unsigned NumRegionInstrs) {}
182 virtual void dumpPolicy() {}
184 /// Check if pressure tracking is needed before building the DAG and
185 /// initializing this strategy. Called after initPolicy.
186 virtual bool shouldTrackPressure() const { return true; }
188 /// Initialize the strategy after building the DAG for a new region.
189 virtual void initialize(ScheduleDAGMI *DAG) = 0;
191 /// Notify this strategy that all roots have been released (including those
192 /// that depend on EntrySU or ExitSU).
193 virtual void registerRoots() {}
195 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
196 /// schedule the node at the top of the unscheduled region. Otherwise it will
197 /// be scheduled at the bottom.
198 virtual SUnit *pickNode(bool &IsTopNode) = 0;
200 /// \brief Scheduler callback to notify that a new subtree is scheduled.
201 virtual void scheduleTree(unsigned SubtreeID) {}
203 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
204 /// instruction and updated scheduled/remaining flags in the DAG nodes.
205 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
207 /// When all predecessor dependencies have been resolved, free this node for
208 /// top-down scheduling.
209 virtual void releaseTopNode(SUnit *SU) = 0;
210 /// When all successor dependencies have been resolved, free this node for
211 /// bottom-up scheduling.
212 virtual void releaseBottomNode(SUnit *SU) = 0;
215 /// Mutate the DAG as a postpass after normal DAG building.
216 class ScheduleDAGMutation {
217 virtual void anchor();
219 virtual ~ScheduleDAGMutation() {}
221 virtual void apply(ScheduleDAGMI *DAG) = 0;
224 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
225 /// schedules machine instructions according to the given MachineSchedStrategy
226 /// without much extra book-keeping. This is the common functionality between
227 /// PreRA and PostRA MachineScheduler.
228 class ScheduleDAGMI : public ScheduleDAGInstrs {
231 std::unique_ptr<MachineSchedStrategy> SchedImpl;
233 /// Topo - A topological ordering for SUnits which permits fast IsReachable
234 /// and similar queries.
235 ScheduleDAGTopologicalSort Topo;
237 /// Ordered list of DAG postprocessing steps.
238 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
240 /// The top of the unscheduled zone.
241 MachineBasicBlock::iterator CurrentTop;
243 /// The bottom of the unscheduled zone.
244 MachineBasicBlock::iterator CurrentBottom;
246 /// Record the next node in a scheduled cluster.
247 const SUnit *NextClusterPred;
248 const SUnit *NextClusterSucc;
251 /// The number of instructions scheduled so far. Used to cut off the
252 /// scheduler at the point determined by misched-cutoff.
253 unsigned NumInstrsScheduled;
256 ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
257 bool RemoveKillFlags)
258 : ScheduleDAGInstrs(*C->MF, C->MLI, C->LIS, RemoveKillFlags),
259 AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
260 CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
262 NumInstrsScheduled = 0;
266 // Provide a vtable anchor
267 ~ScheduleDAGMI() override;
269 /// Return true if this DAG supports VReg liveness and RegPressure.
270 virtual bool hasVRegLiveness() const { return false; }
272 /// Add a postprocessing step to the DAG builder.
273 /// Mutations are applied in the order that they are added after normal DAG
274 /// building and before MachineSchedStrategy initialization.
276 /// ScheduleDAGMI takes ownership of the Mutation object.
277 void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
278 Mutations.push_back(std::move(Mutation));
281 /// \brief True if an edge can be added from PredSU to SuccSU without creating
283 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
285 /// \brief Add a DAG edge to the given SU with the given predecessor
288 /// \returns true if the edge may be added without creating a cycle OR if an
289 /// equivalent edge already existed (false indicates failure).
290 bool addEdge(SUnit *SuccSU, const SDep &PredDep);
292 MachineBasicBlock::iterator top() const { return CurrentTop; }
293 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
295 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
296 /// region. This covers all instructions in a block, while schedule() may only
298 void enterRegion(MachineBasicBlock *bb,
299 MachineBasicBlock::iterator begin,
300 MachineBasicBlock::iterator end,
301 unsigned regioninstrs) override;
303 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
304 /// reorderable instructions.
305 void schedule() override;
307 /// Change the position of an instruction within the basic block and update
308 /// live ranges and region boundary iterators.
309 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
311 const SUnit *getNextClusterPred() const { return NextClusterPred; }
313 const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
315 void viewGraph(const Twine &Name, const Twine &Title) override;
316 void viewGraph() override;
319 // Top-Level entry points for the schedule() driver...
321 /// Apply each ScheduleDAGMutation step in order. This allows different
322 /// instances of ScheduleDAGMI to perform custom DAG postprocessing.
323 void postprocessDAG();
325 /// Release ExitSU predecessors and setup scheduler queues.
326 void initQueues(ArrayRef<SUnit*> TopRoots, ArrayRef<SUnit*> BotRoots);
328 /// Update scheduler DAG and queues after scheduling an instruction.
329 void updateQueues(SUnit *SU, bool IsTopNode);
331 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
332 void placeDebugValues();
334 /// \brief dump the scheduled Sequence.
335 void dumpSchedule() const;
338 bool checkSchedLimit();
340 void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
341 SmallVectorImpl<SUnit*> &BotRoots);
343 void releaseSucc(SUnit *SU, SDep *SuccEdge);
344 void releaseSuccessors(SUnit *SU);
345 void releasePred(SUnit *SU, SDep *PredEdge);
346 void releasePredecessors(SUnit *SU);
349 /// ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules
350 /// machine instructions while updating LiveIntervals and tracking regpressure.
351 class ScheduleDAGMILive : public ScheduleDAGMI {
353 RegisterClassInfo *RegClassInfo;
355 /// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
357 SchedDFSResult *DFSResult;
358 BitVector ScheduledTrees;
360 MachineBasicBlock::iterator LiveRegionEnd;
362 // Map each SU to its summary of pressure changes. This array is updated for
363 // liveness during bottom-up scheduling. Top-down scheduling may proceed but
364 // has no affect on the pressure diffs.
365 PressureDiffs SUPressureDiffs;
367 /// Register pressure in this region computed by initRegPressure.
368 bool ShouldTrackPressure;
369 IntervalPressure RegPressure;
370 RegPressureTracker RPTracker;
372 /// List of pressure sets that exceed the target's pressure limit before
373 /// scheduling, listed in increasing set ID order. Each pressure set is paired
374 /// with its max pressure in the currently scheduled regions.
375 std::vector<PressureChange> RegionCriticalPSets;
377 /// The top of the unscheduled zone.
378 IntervalPressure TopPressure;
379 RegPressureTracker TopRPTracker;
381 /// The bottom of the unscheduled zone.
382 IntervalPressure BotPressure;
383 RegPressureTracker BotRPTracker;
386 ScheduleDAGMILive(MachineSchedContext *C,
387 std::unique_ptr<MachineSchedStrategy> S)
388 : ScheduleDAGMI(C, std::move(S), /*RemoveKillFlags=*/false),
389 RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
390 ShouldTrackPressure(false), RPTracker(RegPressure),
391 TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}
393 ~ScheduleDAGMILive() override;
395 /// Return true if this DAG supports VReg liveness and RegPressure.
396 bool hasVRegLiveness() const override { return true; }
398 /// \brief Return true if register pressure tracking is enabled.
399 bool isTrackingPressure() const { return ShouldTrackPressure; }
401 /// Get current register pressure for the top scheduled instructions.
402 const IntervalPressure &getTopPressure() const { return TopPressure; }
403 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
405 /// Get current register pressure for the bottom scheduled instructions.
406 const IntervalPressure &getBotPressure() const { return BotPressure; }
407 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
409 /// Get register pressure for the entire scheduling region before scheduling.
410 const IntervalPressure &getRegPressure() const { return RegPressure; }
412 const std::vector<PressureChange> &getRegionCriticalPSets() const {
413 return RegionCriticalPSets;
416 PressureDiff &getPressureDiff(const SUnit *SU) {
417 return SUPressureDiffs[SU->NodeNum];
420 /// Compute a DFSResult after DAG building is complete, and before any
421 /// queue comparisons.
422 void computeDFSResult();
424 /// Return a non-null DFS result if the scheduling strategy initialized it.
425 const SchedDFSResult *getDFSResult() const { return DFSResult; }
427 BitVector &getScheduledTrees() { return ScheduledTrees; }
429 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
430 /// region. This covers all instructions in a block, while schedule() may only
432 void enterRegion(MachineBasicBlock *bb,
433 MachineBasicBlock::iterator begin,
434 MachineBasicBlock::iterator end,
435 unsigned regioninstrs) override;
437 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
438 /// reorderable instructions.
439 void schedule() override;
441 /// Compute the cyclic critical path through the DAG.
442 unsigned computeCyclicCriticalPath();
445 // Top-Level entry points for the schedule() driver...
447 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
448 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
449 /// region, TopTracker and BottomTracker will be initialized to the top and
450 /// bottom of the DAG region without covereing any unscheduled instruction.
451 void buildDAGWithRegPressure();
453 /// Move an instruction and update register pressure.
454 void scheduleMI(SUnit *SU, bool IsTopNode);
458 void initRegPressure();
460 void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
462 void updateScheduledPressure(const SUnit *SU,
463 const std::vector<unsigned> &NewMaxPressure);
466 //===----------------------------------------------------------------------===//
468 /// Helpers for implementing custom MachineSchedStrategy classes. These take
469 /// care of the book-keeping associated with list scheduling heuristics.
471 //===----------------------------------------------------------------------===//
473 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
474 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
475 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
477 /// This is a convenience class that may be used by implementations of
478 /// MachineSchedStrategy.
482 std::vector<SUnit*> Queue;
485 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
487 unsigned getID() const { return ID; }
489 StringRef getName() const { return Name; }
491 // SU is in this queue if it's NodeQueueID is a superset of this ID.
492 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
494 bool empty() const { return Queue.empty(); }
496 void clear() { Queue.clear(); }
498 unsigned size() const { return Queue.size(); }
500 typedef std::vector<SUnit*>::iterator iterator;
502 iterator begin() { return Queue.begin(); }
504 iterator end() { return Queue.end(); }
506 ArrayRef<SUnit*> elements() { return Queue; }
508 iterator find(SUnit *SU) {
509 return std::find(Queue.begin(), Queue.end(), SU);
512 void push(SUnit *SU) {
514 SU->NodeQueueId |= ID;
517 iterator remove(iterator I) {
518 (*I)->NodeQueueId &= ~ID;
520 unsigned idx = I - Queue.begin();
522 return Queue.begin() + idx;
528 /// Summarize the unscheduled region.
529 struct SchedRemainder {
530 // Critical path through the DAG in expected latency.
531 unsigned CriticalPath;
532 unsigned CyclicCritPath;
534 // Scaled count of micro-ops left to schedule.
535 unsigned RemIssueCount;
537 bool IsAcyclicLatencyLimited;
539 // Unscheduled resources
540 SmallVector<unsigned, 16> RemainingCounts;
546 IsAcyclicLatencyLimited = false;
547 RemainingCounts.clear();
550 SchedRemainder() { reset(); }
552 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
555 /// Each Scheduling boundary is associated with ready queues. It tracks the
556 /// current cycle in the direction of movement, and maintains the state
557 /// of "hazards" and other interlocks at the current cycle.
558 class SchedBoundary {
560 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
568 const TargetSchedModel *SchedModel;
571 ReadyQueue Available;
574 ScheduleHazardRecognizer *HazardRec;
577 /// True if the pending Q should be checked/updated before scheduling another
581 // For heuristics, keep a list of the nodes that immediately depend on the
582 // most recently scheduled node.
583 SmallPtrSet<const SUnit*, 8> NextSUs;
585 /// Number of cycles it takes to issue the instructions scheduled in this
586 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
590 /// Micro-ops issued in the current cycle
593 /// MinReadyCycle - Cycle of the soonest available instruction.
594 unsigned MinReadyCycle;
596 // The expected latency of the critical path in this scheduled zone.
597 unsigned ExpectedLatency;
599 // The latency of dependence chains leading into this zone.
600 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
601 // For each cycle scheduled: DLat -= 1.
602 unsigned DependentLatency;
604 /// Count the scheduled (issued) micro-ops that can be retired by
605 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
606 unsigned RetiredMOps;
608 // Count scheduled resources that have been executed. Resources are
609 // considered executed if they become ready in the time that it takes to
610 // saturate any resource including the one in question. Counts are scaled
611 // for direct comparison with other resources. Counts can be compared with
612 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
613 SmallVector<unsigned, 16> ExecutedResCounts;
615 /// Cache the max count for a single resource.
616 unsigned MaxExecutedResCount;
618 // Cache the critical resources ID in this scheduled zone.
619 unsigned ZoneCritResIdx;
621 // Is the scheduled region resource limited vs. latency limited.
622 bool IsResourceLimited;
624 // Record the highest cycle at which each resource has been reserved by a
625 // scheduled instruction.
626 SmallVector<unsigned, 16> ReservedCycles;
629 // Remember the greatest possible stall as an upper bound on the number of
630 // times we should retry the pending queue because of a hazard.
631 unsigned MaxObservedStall;
635 /// Pending queues extend the ready queues with the same ID and the
637 SchedBoundary(unsigned ID, const Twine &Name):
638 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
639 Pending(ID << LogMaxQID, Name+".P"),
648 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
649 SchedRemainder *rem);
652 return Available.getID() == TopQID;
655 /// Number of cycles to issue the instructions scheduled in this zone.
656 unsigned getCurrCycle() const { return CurrCycle; }
658 /// Micro-ops issued in the current cycle
659 unsigned getCurrMOps() const { return CurrMOps; }
661 /// Return true if the given SU is used by the most recently scheduled
663 bool isNextSU(const SUnit *SU) const { return NextSUs.count(SU); }
665 // The latency of dependence chains leading into this zone.
666 unsigned getDependentLatency() const { return DependentLatency; }
668 /// Get the number of latency cycles "covered" by the scheduled
669 /// instructions. This is the larger of the critical path within the zone
670 /// and the number of cycles required to issue the instructions.
671 unsigned getScheduledLatency() const {
672 return std::max(ExpectedLatency, CurrCycle);
675 unsigned getUnscheduledLatency(SUnit *SU) const {
676 return isTop() ? SU->getHeight() : SU->getDepth();
679 unsigned getResourceCount(unsigned ResIdx) const {
680 return ExecutedResCounts[ResIdx];
683 /// Get the scaled count of scheduled micro-ops and resources, including
684 /// executed resources.
685 unsigned getCriticalCount() const {
687 return RetiredMOps * SchedModel->getMicroOpFactor();
688 return getResourceCount(ZoneCritResIdx);
691 /// Get a scaled count for the minimum execution time of the scheduled
692 /// micro-ops that are ready to execute by getExecutedCount. Notice the
694 unsigned getExecutedCount() const {
695 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
696 MaxExecutedResCount);
699 unsigned getZoneCritResIdx() const { return ZoneCritResIdx; }
701 // Is the scheduled region resource limited vs. latency limited.
702 bool isResourceLimited() const { return IsResourceLimited; }
704 /// Get the difference between the given SUnit's ready time and the current
706 unsigned getLatencyStallCycles(SUnit *SU);
708 unsigned getNextResourceCycle(unsigned PIdx, unsigned Cycles);
710 bool checkHazard(SUnit *SU);
712 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
714 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
716 void releaseNode(SUnit *SU, unsigned ReadyCycle);
718 void releaseTopNode(SUnit *SU);
720 void releaseBottomNode(SUnit *SU);
722 void bumpCycle(unsigned NextCycle);
724 void incExecutedResources(unsigned PIdx, unsigned Count);
726 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
728 void bumpNode(SUnit *SU);
730 void releasePending();
732 void removeReady(SUnit *SU);
734 /// Call this before applying any other heuristics to the Available queue.
735 /// Updates the Available/Pending Q's if necessary and returns the single
736 /// available instruction, or NULL if there are multiple candidates.
737 SUnit *pickOnlyChoice();
740 void dumpScheduledState();
744 /// Base class for GenericScheduler. This class maintains information about
745 /// scheduling candidates based on TargetSchedModel making it easy to implement
746 /// heuristics for either preRA or postRA scheduling.
747 class GenericSchedulerBase : public MachineSchedStrategy {
749 /// Represent the type of SchedCandidate found within a single queue.
750 /// pickNodeBidirectional depends on these listed by decreasing priority.
752 NoCand, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, RegMax,
753 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
754 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
757 static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
760 /// Policy for scheduling the next instruction in the candidate's zone.
763 unsigned ReduceResIdx;
764 unsigned DemandResIdx;
766 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
769 /// Status of an instruction's critical resource consumption.
770 struct SchedResourceDelta {
771 // Count critical resources in the scheduled region required by SU.
772 unsigned CritResources;
774 // Count critical resources from another region consumed by SU.
775 unsigned DemandedResources;
777 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
779 bool operator==(const SchedResourceDelta &RHS) const {
780 return CritResources == RHS.CritResources
781 && DemandedResources == RHS.DemandedResources;
783 bool operator!=(const SchedResourceDelta &RHS) const {
784 return !operator==(RHS);
788 /// Store the state used by GenericScheduler heuristics, required for the
789 /// lifetime of one invocation of pickNode().
790 struct SchedCandidate {
793 // The best SUnit candidate.
796 // The reason for this candidate.
799 // Set of reasons that apply to multiple candidates.
800 uint32_t RepeatReasonSet;
802 // Register pressure values for the best candidate.
803 RegPressureDelta RPDelta;
805 // Critical resource consumption of the best candidate.
806 SchedResourceDelta ResDelta;
808 SchedCandidate(const CandPolicy &policy)
809 : Policy(policy), SU(nullptr), Reason(NoCand), RepeatReasonSet(0) {}
811 bool isValid() const { return SU; }
813 // Copy the status of another candidate without changing policy.
814 void setBest(SchedCandidate &Best) {
815 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
817 Reason = Best.Reason;
818 RPDelta = Best.RPDelta;
819 ResDelta = Best.ResDelta;
822 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
823 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
825 void initResourceDelta(const ScheduleDAGMI *DAG,
826 const TargetSchedModel *SchedModel);
830 const MachineSchedContext *Context;
831 const TargetSchedModel *SchedModel;
832 const TargetRegisterInfo *TRI;
836 GenericSchedulerBase(const MachineSchedContext *C):
837 Context(C), SchedModel(nullptr), TRI(nullptr) {}
839 void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
840 SchedBoundary *OtherZone);
843 void traceCandidate(const SchedCandidate &Cand);
847 /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
849 class GenericScheduler : public GenericSchedulerBase {
850 ScheduleDAGMILive *DAG;
852 // State of the top and bottom scheduled instruction boundaries.
856 MachineSchedPolicy RegionPolicy;
858 GenericScheduler(const MachineSchedContext *C):
859 GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
860 Bot(SchedBoundary::BotQID, "BotQ") {}
862 void initPolicy(MachineBasicBlock::iterator Begin,
863 MachineBasicBlock::iterator End,
864 unsigned NumRegionInstrs) override;
866 void dumpPolicy() override;
868 bool shouldTrackPressure() const override {
869 return RegionPolicy.ShouldTrackPressure;
872 void initialize(ScheduleDAGMI *dag) override;
874 SUnit *pickNode(bool &IsTopNode) override;
876 void schedNode(SUnit *SU, bool IsTopNode) override;
878 void releaseTopNode(SUnit *SU) override {
879 Top.releaseTopNode(SU);
882 void releaseBottomNode(SUnit *SU) override {
883 Bot.releaseBottomNode(SU);
886 void registerRoots() override;
889 void checkAcyclicLatency();
891 void tryCandidate(SchedCandidate &Cand,
892 SchedCandidate &TryCand,
894 const RegPressureTracker &RPTracker,
895 RegPressureTracker &TempTracker);
897 SUnit *pickNodeBidirectional(bool &IsTopNode);
899 void pickNodeFromQueue(SchedBoundary &Zone,
900 const RegPressureTracker &RPTracker,
901 SchedCandidate &Candidate);
903 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
906 /// PostGenericScheduler - Interface to the scheduling algorithm used by
909 /// Callbacks from ScheduleDAGMI:
910 /// initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
911 class PostGenericScheduler : public GenericSchedulerBase {
914 SmallVector<SUnit*, 8> BotRoots;
916 PostGenericScheduler(const MachineSchedContext *C):
917 GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ") {}
919 ~PostGenericScheduler() override {}
921 void initPolicy(MachineBasicBlock::iterator Begin,
922 MachineBasicBlock::iterator End,
923 unsigned NumRegionInstrs) override {
924 /* no configurable policy */
927 /// PostRA scheduling does not track pressure.
928 bool shouldTrackPressure() const override { return false; }
930 void initialize(ScheduleDAGMI *Dag) override;
932 void registerRoots() override;
934 SUnit *pickNode(bool &IsTopNode) override;
936 void scheduleTree(unsigned SubtreeID) override {
937 llvm_unreachable("PostRA scheduler does not support subtree analysis.");
940 void schedNode(SUnit *SU, bool IsTopNode) override;
942 void releaseTopNode(SUnit *SU) override {
943 Top.releaseTopNode(SU);
946 // Only called for roots.
947 void releaseBottomNode(SUnit *SU) override {
948 BotRoots.push_back(SU);
952 void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
954 void pickNodeFromQueue(SchedCandidate &Cand);